CN102840919A - Parallel-serial conversion circuit for reading circuit of infrared focal plane array detector - Google Patents

Parallel-serial conversion circuit for reading circuit of infrared focal plane array detector Download PDF

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CN102840919A
CN102840919A CN201210334074XA CN201210334074A CN102840919A CN 102840919 A CN102840919 A CN 102840919A CN 201210334074X A CN201210334074X A CN 201210334074XA CN 201210334074 A CN201210334074 A CN 201210334074A CN 102840919 A CN102840919 A CN 102840919A
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data storage
output
flip
connected
input
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CN102840919B (en
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吕坚
周云
杜一颖
阙隆成
庹涛
魏林海
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电子科技大学
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Abstract

The embodiment of the invention discloses a parallel-serial conversion circuit for a reading circuit of an infrared focal plane array detector. The parallel-serial conversion circuit comprises a data storage circuit and a conversion output control circuit, wherein the data storage circuit comprises N data storage units, wherein the N is an integer greater than or equal to 2; each data storage unit comprises a data input end, a control signal input end and a data output end; the data output ends of each of the N data storage units are connected together; the conversion output control circuit comprises N control signal output ends; and each control signal output end is connected to the control signal input end of each of the N data storage units. According to the parallel-serial conversion circuit disclosed by the embodiment of the invention, data stored in each storage unit remain unchanged during the parallel-serial conversion progress till all data are output serially, so that transmission of data among the storage units during conversion of a traditional parallel-serial conversion circuit is eliminated, as a result, power consumption is reduced.

Description

红外焦平面阵列探测器读出电路的并串转换电路 Infrared detector focal plane array readout circuit of the parallel-serial conversion circuit

技术领域 FIELD

[0001] 本发明涉及红外焦平面阵列探测器领域,尤其是涉及一种红外焦平面阵列探测器读出电路的并串转换电路。 [0001] The present invention relates to an infrared focal plane array detector, and more particularly, to an infrared detector focal plane array readout circuit parallel-serial conversion circuit.

背景技术 Background technique

[0002] 根据普朗克辐射定理,任何温度高于绝对零度的物体,其内部都会发生分子热运动,从而产生波长不等的红外辐射。 [0002] According to the Planck radiation theorem, any temperature above absolute zero objects, the internal thermal motion of molecules occurs, resulting in a wavelength ranging from infrared radiation. 红外辐射具有强度和波长直接与物体表面温度有关的重要特征,提供了物体的丰富的信息。 Infrared radiation having a wavelength and intensity important features directly related to the surface temperature, provides a wealth of information of the object. 但是红外辐射是一种不可见的电磁波,利用红外辐射来获取物体的信息的时候,需要将这种红外辐射转换为可测量的信号。 However, an invisible infrared radiation is electromagnetic waves, using infrared radiation to obtain information of an object, the need for such infrared radiation into a measurable signal.

[0003] 红外焦平面阵列探测器就是将红外辐射转换成可测量的信号的装置。 [0003] is an infrared focal plane array detector converts infrared radiation into a signal measurable. 红外焦平面阵列探测器通过光电转换、电信号处理等手段将目标物体的温度分布转换成视频图像,其具有抗干扰能力强、隐蔽性能好、跟踪和制导精度高等优点,在军事和民用领域获得了广泛的应用。 An infrared focal plane array detector by photoelectric conversion, electrical signal processing means for converting the temperature distribution of the target object into a video image, which has strong anti-interference ability, good hiding performance, high precision tracking and guidance, in the field of military and civilian a wide range of applications.

[0004] 但是红外焦平面阵列探测器在工作温度较高时,其本身固有的热激发过程会快速增加,从而使得暗电流和噪声迅速上升,会极大地降低红外焦平面阵列探测器的性能,所以需要制冷设备使其工作在低温环境下。 [0004] However, an infrared focal plane array detector at higher operating temperatures, its inherent thermal excitation process rapidly increases, so that the rapid increase in the dark current and noise, can significantly degrade the performance of an infrared focal plane array detectors, Therefore, the low temperature refrigeration equipment needed to make it work in. 但是由于制冷设备的存在,使得探测系统在体积、重量、功耗和成本方面都大量增加,从而增加了它应用的困难性。 However, due to the refrigeration apparatus, so that the detection system are a significant increase in volume, weight, cost and power consumption, thereby increasing the difficulty of its application.

[0005] 随着技术的不断发展,人们提出了非制冷红外焦平面阵列探测器。 [0005] With the continuous development of technology, it has been proposed uncooled infrared focal plane array detector. 非制冷红外焦平面阵列探测器可在常温下工作,无需制冷设备,并具有质量轻、体积小、寿命长、成本低、功耗小、启动快及稳定性好等优点,满足了民用红外系统和部分军事红外系统对长波红外探测器的迫切需要。 Uncooled infrared focal plane array detector may be operated at room temperature without refrigeration equipment, and light weight, small size, long life, low cost, low power consumption, quick start and good stability, infrared systems to meet the civil and some military infrared systems is an urgent need for long-wave infrared detectors. 因而使这项技术得到了快速的发展和广泛的应用。 Thus making this technology has been rapid development and wide application.

[0006] 为了节省面积以及出处口数目,通常非制冷红外焦平面阵列探测器读出电路在输出时会将并行产生的数字输出转换为串行数据输出。 [0006] In order to save area, and source port number, usually readout uncooled infrared focal plane array detector circuit when the output of the digital output will be generated in parallel into serial data output.

[0007] 传统的并串转换电路在数据并行输入以后,存储的数据将在各个存储单元间串行传输,全部直至输出。 [0007] The conventional serial conversion circuit after the data parallel input, serial transmission data stored in each memory cell between all until the output. 串行输出数据时所有的存储单元都有可能发生存储数据的变化,从而产生一定的功耗。 All the memory cells have data stored change may occur when the serial output data to a certain power.

发明内容 SUMMARY

[0008] 本发明的目的之一是提供一种在数据的串并转换中存储的数据在各个存储单元中保持不变从而可以降低功耗的红外焦平面阵列探测器读出电路的并串转换电路。 [0008] One object of the present invention is to provide a serial data and converts the data stored in each memory cell remains unchanged in power consumption can be reduced infrared detector focal plane array readout circuit of the parallel-serial conversion circuit.

[0009] 本发明实施例公开的技术方案包括: [0009] Embodiments of the invention disclosed in the art include:

一种红外焦平面阵列探测器读出电路的并串转换电路,其特征在于,包括:数据存储电路,所述数据存储电路包括N个数据存储单元,其中N为大于或等于2的整数;每个所述数据存储单元包括数据输入端、控制信号输入端和数据输出端,并且所述N个数据存储单元中每个数据存储单元的数据输出端连接到一起;转换输出控制电路,所述转换输出控制电路包括N个控制信号输出端,每个所述控制信号输出端分别连接到所述N个数据存储单元中的一个数据存储单元的控制信号输入端。 An infrared detector focal plane array readout circuit of the parallel-serial conversion circuit comprising: a data storage circuit, a data storage circuit comprising N data storage means, where N is an integer greater than or equal to 2; each the data storage unit includes a data input, a control signal input and a data output terminal, and the data output terminal N data storage units each connected to the data storage unit together; converter output control circuit, said converter the control circuit includes N output control signal output terminal, each of said control signal output terminal respectively connected to the control signal input terminal of a data storage unit of the N data storage unit.

[0010] 进一步地,每个所述数据存储单元包括D触发器和传输门,所述D触发器的输入端连接到所述数据存储单元的数据输入端,所述D触发器的输出端连接到所述传输门的输入端,所述传输门的输出端连接到所述数据存储单元的数据输出端,所述传输门的第一门控信号端连接到所述数据存储单元的控制信号输入端。 [0010] Further, each of said data storage means comprises a transfer gate and a D flip-flop, the D input of flip-flop data input terminal coupled to said data storage unit, the output of the D flip flop to the input of the transmission gate, said transmission gate output is connected to the data output terminal of the data storage unit, the transfer gate control signal to the first gate terminal connected to the data storage unit a control signal input end.

[0011] 进一步地,每个所述数据存储单元还包括缓冲器,所述缓冲器的输入端连接到所述D触发器的输出端,所述缓冲器的输出端连接到所述传输门的输入端。 [0011] Further, each of the data storage unit further comprises a buffer input connected to the output terminal of the D flip-flop, the buffer output connected to the transmission gate input.

[0012] 进一步地,每个所述数据存储单元还包括反相器,所述反相器的输入端连接到所述数据存储单元的控制信号输入端,所述反相器的输出端连接到所述传输门的第二门控信号端。 [0012] Further, each of the data storage unit further includes an inverter, an input terminal of the inverter connected to the control signal input of the data storage unit, the output of the inverter is connected to the the second gating signal terminal of the transfer gate.

[0013] 进一步地,所述转换输出控制电路包括N+1个D触发器和N个与门,所述N+1个D触发器串行连接;每个所述D触发器包括第一D触发器输出端和第二D触发器输出端;每个所述与门包括第一与门输入端、第二与门输入端和与门输出端;其中:第k个与门的第一与门输入端连接到第k个D触发器的第二D触发器输出端;第k个与门的第二与门输入端连接到第k+Ι个D触发器的第一D触发器输出端;第k各个与门的与门输出端连接到所述转换输出控制电路的第k个控制信号输出端;其中k为大于或等于零而小于或等于NI的整数。 [0013] Further, the output control circuit comprises a converter of N + 1 N D flip-flops and AND gates, the N + 1 th D flip-flops serially connected; each of said first D-flipflop comprises a D D flip-flop output and a second output terminal; and each of said first aND gate comprising a gate input, a second aND gate and the gate input terminal and an output terminal; wherein: the k-th and the first aND gate gate input is connected to the k th D flip-flop output terminal of a second D flip flop; k-th aND gate is connected to a second input of aND gate to the first k + Ι D flip-flop output terminal of the first D flip-flop ; each of the k connected to k-th control signal output terminal of said converter circuit and an output control gate and the gate output terminal; wherein k is greater than or equal to zero and less than or equal to an integer NI.

[0014] 进一步地,每个所述D触发器包括相互串联的第一锁存器和第二锁存器,所述第一锁存器的输出端连接到所述D触发器的第一D触发器输出端,所述第二锁存器的输出端连接到所述D触发器的第二D触发器输出端。 [0014] Further, each of the D flip-flops connected in series comprises a first latch and a second latch, an output of the first latch is connected to the first D flip-flop D the output terminal of the flip-flop, the output of the second latch is connected to the second D flip-flop D flip-flop output terminal.

[0015] 进一步地,所述转换输出控制电路还包括时钟输入端,所述时钟输入端连接到时钟源。 [0015] Further, the converter output circuit further includes a clock control input, the clock input connected to the clock source.

[0016] 进一步地,所述转换输出控制电路还包括N分频计数器,所述N分频计数器的输入端连接到所述时钟输入端,所述N分频计数器的输出端连接到所述N个数据存储单元中的每个数据存储单元。 [0016] Further, the output control circuit further includes converting N frequency dividing counter, said N frequency counter input connected to the clock input of the counter N frequency output terminal connected to the N each data storage unit in the data storage unit.

[0017] 本发明的实施例的并串转换电路中,数据并行输入以后,在并串转换过程中存储的数据在各个存储单元中保持不变,直至全部串行输出。 Parallel-serial conversion circuit of this embodiment [0017] of the present invention, after data is input in parallel, in parallel-serial conversion process data stored in the individual memory cells remain unchanged until all the serial output. 这样,消除了传统的并串转换电路串行输出数据时数据在存储单元之间的传输,从而降低了功耗,防止因为功耗增加而使得红外焦平面阵列探测器的温度升高,提高了红外焦平面阵列探测器的性能。 Thus, the need to carry a traditional parallel-serial conversion circuit when the output data of the serial data between the memory cell, thereby reducing power consumption, increasing power consumption so as to prevent infrared focal plane array detector temperature, improved performance of infrared focal plane array detector.

附图说明 BRIEF DESCRIPTION

[0018] 图I是本发明一个实施例的红外焦平面阵列探测器读出电路的并串转换电路的框图不意图; [0018] Figure I is an infrared focal plane array detector to an embodiment of the present invention the readout circuit and block diagram of a serial converter circuit is not intended;

图2是本发明一个实施例的数据存储电路的示意图; FIG 2 is a schematic view of a data storage circuit according to an embodiment of the present invention;

图3是本发明一个实施例的转换输出控制电路的示意图; 3 is a schematic embodiment of a converter output control circuit of the present invention;

图4是本发明一个实施例的转换输出控制电路的时序示意图。 FIG 4 is a timing diagram of the converter control circuit output example embodiment of the present invention.

具体实施方式 Detailed ways

[0019] 如图I所示,本发明的实施例中,一种红外焦平面阵列探测器读出电路的并串转换电路包括数据存储电路和转换输出控制电路。 [0019] FIG I, an embodiment of the present invention, an infrared detector focal plane array readout circuit of the parallel-serial conversion circuit includes a data storage circuit and converting the output control circuit.

[0020] 数据存储电路包括N个数据存储单元。 [0020] The data storage circuit comprising N data storage means. 这里,“N”是指并串转换电路中的数据存储单元的数量。 Here, "N" is the number of the data storage unit in the parallel-serial conversion circuit. 容易理解,本发明的实施例中,N的值可以根据实际情况的需要而灵活设定,本发明对此不作限制。 Readily understood, embodiments of the present invention, the value of N according to actual needs can be flexibly set, the present invention is not limited to this. 例如,一个实施例中,N可以为大于或等于2的整数。 For example, in one embodiment, N may be an integer greater than or equal to 2.

[0021] 该N个数据存储单元中,每个数据存储单元可以包括数据输入端、控制信号输入端和数据输出端。 [0021] The N data storage units, each data storage unit may include a data input terminal, a control signal input and a data output terminal. 这里,数据输入端用于输入将要进行并串转换的数据。 Here, the data input terminal for inputting data to be subjected to parallel-serial conversion. 在本发明实施例的数据存储电路中,包括N个数据存储单元,每个数据存储单元包括数据输入端,因此该数据存储电路中共包括N个数据输入端,需要并串转换的数据从这N个数据输入端并行地输入。 In the data storage circuit in the embodiment of the present invention, including N data storage units, each data storage cell includes a data input terminal, so that the data storing circuit comprises a CCP N data input terminals, parallel-serial conversion of the data required from N input data input in parallel.

[0022] 类似地,由于数据存储电路包括N个数据存储单元,并且每个数据存储单元包括控制信号输入端和数据输出端,因此该数据存储电路共包括N个控制信号输入端和N个数据输出端。 [0022] Similarly, since the data storage circuit comprising N data storage unit, and each data storage unit comprises a control signal input and a data output terminal, so that the total data storage circuit comprises a control signal input terminal of the N and N data an output terminal. 其中,该N个数据输出端连接到一起,也就是N个数据存储单元中每个数据存储单元的数据输出端连接到一起,作为整个并串转换电路的输出端,存储在数据存储电路中的并行输入的数据在转换输出控制电路(下文详述)的控制下,从该整个并串转换电路的输出端串行地输出。 Wherein the N data output terminals are connected together, that is, the data output terminal N data storage units each connected to the data storage unit together, as a whole, the output terminal of the parallel-serial conversion circuit, data stored in storage circuit under the control of the parallel input data conversion output control circuit (described below), and the entire output from the output terminal of the parallel-serial conversion circuit serially.

[0023] 如图I所示,在图I的实施例中,数据存储电路包括数据存储单元O、数据存储单元I、…、数据存储单元NI,一共N个数据存储单元,数据存储单元O包括数据输入端D〈0>、控制信号输入端κ〈0>和数据输出端,数据存储单元I包括数据输入端D〈l>、控制信号输入端K〈l>和数据输出端,…,数据存储单元NI包括数据输入端D〈N-1>、控制信号输入端K〈N-1>和数据输出端,数据存储单元O、数据存储单元I、…、数据存储单元NI的数据输出端连接在一起形成并串转换电路的输出端OUT。 [0023] FIG. I, in the embodiment of FIG. I, the data storage circuit unit O includes a data storage, a data storage unit I, ..., the NI data storage unit, a total of N data storage means comprises a data storage unit O a data input terminal D <0>, a control signal input terminal κ <0> and a data output terminal, a data storage unit I comprises a data input terminal D <l>, a control signal input terminal K <l> and a data output terminal, ..., the data the storage unit NI comprises a data input terminal D <N-1>, a control signal input terminal K <N-1> and the data output terminal, a data storage unit O, the data storage unit the I, ..., the data output terminal of the data storage unit NI connected together to form a parallel-serial conversion circuit output terminal OUT.

[0024] 转换输出控制电路包括N个控制信号输出端,其中该N个控制信号输出端分别一一对应连接到数据存储电路的N个控制信号输入端,也就是转换输出控制电路的每个控制信号输出端分别连接到该N个数据存储单元中的一个数据存储单元的控制信号输入端。 [0024] The conversion control circuit includes N output control signal output terminal, wherein the control signal output terminal N are correspondingly connected to control signal input terminal of the N data storage circuit, that is, each of the output control circuit controls the converter signal output terminals are connected to a control signal input terminal of a data storage unit of the N data storage unit. 这样,转换输出控制电路输出对应的控制信号到数据存储电路的各个数据存储单元,控制各个数据存储单元按照一定的顺序依次从并串转换电路的输出端OUT输出其存储的数据,从而实现并行输入数据存储电路的数据的串行输出。 Thus, conversion output control output circuit corresponding to the control signal to the data storage circuit of the respective data storage unit, a control output OUT of each data storage unit according to a certain order of the parallel-serial conversion circuit outputs its stored data, so as to achieve parallel input serial output data in the data storage circuit. 这可以通过适当地设置控制信号而实现,例如,适当地设置控制信号的时序、电平等等。 This can be achieved by appropriately setting the control signals, for example, appropriately setting the timing, voltage levels of the control signal and the like. 这里控制信号可以根据实际情况的需要灵活设置,从而控制数据存储电路中的数据存储单元按一定的顺序依次输出其存储的数据,在此不再一一详述。 Here the control signal may be set flexibly according to actual needs, so that the control data storage unit of the memory circuit according to a certain order of output data is stored, which is not reproduced here.

[0025] 本发明的一个实施例中,每个数据存储单元可以包括D触发器和传输门,其中D触发器的输入端连接到该数据存储单元的数据输入端,D触发器的输出端连接到传输门的输入端,传输门的输出端连接到该数据存储单元的数据输出端,传输门的第一门控信号端连接到数据存储单元的控制信号输入端。 [0025] An embodiment of the present invention, each data storage unit may include a transfer gate and a D flip-flop, wherein the flip-flop input terminal D connected to the data input terminal of the data storage unit, is connected to the output of D flip-flop to the input of the transmission gate, the output terminal of the transmission gate connected to the data storage unit of the data output terminal, a first gating signal gate is connected to the end of the transmission data storage unit a control signal input terminal.

[0026] 例如,如图2所示,在图2的实施例中,数据存储单元O包括D触发器DO和传输门T0,其中D触发器DO的输入端连接到数据存储单元O的数据输入端D〈0>,D触发器DO的输出端连接到传输门TO的输入端,传输门TO的输出端连接到数据存储单元O的数据输出端,传输门TO的第一门控信号端连接到数据存储单元O的控制信号输入端K〈0>。 [0026] For example, as shown in the embodiment of FIG. 2, the data storage unit includes a D flip-O DO and transfer gates T0, wherein D flip-flop input terminal DO is connected to the data storage unit of data input 2 O end D <0>, D flip-flop output terminal DO is connected to the tO input of the transmission gate, the transmission gate connected to the output terminal tO of the data output terminal O of the data storage unit, a first transfer gate tO gating signal terminal a control signal input terminal of the data storage unit O K <0>.

[0027] 类似地,数据存储单元I包括D触发器Dl和传输门Tl,其中D触发器Dl的输入端连接到数据存储单元I的数据输入端D〈l>,D触发器Dl的输出端连接到传输门Tl的输入端,传输门Tl的输出端连接到数据存储单元I的数据输出端,传输门Tl的第一门控信号端连接到数据存储单元I的控制信号输入端K〈l>。 [0027] Similarly, the data storage unit includes a D flip-I and Dl transfer gates Tl, wherein the input of D flip-flop Dl is connected to the data storage unit I data input terminal D <l>, the output of the D flip-Dl Tl is connected to the input of the transmission gate, the output terminal of the transfer gate of Tl is connected to the data output terminal of the data storage unit I, first gating signal terminal Tl is connected to the transfer gate control signal input terminal data storage unit I K <l >.

[0028] 依次类推,数据单元2、3、…、k、…、NI可以具有类似的结构,例如,数据存储单元NI包括D触发器D (NI)和传输门T (NI),其中D触发器D (NI)的输入端连接到数据存储单元NI的数据输入端D〈N-1>,D触发器D(NI)的输出端连接到传输门T(NI)的输入端,传输门T(NI)的输出端连接到数据存储单元NI的数据输出端,传输门T(NI)的第一门控信号端连接到数据存储单元NI的控制信号输入端K〈N-1>。 [0028] and so on, the data units 2,3, ..., k, ..., NI can have a similar structure, e.g., the data storage unit includes a D flip-flop D NI (NI) and the transfer gate T (NI), wherein the trigger D device D (NI) input terminal is connected to the data storage unit of the NI data input terminal D <N-1>, D flip-flop D (NI) connected to the output terminal of the transfer gate T (NI) input of the transfer gate T (NI) connected to the output terminal to the data output of the NI data storage unit, the transfer gate T (NI) of the first gating signal terminal is connected to the data storage unit a control signal input terminal NI K <N-1>.

[0029] 本发明的实施例中,每个数据存储单元还可以包括缓冲器,缓冲器的输入端连接到该数据存储单元的D触发器的输出端,缓冲器的输出端连接到该数据存储单元的传输门的输入端。 Example [0029] In the present invention, each data storage unit may further include a buffer, output of the input buffer is connected to the data storage unit of the D flip-flop, the output of the buffer memory connected to the data input of the transfer gate units. 该缓冲器可以增加信号驱动能力。 The buffer may increase the signal drive capability.

[0030] 例如,图2的实施例中,数据存储单元O还可以包括缓冲器B0,缓冲器BO的输入端连接到该数据存储单元O的D触发器DO的输出端,缓冲器BO的输出端连接到该数据存储单元O的传输门TO的输入端。 [0030] For example, the embodiment of FIG. 2, the data storage unit may further comprise O buffer B0, BO is a buffer input connected to the output of the D flip-DO O data storing unit, the output of the buffer BO terminal connected to an input of the transfer gate tO O of the data storage unit.

[0031] 类似地,数据存储单元I还可以包括缓冲器BI,缓冲器BI的输入端连接到该数据存储单元I的D触发器Dl的输出端,缓冲器BI的输出端连接到该数据存储单元I的传输门Tl的输入端。 [0031] Similarly, the data storage unit may further include a buffer I BI, BI input of the buffer is connected to an output terminal of the D flip-Dl data storage unit I, BI output of the buffer store is connected to the data input terminal of the transfer gate unit I Tl.

[0032] 依次类推,数据单元2、3、…、k、…、NI可以具有类似的结构,例如,数据存储单元NI还可以包括缓冲器B (NI),缓冲器B (NI)的输入端连接到该数据存储单元NI的D触发器D(NI)的输出端,缓冲器B(NI)的输出端连接到该数据存储单元NI的传输门T(NI)的输入端。 [0032] and so on, the data units 2,3, ..., k, ..., NI can have a similar structure, e.g., the data storage unit may further comprise a buffer B NI (NI), buffer B (NI) input terminal a data storage unit connected to the D flip-flops D NI (NI) of the output buffer B (NI) is connected to the data output of the memory cell transfer gate T NI (NI) input.

[0033] 本发明的实施例中,每个数据存储单元还可以包括反相器,反相器的输入端连接到该数据存储单元的控制信号输入端,反相器的输出端连接到该数据存储单元的传输门的 Example [0033] In the present invention, each data storage unit may further include an inverter, an input terminal of the inverter is connected to the control signal input terminal, an output terminal of the inverter of the data storage unit connected to the data transfer gate memory cell

第二门控信号端。 Second gating signal terminal.

[0034] 例如,如图2所示,数据存储单元O还可以包括反相器RO,反相器RO的输入端连接到该数据存储单元O的控制信号输入端K〈0>,反相器RO的输出端ΚΒ〈0>连接到该数据存储单元O的传输门TO的第二门控信号端。 [0034] For example, as shown, the data storage unit may further include an inverter O RO, RO input terminal of the inverter is connected to the data storage unit a control signal input terminal O K <0>, the inverter 2 an output terminal RO of ΚΒ <0> is connected to a second terminal of the gating signal O data storing unit of the transfer gate tO.

[0035] 类似地,数据存储单元I还可以包括反相器Rl,反相器Rl的输入端连接到该数据存储单元I的控制信号输入端κ〈1>,反相器Rl的输出端ΚΒ〈1>连接到该数据存储单元I的传输门Tl的第二门控信号端。 [0035] Similarly, the data storage unit may further comprise an inverter I Rl, Rl input terminal of the inverter is connected to the control signal input of the data memory unit I κ <1>, the output of the inverter Rl ΚΒ <1> Tl is connected to the transfer gates to the data storage unit I of the second gating signal terminal.

[0036] 依次类推,数据单元2、3、…、k、…、NI可以具有类似的结构,例如,数据存储单元NI还可以包括反相器R (NI),反相器R (NI)的输入端连接到该数据存储单元NI的控制信号输入端1(〈^1>,反相器1?0-1)的输出端KB〈N-1>连接到该数据存储单元NI的传输门T(NI)的第二门控信号端。 [0036] and so on, the data units 2,3, ..., k, ..., NI can have a similar structure, e.g., the data storage unit may further comprise NI R & lt inverter (NI), R & lt inverter (NI) of an input terminal connected to the data storage unit a control signal input terminal NI 1 (<^ 1>, the inverter 1? 0-1) output terminal KB <N-1> data storage unit connected to the transfer gate T NI (NI) of the second gating signal terminal.

[0037] 如图3所示,本发明的一个实施例中,转换输出控制电路包括N+1个D触发器和N个与门,该N+1个D触发器串行连接;每个D触发器包括第一D触发器输出端和第二D触发器输出端;每个与门包括第一与门输入端、第二与门输入端和与门输出端;其中,转换输出控制电路中各个D触发器和与门的连接关系满足: [0037] As shown in FIG. 3, an embodiment of the present invention, the converter output control circuit comprises a D flip-flop N + 1 and N AND gates, the N + 1 th D flip-flops serially connected; each D a first D flip-flop comprises a second D flip-flop output terminal and the output terminal; each aND gate comprising a first input terminal of an aND gate, second aND gate and the gate input terminal and an output terminal; wherein the control circuit converts the output connection relationship of each D flip-flop and the aND gate is satisfied:

第k个与门的第一与门输入端连接到第k个D触发器的第二D触发器输出端;第k个与门的第二与门输入端连接到第k+1个D触发器的第一D触发器输出端;第1^个与门的与门输出端连接到转换输出控制电路的第k个控制信号输出端;其中k为大于或等于零而小于或等于NI的整数。 K-th AND gate is connected to a first input of gates to the k th D flip-flop output terminal of a second D flip flop; k-th AND gate is connected to a second input of the first gate to the k + 1 th D flip- a first D flip-flop's output terminal; ^ a first aND gate connection to the output terminal of the k-th gate control signal output terminal of the converter output control circuit; wherein k is greater than or equal to zero and less than or equal to an integer of NI.

[0038] 这里,k是表示转换输出控制电路中N+1个D触发器中某一个D触发器的编号变量。 [0038] Here, k is a conversion and output of a control circuit in the N + D flip-flop of a variable number of D flip-flops. 例如,如前文所述,转换输出控制电路中N+1个D触发器串行连接(串联),可以对该N+1个D触发器按照信号传递的方向依次编号为第O个D触发器、第I个D触发器、第2个D触发器、…、第N个D触发器,k可以作为这些D触发器的编号的索引。 For example, as previously described, converting the output control circuit in the N + 1 flip-flops of D connected (in series) may be the N + 1 th D flip-flop in the direction of signal transmission sequentially numbered as O D flip-flop , I, D flip-flop, the second D flip-flop, ..., N-th D flip-flop, k as the index number of the D flip-flop.

[0039] 类似地,其中N个与门也可以用类似的方式编号,即按照信号传递的方向依次编号为第O个与门、第I个与门、第2个与门、…、第NI个与门。 [0039] Similarly, where the N AND gates can also be used in a similar manner numbers, i.e. in the direction of signal transmission sequentially numbered as O AND gates, I-th AND gate, the second AND gates, ..., the NI aND gates. 由于与门将连接到各自对应的D触发器上,因此这里统一使用k作为D触发器和与门的编号的索引,此时,k可以是大于或等于零而小于或等于NI的整数,即k在零和NI之间变化且为整数。 Since the AND gate is connected to the respective corresponding D flip-flops, so herein using uniform index number k as D flip-flops and an AND gate, in which case, k can be greater than or equal to zero and less than or equal to NI integer, i.e., the k varies between zero and NI and is an integer.

[0040] 应当理解,这里的编号是为了方便说明本发明的电路的结构而设定,该编号本身并不是对本发明的特征的限制,本发明的内容应当以其表现出的实质的电路结构为准。 [0040] It should be understood that here is numbered for convenience of explanation of the structure of a circuit according to the present invention is set, the number itself is not a limitation of the features of the present invention, the present invention should exhibit its circuit configuration is substantial quasi.

[0041] 例如,如图3所示,在图3的实施例中,第O个与门And_0的第一与门输入端连接到第O个D触发器DCO的第二D触发器输出端Q02 ;第O个与门And_0的第二与门输入端连接到第I个D触发器DCl的第一D触发器输出端Qll ;第O个与门And_0的与门输出端连接到转换输出控制电路的第O个控制信号输出端K〈0>。 [0041] For example, as shown in the embodiment of FIG. 3, the first connection O 3 and the first input of AND gate AND gate And_0 O to D flip-flops of the DCO output terminal of the second D flip-flop Q02 ; O connection of the second aND gate input of aND gate And_0 to the output terminal of a first D flip-Qll DCl I, D flip-flops; a second aND gate And_0 O connection and an output terminal to a gate output of converter control circuit the first control signal output terminal O K <0>.

[0042] 类似地,第I个与门And_l的第一与门输入端连接到第I个D触发器DCl的第二D触发器输出端Q12 ;第I个与门And_l的第二与门输入端连接到第2个D触发器DC2的第一D触发器输出端Q21 ;第I个与门And_l的与门输出端连接到转换输出控制电路的第I个控制信号输出端K〈l>。 [0042] Similarly, the I-th AND gate is connected to a first input of AND gate And_l to the I-th D flip-flop DCl second D flip-flop output terminal Q12; I-th gate and a second AND gate input And_l terminal is connected to the second D flip-flop DC2 first D flip-flop output terminal Q21 is; I-th gate connected to the gate And_l I-th output terminal to the control signal output terminal of the converter output control circuit K <l>.

[0043] 依次类推,第2个与门、第3个与门、…、第NI个与门的连接关系可以是类似的连接关系,例如,第NI个与门And_ NI的第一与门输入端连接到第N-2个D触发器DC (NI)的第二D触发器输出端Q (NI) 2 ;第NI个与门And_ NI的第二与门输入端连接到第N个D触发器DCN的第一D触发器输出端QNl ;第NI个与门And_ NI的与门输出端连接到转换输出控制电路的第NI个控制信号输出端K〈 N-IX [0043] and so on, and the second door, the third AND gate, ..., NI connection relationship with the first gate connection relationship may be similar, for example, the number NI of the first AND gate input of gate And_ NI terminal connected to the N-2 D flip-flops the DC (NI) of a second D flip-flop output terminal Q (NI) 2; NI connection of the second aND gate input of aND gate And_ NI to the N-th D flip- DCN is a first D flip-flop output terminal QNL; NI connection of aND gate output of aND gate And_ NI NI to a first control signal output of the converter output control circuit K <N-IX

[0044] 本发明的实施例中,每个D触发器可以包括相互串联的第一锁存器和第二锁存器,每个D触发器的第一锁存器的输出端连接到该D触发器的第一D触发器输出端,第二锁存器的输出端连接到该D触发器的第二D触发器输出端。 Example [0044] In the present invention, each of the D flip-flops connected in series may include a first latch and a second latch output terminal of the first D flip-flop of each latch is connected to the D a first D flip-flop output terminal, the output of the second latch is connected to the second D flip-flop D flip-flop output terminal.

[0045] 例如,图3所示的实施例中,第O个D触发器DCO包括第一锁存器LOl和第二锁存器L02,第一锁存器LOl的输出端连接到该第O个D触发器DCO的第一D触发器输出端(图中未显示出),第二锁存器L02的输出端连接到该第O个D触发器的第二D触发器输出端Q02。 [0045] For example, the embodiment shown in Figure 3, a first D flip-flop O DCO lol comprises a first latch and a second latch L02, LOl an output terminal connected to the first latch section O a first D flip-flop output terminal of D flip-flops of the DCO (not show), L02 of the second latch output terminal coupled to the second D flip-flops O a second D flip-flop output terminal Q02.

[0046] 类似地,第I个D触发器DCl包括第一锁存器Lll和第二锁存器L12,第一锁存器Lll的输出端连接到该第I个D触发器DCl的第一D触发器输出端Qll,第二锁存器L12的输出端连接到该第I个D触发器的第二D触发器输出端Q12。 [0046] Similarly, the I-th D flip-flop DCl comprises a first latch and a second latch Lll L12, Lll first latch output terminal coupled to the I-th first D flip-flop DCl D flip-flop output terminal Qll, second latch L12 is connected to the output terminal of the D flip-flop I, a second D flip-flop output terminal Q12.

[0047] 以此类推,第2个D触发器、第3个D触发器、…、第N个D触发器可以具有类似的结构。 [0047] and so on, the second D flip-flop, the D flip-flop 3, ..., N-th D flip-flop may have a similar structure. 例如,第N个D触发器DCN包括第一锁存器LNl和第二锁存器LN2,第一锁存器LNl的输出端连接到该第N个D触发器DCN的第一D触发器输出端QNl,第二锁存器LN2的输出端连接到该第N个D触发器的第二D触发器输出端QN2。 For example, the N-th D flip-flop DCN comprises a first latch and a second latch LNL LN2, LNl first latch output terminal connected to a first output of said first D flip-flop D DCN of the N end QNl, LN2, a second latch output is connected to the N-th D flip-flop output terminal of a second D flip QN2.

[0048] 本发明的实施例中,如图3所示,转换输出控制电路还可以包括时钟输入端CK1,时钟输入端CKI可以连接到时钟源,以为本发明的实施例中的电路提供时钟信号。 Example [0048] In the present invention, shown in Figure 3, the conversion circuit may further include an output control terminal CK1 is a clock input, a clock input connected to a clock source can CKI, embodiments of the present invention to provide a clock signal circuit that . 时钟输入端CKl可以连接到转换输出控制电路中的每个D触发器或者锁存器。 CKl clock input terminal may be connected to each of the D flip-flop or latch converter output control circuit.

[0049] 本发明的实施例中,还可以包括N分频计数器,该N分频计数器的输入端连接到时钟输入端CKl,该N分频计数器的输出端CK2连接到前述的数据存储电路中的N个数据存储单元中的每个数据存储单元,例如,连接到每个数据存储单元中的D触发器上,如图I和图2所示。 [0049] The embodiments of the present invention may further include N-scale counter, the N frequency counter input connected to the clock input CKL, the N-scale counter output terminal CK2 is connected to the data storage circuit N data storage unit in each of the data storage unit, for example, is connected to each data storage unit in the D flip-flops, and I as shown in FIG. 2.

[0050] N分频计数器将主时钟(CKl)作N分频,然后作为数据存储电路的控制时钟(CK2 )。 [0050] The N-scale counter master clock (CKL) for N frequency dividing, and as the data storage circuit control clock (CK2). 这样,通过分频得到的时钟信号CK2可以保证数据存储电路并行读入数据,完成串行输出之后,再进行下一次的并行读入数据,确保并行输入数据的每一位都正确地依次串行输出。 Thus, the clock signal CK2 by dividing the resulting data memory circuit can ensure the parallel read data, after completion of the serial output, then the next time the parallel read data are properly ensure that every sequentially input data serial-parallel output. N分频计数器作为常见电路在此不再赘述。 N-scale counter as a common circuit are not repeated here.

[0051] 图4是本发明一个实施例的转换输出控制电路的输入输出时序信号示意图。 [0051] FIG. 4 is a schematic diagram of the input and output signal switching output timing control circuit embodiment of the embodiment of the present invention. 在启动信号触发转换输出控制电路开始工作之后,在时钟信号CKl的控制下,产生的一系列输出信号如图4所示。 After the start signal triggers the converter output control circuit operates under the control of the clock signal CKl, a series of output signals generated as shown in FIG. 相邻两个D触发器的输出经过与门后,输出信号为数据存储电路的控制信号Κ〈0>Ί(〈Ν-1>,即:第k个D触发器的第二锁存器Lk2的输出(即第k个D触发器的第二D触发器输出端Qk2的输出)与第k+Ι个D触发器的第一锁存器L (k+1) I的输出(即第k+Ι个D触发器的第一D触发器输出端Q(k+1) I的输出)分别作为第k个与门(And_k)的输入,第k个与门(And_k)的输出即是第k个数据存储单元的传输门的控制信号K〈k>。其中k为大于或等于零而小于或等于NI的整数。 Two adjacent D flip-flop outputs through the rear gate, the output signal of the control signal to the data storage circuit Κ <0> Ί (<Ν-1>, namely: a second latch of the k th D flip-flop Lk2 the output (i.e., output of the second D flip-flop k th D flip-flop output terminal Qk2) and the first k + Ι D flip-flops of the first latch (k + 1) I output L (i.e., the k + a first D flip-flop output terminal Q of the D flip-flops iota (k + 1) I output) were used as the k-th aND gates (And_k) input of the k-th aND gates (And_k) that is the output of the first k data transfer gate control signal storage cells K <k>. where k is greater than or equal to zero and less than or equal to an integer NI.

[0052] 由图可知在任意时刻,Κ〈0>Ί(〈Ν-1>中只有一位为有效信号,控制数据存储电路中对应的数据存储单元中的对应的一位数据输出,这样,数据存储单元就依次完成了数据输出,从而实现数据的并行输入、串行输出。所产生的控制信号存在半个时钟的交错,可以保证数据不会错误传输。在控制信号都关闭的半个时钟内数据依靠寄生电容保持,也不会发生错误。从而保证了数据传输的准确性。 [0052] at any time is apparent from FIG, Κ <0> Ί (<Ν-1> Only a valid signal, outputs the control data corresponding to a data storage unit in the corresponding memory circuit, so that, a data storage unit to sequentially output data is completed, in order to achieve parallel input, serial output data. the presence of staggered half a clock signal generated by the control, can not guarantee a data transmission error in the control signal is half a clock are closed rely on to keep the parasitic capacitance in the data, the error does not occur thus ensuring the accuracy of data transmission.

[0053] 本发明的实施例的并串转换电路中,数据并行输入以后,在并串转换过程中存储的数据在各个存储单元中保持不变,直至全部串行输出。 [0053] The parallel-serial conversion circuit according to embodiment of the present invention, after data is input in parallel, in parallel-serial conversion process data stored in the individual memory cells remain unchanged until all the serial output. 这样,消除了传统的并串转换电路串行输出数据时数据在存储单元之间的传输,从而降低了功耗,防止因为功耗增加而使得红外焦平面阵列探测器的温度升高,提高了红外焦平面阵列探测器的性能。 Thus, the need to carry a traditional parallel-serial conversion circuit when the output data of the serial data between the memory cell, thereby reducing power consumption, increasing power consumption so as to prevent infrared focal plane array detector temperature, improved performance of infrared focal plane array detector.

[0054] 以上通过具体的实施例对本发明进行了说明,但本发明并不限于这些具体的实施例。 [0054] carried out by the above specific embodiments of the present invention has been described, but the present invention is not limited to these specific embodiments. 本领域技术人员应该明白,还可以对本发明做各种修改、等同替换、变化等等,这些变换只要未背离本发明的精神,都应在本发明的保护范围之内。 Those skilled in the art should appreciate that the present invention may also be made of various modifications, equivalent substitutions, changes, etc., as long as such changes do not depart from the spirit of the present invention, should fall within the scope of the present invention. 此外,以上多处所述的“一个实施例”表示不同的实施例,当然也可以将其全部或部分结合在一个实施例中。 In addition, many more than "one embodiment" of the representation of different embodiments, of course, also be incorporated in all or part of one embodiment.

Claims (8)

1. 一种红外焦平面阵列探测器读出电路的并串转换电路,其特征在于,包括: 数据存储电路,所述数据存储电路包括N个数据存储单元,其中N为大于或等于2的整数;每个所述数据存储单元包括数据输入端、控制信号输入端和数据输出端,并且所述N个数据存储单元中每个数据存储单元的数据输出端连接到一起; 转换输出控制电路,所述转换输出控制电路包括N个控制信号输出端,每个所述控制信号输出端分别连接到所述N个数据存储单元中的一个数据存储单元的控制信号输入端。 1. An infrared detector focal plane array readout circuit of the parallel-serial conversion circuit comprising: a data storage circuit, a data storage circuit comprising N data storage means, where N is an integer greater than or equal to 2 ; each of said data storage unit includes a data input terminal, a control signal input and a data output terminal, and a data output terminal of the N data storage units each connected to the data storage unit together; converter output control circuit, the converting said output control circuit includes N control signal output terminal, each of said control signal output terminal respectively connected to the control signal input terminal of a data storage unit of the N data storage unit.
2.如权利要求I所述的并串转换电路,其特征在于:每个所述数据存储单元包括D触发器和传输门,所述D触发器的输入端连接到所述数据存储单元的数据输入端,所述D触发器的输出端连接到所述传输门的输入端,所述传输门的输出端连接到所述数据存储单元的数据输出端,所述传输门的第一门控信号端连接到所述数据存储单元的控制信号输入端。 2. I claim the parallel-serial converting circuit, wherein: each of said data storage means comprises a transfer gate and a D flip-flop, the flip-flop D input terminal connected to said data storage unit output of the input terminal D of the flip-flop is connected to an input of the transmission gate, said transmission gate output is connected to the data output of the data storage unit, the transfer gate control signal of the first gate terminal is connected to a control signal input of the data storage unit.
3.如权利要求2所述的并串转换电路,其特征在于:每个所述数据存储单元还包括缓冲器,所述缓冲器的输入端连接到所述D触发器的输出端,所述缓冲器的输出端连接到所述传输门的输入端。 As claimed in claim 2, the parallel-serial converting circuit, wherein: each of said data storage means further comprises a buffer input connected to the output terminal of the D flip-flop, the output of the buffer is connected to an input of the transfer gate.
4.如权利要求2或3所述的并串转换电路,其特征在于:每个所述数据存储单元还包括反相器,所述反相器的输入端连接到所述数据存储单元的控制信号输入端,所述反相器的输出端连接到所述传输门的第二门控信号端。 Each of said data storage control unit further includes an inverter, an input terminal of the inverter connected to the data storage unit: parallel-serial conversion circuit, characterized in that as claimed in claim 2 or 3, signal input terminal, an output terminal of the inverter is connected to said second transmission gate terminal gating signal.
5.如权利要求I所述的并串转换电路,其特征在于:所述转换输出控制电路包括N+1个D触发器和N个与门,所述N+1个D触发器串行连接;每个所述D触发器包括第一D触发器输出端和第二D触发器输出端;每个所述与门包括第一与门输入端、第二与门输入端和与门输出端;其中: 第k个与门的第一与门输入端连接到第k个D触发器的第二D触发器输出端;第k个与门的第二与门输入端连接到第k+Ι个D触发器的第一D触发器输出端;第k个与门的与门输出端连接到所述转换输出控制电路的第k个控制信号输出端;其中k为大于或等于零而小于或等于NI的整数。 5. I claim the parallel-serial converting circuit, wherein: said output control circuit comprises a converter of N + 1 N D flip-flops and AND gates, the N + 1 th D flip-flops serially connected ; each of said first D-flipflop comprises a D flip-flop output and a second output terminal of D flip-flop; and each of said first aND gate comprising a gate input, a second aND gate and the gate input terminal and an output terminal ; wherein: the k-th aND gate is connected to a first input of gates to the k th D flip-flop output terminal of a second D flip flop; k-th aND gate is connected to a second input of aND gate to the first k + Ι a first D flip-flop output terminal of the D flip-flops; k-th and the gate connected to the gate of the k-th output terminal to a control signal output terminal of the output control circuit of the converter; wherein k is greater than or equal to zero and less than or equal to NI is an integer.
6.如权利要求5所述的并串转换电路,其特征在于:每个所述D触发器包括相互串联的第一锁存器和第二锁存器,所述第一锁存器的输出端连接到所述D触发器的第一D触发器输出端,所述第二锁存器的输出端连接到所述D触发器的第二D触发器输出端。 6. The parallel-serial conversion circuit as claimed in claim 5, wherein: each of the D flip-flops connected in series comprises a first latch and a second latch, the output of the first latch terminal connected to the first D flip-flop D flip-flop output terminal, the output of the second latch is connected to the second D flip-flop D flip-flop output terminal.
7.如权利要求I所述的并串转换电路,其特征在于:所述转换输出控制电路还包括时钟输入端,所述时钟输入端连接到时钟源。 I as claimed in claim 7 and said serial converter circuit, wherein: said converter output circuit further includes a clock control input, the clock input connected to the clock source.
8.如权利要求7所述的并串转换电路,其特征在于:所述转换输出控制电路还包括N分频计数器,所述N分频计数器的输入端连接到所述时钟输入端,所述N分频计数器的输出端连接到所述N个数据存储单元中的每个数据存储单元。 Parallel-serial conversion circuit, characterized in that as claimed in claim 7: said output control circuit further comprises a converter coupled to the clock input of divide by N counter, a divide by N counter input, the N-divided output of the counter is connected to each of the N data storage unit in the data storage unit.
CN201210334074.XA 2012-09-12 2012-09-12 Parallel-serial conversion circuit for reading circuit of infrared focal plane array detector CN102840919B (en)

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