CN102840919A - Parallel-serial conversion circuit for reading circuit of infrared focal plane array detector - Google Patents
Parallel-serial conversion circuit for reading circuit of infrared focal plane array detector Download PDFInfo
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- CN102840919A CN102840919A CN201210334074XA CN201210334074A CN102840919A CN 102840919 A CN102840919 A CN 102840919A CN 201210334074X A CN201210334074X A CN 201210334074XA CN 201210334074 A CN201210334074 A CN 201210334074A CN 102840919 A CN102840919 A CN 102840919A
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Abstract
The embodiment of the invention discloses a parallel-serial conversion circuit for a reading circuit of an infrared focal plane array detector. The parallel-serial conversion circuit comprises a data storage circuit and a conversion output control circuit, wherein the data storage circuit comprises N data storage units, wherein the N is an integer greater than or equal to 2; each data storage unit comprises a data input end, a control signal input end and a data output end; the data output ends of each of the N data storage units are connected together; the conversion output control circuit comprises N control signal output ends; and each control signal output end is connected to the control signal input end of each of the N data storage units. According to the parallel-serial conversion circuit disclosed by the embodiment of the invention, data stored in each storage unit remain unchanged during the parallel-serial conversion progress till all data are output serially, so that transmission of data among the storage units during conversion of a traditional parallel-serial conversion circuit is eliminated, as a result, power consumption is reduced.
Description
Technical field
The present invention relates to the infrared focal plane array seeker field, especially relate to a kind of parallel-to-serial converter of infrared focal plane array seeker sensing circuit.
Background technology
According to the planck radiation theorem, any temperature is higher than the object of absolute zero, and its inside all molecular thermalmotion can take place, thereby produces the infrared radiation that wavelength does not wait.Infrared radiation has intensity and the direct key character relevant with the body surface temperature of wavelength, and the abundant information of object is provided.But infrared radiation is a kind of sightless electromagnetic wave, when utilizing infrared radiation to obtain the information of object, need convert this infrared radiation into measurable signal.
Infrared focal plane array seeker is exactly the device that infrared radiation is converted to measurable signal.Infrared focal plane array seeker converts the Temperature Distribution of target object to video image through means such as opto-electronic conversion, electric signal processing; It has good, the TG precision advantages of higher of strong, the hidden performance of antijamming capability, has obtained in the military and civilian field to use widely.
But infrared focal plane array seeker is when working temperature is higher; The quick increase of itself intrinsic thermal excitation process meeting; Thereby make dark current and noise rise rapidly; Can greatly reduce the performance of infrared focal plane array seeker, so need refrigeration plant that it is operated under the low temperature environment.But the existence owing to refrigeration plant makes detection system all roll up aspect volume, weight, power consumption and the cost, thereby has increased the difficulty of its application.
Along with the continuous development of technology, people have proposed non-refrigerate infrared focal plane array seeker.Non-refrigerate infrared focal plane array seeker can be worked at normal temperatures; Need not refrigeration plant; And have light weight, volume is little, the life-span is long, cost is low, power consumption is little, start fast and advantages such as good stability, has satisfied the military infrared system of civilian infrared system and part pressing for Long Wave Infrared Probe.Thereby make this technology obtain development fast and use widely.
In order to save area and source mouth number, the non-refrigerate infrared focal plane array seeker sensing circuit can convert the numeral output of the generation that walks abreast into serial data output when output usually.
Traditional parallel-to-serial converter is after data parallel input, and the data of storage will serial transmission between each storage unit, all until output.Storage unit all during SOD serial output data all might be stored the variation of data, thereby produce certain power consumption.
Summary of the invention
Thereby one of the object of the invention provides in each storage unit, the remain unchanged parallel-to-serial converter of the infrared focal plane array seeker sensing circuit that can reduce power consumption of the data of storage in a kind of string and conversion in data.
The disclosed technical scheme of the embodiment of the invention comprises:
A kind of parallel-to-serial converter of infrared focal plane array seeker sensing circuit is characterized in that, comprising: data storage circuitry, said data storage circuitry comprise N data storage unit, and wherein N is the integer more than or equal to 2; Each said data storage cell comprises data input pin, signal input end and data output end, and the data output end of each data storage cell connects together in said N data storage unit; The conversion output control circuit, said conversion output control circuit comprises N control signal output ends, each said control signal output ends is connected respectively to the signal input end of a said N data storage unit in the data storage unit.
Further; Each said data storage cell comprises d type flip flop and transmission gate; The input end of said d type flip flop is connected to the data input pin of said data storage cell; The output terminal of said d type flip flop is connected to the input end of said transmission gate, and the output terminal of said transmission gate is connected to the data output end of said data storage cell, and the first gate-control signal end of said transmission gate is connected to the signal input end of said data storage cell.
Further, each said data storage cell also comprises impact damper, and the input end of said impact damper is connected to the output terminal of said d type flip flop, and the output terminal of said impact damper is connected to the input end of said transmission gate.
Further, each said data storage cell also comprises phase inverter, and the input end of said phase inverter is connected to the signal input end of said data storage cell, and the output terminal of said phase inverter is connected to the second gate-control signal end of said transmission gate.
Further, said conversion output control circuit comprises N+1 d type flip flop and N and door, and a said N+1 d type flip flop is connected in series; Each said d type flip flop comprises the first d type flip flop output terminal and the second d type flip flop output terminal; Each said and door comprise first with a door input end, second with input end and and gate output terminal; Wherein: first of k and door is connected to the second d type flip flop output terminal of k d type flip flop with an input end; Second of k and door is connected to the first d type flip flop output terminal of k+1 d type flip flop with an input end; K each with door be connected to k control signal output ends of said conversion output control circuit with gate output terminal; Wherein k for more than or equal to zero be less than or equal to N-1 integer.
Further; Each said d type flip flop comprises first latch and second latch of mutual series connection; The output terminal of said first latch is connected to the first d type flip flop output terminal of said d type flip flop, and the output terminal of said second latch is connected to the second d type flip flop output terminal of said d type flip flop.
Further, said conversion output control circuit also comprises input end of clock, and said input end of clock is connected to the clock source.
Further; Said conversion output control circuit also comprises the Fractional-N frequency counter; The input end of said Fractional-N frequency counter is connected to said input end of clock, and the output terminal of said Fractional-N frequency counter is connected to said N each data storage cell in the data storage unit.
In the parallel-to-serial converter of embodiments of the invention, after the data parallel input, and go here and there the data of storing in the transfer process and in each storage unit, remain unchanged, until whole serials outputs.Like this; The transmission of data between storage unit when having eliminated traditional parallel-to-serial converter SOD serial output data; Thereby reduced power consumption, prevented to make the temperature of infrared focal plane array seeker raise, improved the performance of infrared focal plane array seeker because power consumption increases.
Description of drawings
Fig. 1 is the block diagram representation of parallel-to-serial converter of the infrared focal plane array seeker sensing circuit of one embodiment of the invention;
Fig. 2 is the synoptic diagram of the data storage circuitry of one embodiment of the invention;
Fig. 3 is the synoptic diagram of the conversion output control circuit of one embodiment of the invention;
Fig. 4 is the sequential synoptic diagram of the conversion output control circuit of one embodiment of the invention.
Embodiment
As shown in Figure 1, in the embodiments of the invention, a kind of parallel-to-serial converter of infrared focal plane array seeker sensing circuit comprises data storage circuitry and conversion output control circuit.
Data storage circuitry comprises N data storage unit.Here, " N " is meant the quantity of the data storage cell in the parallel-to-serial converter.Understand easily, in the embodiments of the invention, the value of N can be set according to the needs of actual conditions flexibly, and the present invention does not limit this.For example, among the embodiment, N can be for more than or equal to 2 integer.
In this N the data storage unit, each data storage cell can comprise data input pin, signal input end and data output end.Here, data input pin is used for input and will carries out and go here and there data converted.In the data storage circuitry of the embodiment of the invention; Comprise N data storage unit; Each data storage cell comprises data input pin, so comprises N data input end in this data storage circuitry altogether, and the data converted of need and going here and there is imported from this N data input end concurrently.
Similarly, because data storage circuitry comprises N data storage unit, and each data storage cell comprises signal input end and data output end, so this data storage circuitry comprises N signal input end and N data output terminal altogether.Wherein, This N data output terminal connects together; Just the data output end of each data storage cell connects together in N data storage unit; As the output terminal of whole parallel-to-serial converter, the data that are stored in the parallel input in the data storage circuitry are under the control of conversion output control circuit (hereinafter detailed description), from the output terminal serial ground output of this whole parallel-to-serial converter.
As shown in Figure 1; In the embodiment in figure 1; Data storage circuitry comprise data storage cell 0, data storage cell 1 ..., data storage cell N-1; Have N data storage unit altogether; Data storage cell 0 comprises data input pin D < 0 >, signal input end K < 0>and data output end, and data storage cell 1 comprises data input pin D < 1 >, signal input end K < 1>and data output end ... Data storage cell N-1 comprises data input pin D < N-1 >, signal input end K < N-1>and data output end, data storage cell 0, data storage cell 1 ..., data storage cell N-1 data output end be joined together to form the output terminal OUT of parallel-to-serial converter.
The conversion output control circuit comprises N control signal output ends; This N control signal output ends N signal input end of data storage circuitry that connect one to one respectively wherein, each control signal output ends of just changing output control circuit is connected respectively to the signal input end of this a N data storage unit in the data storage unit.Like this; The corresponding control signal of conversion output control circuit output arrives each data storage cell of data storage circuitry; Control each data storage cell and export the data of its storage in a certain order successively from the output terminal OUT of parallel-to-serial converter, thereby realize the serial output of the data of parallel input data memory circuit.This can realize through control signal suitably is set, and for example, sequential, level of control signal or the like is set suitably.Here control signal can be provided with according to the needs of actual conditions flexibly, thereby the data storage cell in the control data memory circuit is exported the data of its storage in sequence successively, details no longer one by one at this.
In one embodiment of the present of invention; Each data storage cell can comprise d type flip flop and transmission gate; Wherein the input end of d type flip flop is connected to the data input pin of this data storage cell; The output terminal of d type flip flop is connected to the input end of transmission gate, and the output terminal of transmission gate is connected to the data output end of this data storage cell, and the first gate-control signal end of transmission gate is connected to the signal input end of data storage cell.
For example; As shown in Figure 2, in the embodiment of Fig. 2, data storage cell 0 comprises d type flip flop D0 and transmission gate T0; Wherein the input end of d type flip flop D0 is connected to the data input pin D < 0>of data storage cell 0; The output terminal of d type flip flop D0 is connected to the input end of transmission gate T0, and the output terminal of transmission gate T0 is connected to the data output end of data storage cell 0, and the first gate-control signal end of transmission gate T0 is connected to the signal input end K < 0>of data storage cell 0.
Similarly; Data storage cell 1 comprises d type flip flop D1 and transmission gate T1; Wherein the input end of d type flip flop D1 is connected to the data input pin D < 1>of data storage cell 1; The output terminal of d type flip flop D1 is connected to the input end of transmission gate T1, and the output terminal of transmission gate T1 is connected to the data output end of data storage cell 1, and the first gate-control signal end of transmission gate T1 is connected to the signal input end K < 1>of data storage cell 1.
And the like; Data cell 2,3 ..., k ..., N-1 can have similar structure; For example; Data storage cell N-1 comprises d type flip flop D (N-1) and transmission gate T (N-1), and wherein the input end of d type flip flop D (N-1) is connected to the data input pin D < N-1>of data storage cell N-1, and the output terminal of d type flip flop D (N-1) is connected to the input end of transmission gate T (N-1); The output terminal of transmission gate T (N-1) is connected to the data output end of data storage cell N-1, and the first gate-control signal end of transmission gate T (N-1) is connected to the signal input end K < N-1>of data storage cell N-1.
In the embodiments of the invention, each data storage cell can also comprise impact damper, and the input end of impact damper is connected to the output terminal of the d type flip flop of this data storage cell, and the output terminal of impact damper is connected to the input end of the transmission gate of this data storage cell.This impact damper can increase the signal driving force.
For example; Among the embodiment of Fig. 2; Data storage cell 0 can also comprise impact damper B0, and the input end of impact damper B0 is connected to the output terminal of the d type flip flop D0 of this data storage cell 0, and the output terminal of impact damper B0 is connected to the input end of the transmission gate T0 of this data storage cell 0.
Similarly, data storage cell 1 can also comprise impact damper B1, and the input end of impact damper B1 is connected to the output terminal of the d type flip flop D1 of this data storage cell 1, and the output terminal of impact damper B1 is connected to the input end of the transmission gate T1 of this data storage cell 1.
And the like; Data cell 2,3 ..., k ..., N-1 can have similar structure; For example; Data storage cell N-1 can also comprise impact damper B (N-1), and the input end of impact damper B (N-1) is connected to the output terminal of the d type flip flop D (N-1) of this data storage cell N-1, and the output terminal of impact damper B (N-1) is connected to the input end of the transmission gate T (N-1) of this data storage cell N-1.
In the embodiments of the invention; Each data storage cell can also comprise phase inverter; The input end of phase inverter is connected to the signal input end of this data storage cell, and the output terminal of phase inverter is connected to the second gate-control signal end of the transmission gate of this data storage cell.
For example; As shown in Figure 2; Data storage cell 0 can also comprise phase inverter R0, and the input end of phase inverter R0 is connected to the signal input end K < 0>of this data storage cell 0, and the output terminal KB < 0>of phase inverter R0 is connected to the second gate-control signal end of the transmission gate T0 of this data storage cell 0.
Similarly; Data storage cell 1 can also comprise phase inverter R1; The input end of phase inverter R1 is connected to the signal input end K < 1>of this data storage cell 1, and the output terminal KB < 1>of phase inverter R1 is connected to the second gate-control signal end of the transmission gate T1 of this data storage cell 1.
And the like; Data cell 2,3 ..., k ..., N-1 can have similar structure; For example; Data storage cell N-1 can also comprise phase inverter R (N-1), and the input end of phase inverter R (N-1) is connected to the signal input end K < N-1>of this data storage cell N-1, and the output terminal KB < N-1>of phase inverter R (N-1) is connected to the second gate-control signal end of the transmission gate T (N-1) of this data storage cell N-1.
As shown in Figure 3, in one embodiment of the present of invention, the conversion output control circuit comprises N+1 d type flip flop and N and door, and this N+1 d type flip flop is connected in series; Each d type flip flop comprises the first d type flip flop output terminal and the second d type flip flop output terminal; Each with door comprise first with a door input end, second with input end and and gate output terminal; Wherein, each d type flip flop and satisfied in the conversion output control circuit with the annexation of door:
First of k and door is connected to the second d type flip flop output terminal of k d type flip flop with an input end; Second of k and door is connected to the first d type flip flop output terminal of k+1 d type flip flop with an input end; K is connected to k control signal output ends changing output control circuit with door with gate output terminal; Wherein k for more than or equal to zero be less than or equal to N-1 integer.
Here, k is the numbering variable of some d type flip flops in N+1 d type flip flop in the expression conversion output control circuit.For example; Of preamble; N+1 d type flip flop (series connection) connected in series in the conversion output control circuit; Can to this N+1 d type flip flop according to the direction number consecutively of signal transmission be the 0th d type flip flop, the 1st d type flip flop, the 2nd d type flip flop ..., a N d type flip flop, k can be used as the index of the numbering of these d type flip flops.
Similarly, wherein N also can use similar mode to number with door, promptly according to the direction number consecutively of signal transmission be the 0th with door, the 1st and door, the 2nd with door ..., N-1 and door.Owing to be connected on each self-corresponding d type flip flop with goalkeeper, therefore unified here use k as d type flip flop and with the index of the numbering of door, at this moment, k can be the integer that is less than or equal to N-1 more than or equal to zero, promptly k changes between zero-sum N-1 and is integer.
Should be appreciated that the numbering here is the structure of circuit of the present invention is described for ease and is set, this numbering itself is not the restriction to characteristic of the present invention, and content of the present invention should be as the criterion with the circuit structure of its essence that shows.
For example, as shown in Figure 3, in the embodiments of figure 3, the 0th is connected to the second d type flip flop output terminal Q02 of the 0th d type flip flop DC0 with first of door And_0 with the door input end; The 0th is connected to the first d type flip flop output terminal Q11 of the 1st d type flip flop DC1 with second of door And_0 with the door input end; The 0th with the door And_0 with gate output terminal be connected to the conversion output control circuit the 0th control signal output ends K < 0 >.
Similarly, the 1st is connected to the second d type flip flop output terminal Q12 of the 1st d type flip flop DC1 with first of door And_1 with the door input end; The 1st is connected to the first d type flip flop output terminal Q21 of the 2nd d type flip flop DC2 with second of door And_1 with the door input end; The 1st with the door And_1 with gate output terminal be connected to the conversion output control circuit the 1st control signal output ends K < 1 >.
And the like; The 2nd with the door, the 3rd with the door ..., N-1 with annexation can be similar annexation; For example, individual first and the input end with door And_ N-1 of N-1 is connected to the second d type flip flop output terminal Q (N-1) 2 of N-2 d type flip flop DC (N-1); N-1 second and an input end with door And_ N-1 is connected to the first d type flip flop output terminal QN1 of N d type flip flop DCN; N-1 is connected to N-1 the control signal output ends K < N-1>that changes output control circuit with door And_ N-1's with gate output terminal.
In the embodiments of the invention; Each d type flip flop can comprise first latch and second latch of mutual series connection; The output terminal of first latch of each d type flip flop is connected to the first d type flip flop output terminal of this d type flip flop, and the output terminal of second latch is connected to the second d type flip flop output terminal of this d type flip flop.
For example; Among the embodiment shown in Figure 3; The 0th d type flip flop DC0 comprises the first latch L01 and the second latch L02; The output terminal of the first latch L01 is connected to the first d type flip flop output terminal (not demonstrating among the figure) of the 0th d type flip flop DC0, and the output terminal of the second latch L02 is connected to the second d type flip flop output terminal Q02 of the 0th d type flip flop.
Similarly; The 1st d type flip flop DC1 comprises the first latch L11 and the second latch L12; The output terminal of the first latch L11 is connected to the first d type flip flop output terminal Q11 of the 1st d type flip flop DC1, and the output terminal of the second latch L12 is connected to the second d type flip flop output terminal Q12 of the 1st d type flip flop.
By that analogy, the 2nd d type flip flop, the 3rd d type flip flop ..., a N d type flip flop can have similar structure.For example; N d type flip flop DCN comprises the first latch LN1 and the second latch LN2; The output terminal of the first latch LN1 is connected to the first d type flip flop output terminal QN1 of this N d type flip flop DCN, and the output terminal of the second latch LN2 is connected to the second d type flip flop output terminal QN2 of this N d type flip flop.
In the embodiments of the invention, as shown in Figure 3, the conversion output control circuit can also comprise input end of clock CK1, and input end of clock CK1 can be connected to the clock source, thinks that the circuit in the embodiments of the invention provides clock signal.Input end of clock CK1 can be connected to each d type flip flop or the latch in the conversion output control circuit.
In the embodiments of the invention; Can also comprise the Fractional-N frequency counter; The input end of this Fractional-N frequency counter is connected to input end of clock CK1, and the output terminal CK2 of this Fractional-N frequency counter is connected to each data storage cell in N the data storage unit in the aforesaid data storage circuitry, for example; Be connected on the d type flip flop in each data storage cell, as depicted in figs. 1 and 2.
The Fractional-N frequency counter is made Fractional-N frequency with major clock (CK1), then as the control clock (CK2) of data storage circuitry.Like this, the clock signal C K2 that obtains through frequency division can guarantee the parallel data of reading in of data storage circuitry, accomplishes after the serial output, carries out the parallel data of reading in next time again, guarantees each all serial output successively correctly of parallel input data.The Fractional-N frequency counter repeats no more at this as circuit common.
Fig. 4 is the input and output clock signal synoptic diagram of the conversion output control circuit of one embodiment of the invention.After enabling signal triggering conversion output control circuit was started working, under the control of clock signal C K1, a series of output signals of generation were as shown in Figure 4.The output of adjacent two d type flip flops through with behind the door; The output signal is control signal K < the 0>~ K < N-1>of data storage circuitry; That is: the output (i.e. the output of the first d type flip flop output terminal Q (k+1) 1 of k+1 d type flip flop) of the first latch L (k+1) 1 of the output of the second latch Lk2 of k d type flip flop (i.e. the output of the second d type flip flop output terminal Qk2 of k d type flip flop) and k+1 d type flip flop is respectively as k the input with door (And_k), and k the output with door (And_k) promptly is the control signal K < k>of the transmission gate of k data storage unit.Wherein k for more than or equal to zero be less than or equal to N-1 integer.
Can know at any time by figure; Have only one to be useful signal among K < 0>~ K < N-1 >; The one digit number of the correspondence in the control data memory circuit in the data storage cell of correspondence is according to output; Like this, data storage cell has just been accomplished data output successively, thereby realizes parallel input, the serial output of data.There is the staggered of half clock in the control signal that is produced, can guarantee that data can erroneous transmissions.Data rely on stray capacitance to keep in half clock that control signal is all closed, and also can not make a mistake.Thereby guaranteed the accuracy of data transmission.
In the parallel-to-serial converter of embodiments of the invention, after the data parallel input, and go here and there the data of storing in the transfer process and in each storage unit, remain unchanged, until whole serials outputs.Like this; The transmission of data between storage unit when having eliminated traditional parallel-to-serial converter SOD serial output data; Thereby reduced power consumption, prevented to make the temperature of infrared focal plane array seeker raise, improved the performance of infrared focal plane array seeker because power consumption increases.
More than describe the present invention through concrete embodiment, but the present invention is not limited to these concrete embodiment.It will be understood by those skilled in the art that and to make various modifications to the present invention, be equal to replacement, change or the like that these conversion all should be within protection scope of the present invention as long as do not deviate from spirit of the present invention.In addition, above many places described " embodiment " representes various embodiment, can certainly be with its all or part of being combined among the embodiment.
Claims (8)
1. the parallel-to-serial converter of an infrared focal plane array seeker sensing circuit is characterized in that, comprising:
Data storage circuitry, said data storage circuitry comprise N data storage unit, and wherein N is the integer more than or equal to 2; Each said data storage cell comprises data input pin, signal input end and data output end, and the data output end of each data storage cell connects together in said N data storage unit;
The conversion output control circuit, said conversion output control circuit comprises N control signal output ends, each said control signal output ends is connected respectively to the signal input end of a said N data storage unit in the data storage unit.
2. parallel-to-serial converter as claimed in claim 1; It is characterized in that: each said data storage cell comprises d type flip flop and transmission gate; The input end of said d type flip flop is connected to the data input pin of said data storage cell; The output terminal of said d type flip flop is connected to the input end of said transmission gate; The output terminal of said transmission gate is connected to the data output end of said data storage cell, and the first gate-control signal end of said transmission gate is connected to the signal input end of said data storage cell.
3. parallel-to-serial converter as claimed in claim 2; It is characterized in that: each said data storage cell also comprises impact damper; The input end of said impact damper is connected to the output terminal of said d type flip flop, and the output terminal of said impact damper is connected to the input end of said transmission gate.
4. like claim 2 or 3 described parallel-to-serial converters; It is characterized in that: each said data storage cell also comprises phase inverter; The input end of said phase inverter is connected to the signal input end of said data storage cell, and the output terminal of said phase inverter is connected to the second gate-control signal end of said transmission gate.
5. parallel-to-serial converter as claimed in claim 1 is characterized in that: said conversion output control circuit comprises N+1 d type flip flop and N and door, and a said N+1 d type flip flop is connected in series; Each said d type flip flop comprises the first d type flip flop output terminal and the second d type flip flop output terminal; Each said and door comprise first with a door input end, second with input end and and gate output terminal; Wherein:
First of k and door is connected to the second d type flip flop output terminal of k d type flip flop with an input end; Second of k and door is connected to the first d type flip flop output terminal of k+1 d type flip flop with an input end; K be connected to k control signal output ends of said conversion output control circuit with gate output terminal; Wherein k for more than or equal to zero be less than or equal to N-1 integer.
6. parallel-to-serial converter as claimed in claim 5; It is characterized in that: each said d type flip flop comprises first latch and second latch of mutual series connection; The output terminal of said first latch is connected to the first d type flip flop output terminal of said d type flip flop, and the output terminal of said second latch is connected to the second d type flip flop output terminal of said d type flip flop.
7. parallel-to-serial converter as claimed in claim 1 is characterized in that: said conversion output control circuit also comprises input end of clock, and said input end of clock is connected to the clock source.
8. parallel-to-serial converter as claimed in claim 7; It is characterized in that: said conversion output control circuit also comprises the Fractional-N frequency counter; The input end of said Fractional-N frequency counter is connected to said input end of clock, and the output terminal of said Fractional-N frequency counter is connected to said N each data storage cell in the data storage unit.
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| CN104458004A (en) * | 2014-11-25 | 2015-03-25 | 中国电子科技集团公司第十一研究所 | Double-spectral-section monolithic integration linear array type infrared focal plane readout circuit and design method |
| CN114401014A (en) * | 2022-01-04 | 2022-04-26 | 电子科技大学 | Low-power-consumption parallel-serial conversion circuit |
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