CN102830127B - Discrete fourier transform (DFT) frequency sampling-based sliver spectrum analysis IP soft core and test method thereof - Google Patents

Abstract

The invention discloses a discrete fourier transform (DFT) frequency sampling-based sliver spectrum analysis IP soft core and a test method thereof. The DFT frequency sampling-based sliver spectrum analysis IP soft core comprises a sliver spectrum analysis computing unit. The sliver spectrum analysis computing unit comprises field programmable gate array (FPGA) device hardware. In the FPGA device hardware, through a HDL language, a DFT frequency sampling-based sliver spectrum analysis algorithm is encapsulated into the DFT frequency sampling-based sliver spectrum analysis IP soft core having 55 channels. The DFT frequency sampling-based sliver spectrum analysis IP soft core having the 55 channels comprises the 55 channels having different center frequency values and different band width values. Each one of the 55 channels comprises a DFT frequency sampling-based IP sub-core and the DFT frequency sampling-based IP sub-core comprises an input module, a state machine, a multiplier, an accumulator module and an output module. The DFT frequency sampling-based sliver spectrum analysis IP soft core can be transplanted into a FPGA device hardware platform through simple configuration, can independently complete a digital sliver signal spectrum analysis task, and has characteristics of strong generality, good portability and high parallel computation real-time property.

Description

The soft core of sliver Spectrum Analysis IP and method of testing thereof based on DFT frequency sampling

Technical field

The invention belongs to textile on-line monitoring and signal handling equipment technical field, relate to a kind of weaving evenness of yarn strip on-line detecting system, be specifically related to a kind of soft core of sliver Spectrum Analysis IP based on DFT frequency sampling, the invention still further relates to the method for testing of the soft core of above-mentioned sliver Spectrum Analysis IP.

Background technology

Yarn unevenness is one of leading indicator of weighing yarn quality, is also the deciding factor that affects fabric appearance quality, and the detection of yarn unevenness is the important means of implementing effective quality control in Spinning process.In textile industry, conventionally adopt Spectra Analysis to detect yarn unevenness, the essence of Spectrum Analysis is spectrum analysis.

In theory, yarn unevenness signal includes countless wavelength, and continuous distribution is in the interval of 0～∞, and the amplitude of each component and phase place are all random harmonic components.Significantly periodically irregular when make sliver produce because of certain mechanical reason, while there is being superimposed on the discrete wavelength component on continuous wave spectrum, the Perfected process addressing this problem is to form and comprise from the wave spectrogram of all wavelengths of 0～∞ in the interval of endless, yet the wave spectrogram of all wavelengths cannot obtain.Owing to being only concerned about the wavelength in a certain particular range in production practices, therefore, in production, wavelength is limited within the scope of this, can greatly reduce the treatment capacity of data.Yet in limited wavelength coverage, on wave spectrogram, still there is unlimited a plurality of point, also need range of wavelengths to divide, limited total wavelength coverage is divided into some groups, be called radio frequency channel (channel), the numerical value of each radio frequency channel, with the class mean representative of one group of wavelength component contained in radio frequency channel, so just forms step-like wave spectrogram.Theoretical and combination reality according to these, Ulster Corporation has proposed the earliest the indirect method of sliver Spectrum Analysis sliver has been carried out to quality testing, be about to the corresponding 0～300Hz frequency range of the main wave spectrum of sliver signal and be divided into 55 channels, the frequency values of these 55 channels is a geometric progression, the upper and lower cutoff frequency of its lowest channel is respectively 0.168Hz and 0.164Hz, the upper and lower cutoff frequency of highest channel is 299.525Hz and 292.393Hz, and the ratio of the resonance frequency between adjacent two channels is allow textile strand bars simultaneously by 55 bandpass filter, the output of each wave filter is recorded to the frequency spectrum profile that just can obtain sliver signal, according to formula λ=υ/f, frequency inverted is become to wavelength again, convert the spectrogram of sliver to wave spectrogram and export and show.Sliver wave spectrogram (spectrogram) is that the various periodicity that can be used to quantitative test Yarn Evenness are irregular at the inner state that characterizes sliver plucked of frequency field (wavelength domain).At present textile industry Zhong Junyi Ulster Corporation is to the limited range of sliver signal wavelength and divide as industry standard.

The method of conventional wave analysis of spectrum has two kinds, first method is the Filtering Analysis method of Uster-II B spectrometer, the simulating signal of directly by many groups analog filter, sliver sensor being sent into is carried out filtering, then filtering result is processed and with the formal output of wave spectrogram.The method needs many group analog filters, and because the required hardware of many group analog filters is complicated, the circuit of the existing Spectrum Analysis of historical facts or anecdotes is complicated, huge, and reliability and stability are difficult to guarantee.Development along with Digital Signal Processing, digital filter has the new features that analog filter cannot replace, for example: digital filter is without drift, can process low frequency signal, its Frequency Response can accomplish to be in close proximity to the characteristic of ideal filter, so digital filter has replaced traditional analog filter and has been widely used in Spectrum Analysis.But no matter be analog filtering method or digital filtering, filter method is all Time Domain Analysis, is indirectly obtaining signal spectrum.Second method is directly to carry out full frequency band Fourier transform after the simulating signal sampling that sliver sensor is sent into, and obtains the frequency domain amplitude of sliver signal, forms spectrogram, then according to corresponding formula, is converted into the formal output of wave spectrogram.This method adopts Fourier transform to obtain the all-channel wave spectrogram of sliver signal, yet the frequency spectrum of the part passage in just this band limits of 0～300Hz that Spectrum Analysis is concerned about, so the frequency spectrum that directly calculates all-channel will exist the calculating of larger a part of gibberish, the time complexity and the space complexity that calculate have greatly been increased.

Summary of the invention

The object of this invention is to provide a kind of soft core of sliver Spectrum Analysis IP based on DFT frequency sampling, the soft core of this sliver Spectrum Analysis IP has highly versatile, real-time is good and develop simple feature.

The technical solution adopted in the present invention is, the soft core of sliver Spectrum Analysis IP based on DFT frequency sampling, include sliver Spectrum Analysis computing unit, sliver Spectrum Analysis computing unit includes FPGA device hardware, in FPGA device hardware, utilizing HDL language is the soft core of 55 passage sliver Spectrum Analysis IP by the sliver Spectrum Analysis algorithm packaging based on DFT frequency sampling, the soft core of 55 passage sliver Spectrum Analysis IP includes centre frequency difference and amount of bandwidth 55 channels not etc., each channel includes a set of IP daughter nucleus based on DFT frequency sampling, IP daughter nucleus includes load module, state machine, two multipliers, two accumulator module and output module, load module includes xvalues module, real part constant coefficient avalues module, imaginary part constant coefficient bvalues module, in state machine, be provided with state_m module, in multiplier, be provided with mult module, accumulator module includes the cumulative accax module of real part and the cumulative accbx module of imaginary part,

Load module is connected with state machine by wire, state machine is respectively by wire and xvalues module, real part constant coefficient avalues module, imaginary part constant coefficient bvalues module connects, real part constant coefficient avalues module is by the mult module in wire and a multiplier, the real part accax module that adds up, a trigger DFFE connects successively, imaginary part constant coefficient bvalues module is by the mult module in wire and another multiplier, the imaginary part accbx module that adds up, another trigger DFFE connects successively, xvalues module is connected respectively with two multipliers by wire.

The detection method of the soft core of sliver Spectrum Analysis IP based on DFT frequency sampling, specifically according to following steps, implement:

Here the first Spectrum Analysis of sliver Spectrum Analysis IP kernel of take is example, and the Spectrum Analysis principle of all the other 54 channels is all identical with the 1st channel with implementation procedure;

Step 1, obtains digital yarns bars

In the soft core of sliver Spectrum Analysis IP,

1) the simulation sliver signal first evenness of yarn strip detecting sensor being obtained is changed through A/D converter, and simulation sliver signal is converted into digital yarns bars;

2) digital yarns bars is sent into load module, the xvalues module in load module is directly that sampling point value is deposited in the storer of FPGA device hardware inside by the digital yarns bars of input;

Step 2, carries out DFT conversion by digital yarns bars

The digital yarns bars of obtaining in step 1 is carried out to DFT conversion

1) carry out a DFT computing and will use 6300 sampled values, xvalues module is directly deposited sampled value in the storer of FPGA device hardware inside, xvalues module in load module, real part constant coefficient avalues module, imaginary part constant coefficient bvalues module all according to input sel[12..0] value enter different branches, export different storing values;

2) according to DFT transformation for mula, digital sliver signal is carried out to DFT conversion,

DFT transformation for mula is:

$X\left(k\right)=\mathrm{DFT}\left[x\left(n\right)\right]=\underset{n=0}{\overset{L-1}{\mathrm{\Σ}}}x\left(n\right)e^{-j\frac{2\mathrm{\π}}{P}\mathrm{kn}}=\underset{n=0}{\overset{L-1}{\mathrm{\Σ}}}x\left(n\right)(\cos \frac{2\mathrm{\π}}{P}\mathrm{kn}-j\sin \frac{2\mathrm{\π}}{P}\mathrm{kn})$

In DFT transformation for mula, in frequency domain, the corresponding relation of effective frequency and k is: wherein f represents the frequency values of 175 effective frequencies in frequency domain;

Order $a_k\left(n\right)=\cos \frac{2\mathrm{\π}}{P}\mathrm{kn},$ $b_k\left(n\right)=\sin \frac{2\mathrm{\π}}{P}\mathrm{kn},$

DFT transformation for mula can be written as:

$X\left(k\right)=\mathrm{DFT}\left[x\left(n\right)\right]=\underset{n=0}{\overset{L-1}{\mathrm{\Σ}}}x\left(n\right)\×[a_k\left(n\right)-j{b}_k\left(n\right)]$

As one timing of k value, a _kand b (n) _k(n) be the class value about n, the span of n is [0, L-1], a _kand b (n) _k(n) be L the constant corresponding to 0≤n≤L-1, by a _kand b (n) _k(n) be stored in advance in external memory storage after calculating, when digital yarns bars is inputted by a _kand b (n) _k(n) value is read in participation computing in FPGA device hardware;

DFT computing is mainly multiply-accumulate computing, and DFT computing is similar and simpler to realizing of wave filter, implementation procedure only need be on the basis of multiply-accumulate an additional state machine control the sequential of multiply accumulating; In multiplier, be provided with mult module, input multiplier and multiplicand correspond respectively to 14 constant coefficient values of digital yarns bars value, real part constant coefficient avalues module and the imaginary part constant coefficient bvalues mould of 14 inputs, and Output rusults represents by 28 two's complement; Cumulative mould device piece comprises the cumulative accax module of real part and the cumulative accbx module of imaginary part, and the cumulative accax module of real part is identical with the computing of the cumulative accbx module of imaginary part; The cumulative accax module of real part is again the input value ax[27..0 of accumulator module by input clock signal clk, output trigger pip first_d, mult module output valve simultaneously] and the real part accumulation result value accax[36..0 of accumulator module] forms, the cumulative accax module of real part is carried out the digital yarns bars value and the real part coefficient a that input _kthe accumulating operation of product; By 6300 digital sliver signals of input, be that sampled value is carried out the real part of DFT computing and the result of imaginary part calculating adds up and exports, finally obtain the real part A of 6300 sampled value DFT _kwith imaginary part B _k;

When new round accumulation loop starts by upper accumulation result zero clearing once, state machine has 6303 states, corresponding 6302 sel signals and an idle condition, this idle condition is idle state and default state, state machine constantly circulates between 6302 states at 1 state, simultaneously can be to xvalues module, real part constant coefficient avalues module, a new sel value of imaginary part constant coefficient bvalues module output, because input signal is corresponding one by one with sel signal with constant coefficient, sel signal value of the every output of state machine, real part constant coefficient avalues module and imaginary part constant coefficient bvalues module all can be exported a corresponding value, and send in multiplier, thereby make corresponding input signal values and constant coefficient do multiplying, finally result of product is sent into accumulator module, state machine can be in beginning and the end of each circulation, respectively first signal and follow signal are put to 1, when first signal is 1, accumulator module will be the result zero clearing of last round of circulation, start new round accumulation calculating, when follow signal is 1, trigger DEEF just starts output, with this, reaches the object of controlling output.

Step 3, calculates the amplitude M that Spectrum Analysis is concerned about _k

According to the real part A that calculates DFT in step 2 _kwith imaginary part B _k, carrying out root mean square computing, formula is as follows, calculates the amplitude M that Spectrum Analysis is concerned about _k;

The amplitude M that Spectrum Analysis is concerned about _kcomputing formula as follows:

$M_k=\sqrt[2]{A_k^2+B_k^2}$

According to 6300 sampled values of the soft core of Spectrum Analysis IP, calculate the amplitude M of 175 frequencies _k;

Step 4, obtains sliver signal full frequency band wave spectrum

In 55 channels of full frequency band of sliver Spectrum Analysis, in each channel, comprise the amplitude M of one or more frequencies _k, the band bandwidth more frequency number in wide channel is just more, and in 55 channels, the final output wave spectrum of each channel be the interior all frequency amplitude M of each channel _kaverage, and the combination of 55 channel wave spectrums is full frequency band sliver signal wave spectrum.

The invention has the beneficial effects as follows,

1) adopt DFT frequency sampling new algorithm to replace the bandpass filtering mode adopting in conventional wave spectral analysis method, realize the analytical calculation to sliver wave spectrum, can effectively reduce the calculated amount of Spectrum Analysis;

2) in the new algorithm based on DFT frequency sampling, adopt Non-uniform sampling mode, can reduce DFT calculating and count, further reduce calculated amount;

3) in 55 channels of full frequency band of sliver Spectrum Analysis, each channel adopts respectively the sliver Spectrum Analysis new algorithm of DFT frequency domain sample to realize the Spectrum Analysis of each channel, and Spectrum Analysis algorithm between each channel adopts parallel constitution, the Spectrum Analysis of each channel of Parallel Implementation is calculated, thereby again promote all band Spectrum Analysis computing velocity, effectively improve the real-time that all band Spectrum Analysis is calculated;

4) by HDL hardware description language, the sliver Spectrum Analysis new algorithm of each channel DFT frequency domain sample of parallel organization is encapsulated as to the soft core of IP of energy complete independently full frequency band sliver signal wave analysis of spectrum, thereby conveniently FPGA hardware platform is put and downloaded in the soft caryogamy of IP, complete the real-time calculating of Spectrum Analysis.

Accompanying drawing explanation

Fig. 1 realizes the theory diagram of sliver signal 55 channel wave analysis of spectrums based on DFT frequency domain sample algorithm under FPGA hardware platform in the present invention;

Fig. 2 is the sliver signal wave analysis of spectrum theory diagram in a passage in 55 passages in the sliver Spectrum Analysis IP kernel based on DFT frequency domain sample in the present invention;

Fig. 3 be in the present invention in sliver Spectrum Analysis IP kernel in 55 passages the HDL language of the sliver signal wave analysis of spectrum in a passage mix with schematic diagram and input top design;

In figure, 1.xvalues module, 2. real part constant coefficient avalues module, 3. imaginary part constant coefficient bvalues module, 4.state m module, 5.mult module, 6. the cumulative accax module of real part, the 7. cumulative accbx module of imaginary part, 8.FPGA device hardware, the soft core of 9.55 passage sliver Spectrum Analysis IP, 10.IP daughter nucleus, 11. load modules, 12. state machines, 13. multipliers, 14. accumulator module, 15 output modules.

Embodiment

Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.

The soft core of sliver Spectrum Analysis IP based on DFT frequency sampling, inner structure as shown in Figures 1 and 2, include sliver Spectrum Analysis computing unit, sliver Spectrum Analysis computing unit includes FPGA device hardware 8, the interior HDL of the utilization language of FPGA device hardware 8 is the soft core 9 of 55 passage sliver Spectrum Analysis IP by the sliver Spectrum Analysis algorithm packaging based on DFT frequency sampling, the soft core 9 of 55 passage sliver Spectrum Analysis IP includes centre frequency difference and amount of bandwidth 55 channels not etc., each channel includes a set of IP daughter nucleus 10 based on DFT frequency sampling, IP daughter nucleus 10 includes load module 11, state machine 12, two multipliers 13, two accumulator module 14 and output module 15, load module 11 includes xvalues module 1, real part constant coefficient avalues module 2, imaginary part constant coefficient bvalues module 3, in state machine 12, be provided with state_m module 4, in multiplier 13, be provided with mult module 5, accumulator module 14 includes the cumulative accax module 6 of real part and the cumulative accbx module 7 of imaginary part,

Load module 11 is connected with state machine 12 by wire, state machine 12 is respectively by wire and xvalues module 1, real part constant coefficient avalues module 2, imaginary part constant coefficient bvalues module 3 connects, real part constant coefficient avalues module 2 is by the mult module 5 in wire and a multiplier 13, the real part accax module 6 that adds up, a trigger DFFE connects successively, imaginary part constant coefficient bvalues module 3 is by the mult module 5 in wire and another multiplier 13, the imaginary part accbx module 7 that adds up, another trigger DFFE connects successively, xvalues module 1 is connected respectively with two multipliers 13 by wire.

The detection method of the soft core of sliver Spectrum Analysis IP based on DFT frequency sampling, as shown in Figures 2 and 3, specifically according to following steps, implement:

Here the first Spectrum Analysis of sliver Spectrum Analysis IP kernel of take is example, and the Spectrum Analysis principle of all the other 54 channels is all identical with the 1st channel with implementation procedure;

Step 1, obtains digital yarns bars

In the soft core of sliver Spectrum Analysis IP, as shown in Figure 1,

1) the simulation sliver signal first evenness of yarn strip detecting sensor being obtained is changed through A/D converter, and simulation sliver signal is converted into digital yarns bars;

2) digital yarns bars is sent into load module 11, the xvalues module 1 in load module 11 is directly that sampling point value is deposited in the storer of FPGA device hardware 8 inside by the digital yarns bars of input;

Step 2, carries out DFT conversion by digital yarns bars

The digital yarns bars of obtaining in step 1 is carried out to DFT conversion

1) carry out a DFT computing and will use 6300 sampled values, xvalues module 1 is directly deposited sampled value in the storer of FPGA device hardware 8 inside, xvalues module 1 in load module 11, real part constant coefficient avalues module 2, imaginary part constant coefficient bvalues module 3 all according to input sel[12..0] value enter different branches, export different storing values;

2) according to DFT transformation for mula, digital sliver signal is carried out to DFT conversion,

DFT transformation for mula is:

$X\left(k\right)=\mathrm{DFT}\left[x\left(n\right)\right]=\underset{n=0}{\overset{L-1}{\mathrm{\Σ}}}x\left(n\right)e^{-j\frac{2\mathrm{\π}}{P}\mathrm{kn}}=\underset{n=0}{\overset{L-1}{\mathrm{\Σ}}}x\left(n\right)(\cos \frac{2\mathrm{\π}}{P}\mathrm{kn}-j\sin \frac{2\mathrm{\π}}{P}\mathrm{kn})$

In DFT transformation for mula, in frequency domain, the corresponding relation of effective frequency and k is: wherein f represents the frequency values of 175 effective frequencies in frequency domain;

Order $a_k\left(n\right)=\cos \frac{2\mathrm{\π}}{P}\mathrm{kn},$ $b_k\left(n\right)=\sin \frac{2\mathrm{\π}}{P}\mathrm{kn},$

DFT transformation for mula can be written as:

$X\left(k\right)=\mathrm{DFT}\left[x\left(n\right)\right]=\underset{n=0}{\overset{L-1}{\mathrm{\Σ}}}x\left(n\right)\×[a_k\left(n\right)-j{b}_k\left(n\right)]$

As one timing of k value, a _kand b (n) _k(n) be the class value about n, the span of n is [0, L-1], a _kand b (n) _k(n) be L the constant corresponding to 0≤n≤L-1, by a _kand b (n) _k(n) be stored in advance in external memory storage after calculating, when digital yarns bars is inputted by a _kand b (n) _k(n) value is read in the interior participation computing of FPGA device hardware 8;

DFT computing is mainly multiply-accumulate computing, and DFT computing is similar and simpler to realizing of wave filter, implementation procedure only need be on the basis of multiply-accumulate an additional state machine 12 control the sequential of multiply accumulating; In multiplier 13, be provided with mult module 5, input multiplier and multiplicand correspond respectively to 14 constant coefficient values of digital yarns bars value, real part constant coefficient avalues module 6 and the imaginary part constant coefficient bvalues module 7 of 14 inputs, and Output rusults represents by 28 two's complement; Cumulative mould device piece 14 comprises the cumulative accax module 6 of real part and the cumulative accbx module 7 of imaginary part, and the cumulative accax module 6 of real part is identical with the computing of the cumulative accbx module 7 of imaginary part; The cumulative accax module 6 of real part is again the input value ax[27..0 of accumulator module 14 by input clock signal clk, output trigger pip first_d, mult module 5 output valves simultaneously] and the real part accumulation result value accax[36..0 of accumulator module 14] forms, the cumulative accax module 6 of real part is carried out the digital yarns bars value and the real part coefficient a that input _kthe accumulating operation of product; By 6300 digital sliver signals of input, be that sampled value is carried out the real part of DFT computing and the result of imaginary part calculating adds up and exports, finally obtain the real part A of 6300 sampled value DFT _kwith imaginary part B _k;

When new round accumulation loop starts by upper accumulation result zero clearing once, state machine 12 has 6303 states, corresponding 6302 sel signals and an idle condition, this idle condition is idle state and default state, state machine 12 constantly circulates between 6302 states at 1 state, simultaneously can be to xvalues module 1, real part constant coefficient avalues module 2, a new sel value of imaginary part constant coefficient bvalues module 3 outputs, because input signal is corresponding one by one with sel signal with constant coefficient, sel signal value of the every output of state machine 12, real part constant coefficient avalues module 2 and imaginary part constant coefficient bvalues module 3 all can be exported a corresponding value, and send in multiplier 13, thereby make corresponding input signal values and constant coefficient do multiplying, finally result of product is sent into accumulator module 14, state machine 12 can be in beginning and the end of each circulation, respectively first signal and follow signal are put to 1, when first signal is 1, accumulator module 14 will be the result zero clearing of last round of circulation, start new round accumulation calculating, when follow signal is 1, trigger DEEF just starts output, with this, reaches the object of controlling output.

Step 3, calculates the amplitude M that Spectrum Analysis is concerned about _k

According to the real part A that calculates DFT in step 2 _kwith imaginary part B _k, carrying out root mean square computing, formula is as follows, calculates the amplitude M that Spectrum Analysis is concerned about _k;

The amplitude M that Spectrum Analysis is concerned about _kcomputing formula as follows:

$M_k=\sqrt[2]{A_k^2+B_k^2}$

According to 6300 sampled values of the soft core of Spectrum Analysis IP, calculate the amplitude M of 175 frequencies _k;

Step 4, obtains sliver signal full frequency band wave spectrum

In 55 channels of full frequency band of sliver Spectrum Analysis, in each channel, comprise the amplitude M of one or more frequencies _k, the band bandwidth more frequency number in wide channel is just more, and in 55 channels, the final output wave spectrum of each channel be the interior all frequency amplitude M of each channel _kaverage, and the combination of 55 channel wave spectrums is full frequency band sliver signal wave spectrum.

Because the whole computing of the soft core of sliver Spectrum Analysis IP be take multiply-accumulate as main, may cause overflowing of net result or pilot process numerical value, for preventing that operation result numerical value from overflowing, in the situation that guaranteeing computational accuracy, reduce as much as possible again the word length that participates in computing parameter simultaneously, through MATLAB mathematical software simulating, verifying, in the present invention, determine input signal x (n), constant coefficient a _kand b _kall use 14 binary code representations, and multiply-accumulate result A _kand B _kby 37 two's complement, represent;

The HDL language of the sliver signal wave analysis of spectrum in a passage in sliver Spectrum Analysis IP kernel in 55 passages mixes input top design as shown in Figure 3 with schematic diagram.

State_m module 4 in state machine 12 is by inputting clk, reset and output follow, first, sel[12..0] form, be mainly responsible for the flow process of whole frequency sampling DFT computing and control, be the core of computing; Wherein export sel[12..0] controlling the input timing of three modules of input; Output follow controls the output of end product; Output first is the control signal of accumulator module 14, and when new round accumulation loop starts, by upper accumulation result zero clearing once, state machine 12 is core components, and state machine has 6303 states in the present invention.

Sliver Spectrum Analysis computing unit is the core component of sliver wave spectrum analyzer, the soft core implementation of IP of the present invention utilizes DFT frequency employing method, according to Ulster Corporation, the division of wave spectrum channel is selectively calculated the frequency spectrum of the part channel that Spectrum Analysis is concerned about, and utilize HDL language to be transplanted to the sliver Spectrum Analysis algorithm based on DFT frequency domain sample and can carry out on the FPAG device hardware 8 of concurrent operation, design can complete independently sliver Spectrum Analysis work the soft core of IP; Compare with traditional sliver analysis method by use of spectrum, the hardware resource that the inventive method takies greatly reduces, real-time analysis computing power is significantly improved, core component sliver Spectrum Analysis computing unit of the present invention, only the soft core of IP need to be configured on the FPAG hardware device 8 of selection, largely simplify design difficulty, reduced development time and cost.

Sliver signal wave spectrogram is got through certain processing by sliver signal spectrum figure, so should first calculate the frequency spectrum of sliver signal while studying in practice the wave spectrogram of sliver signal, and then according to corresponding formula, spectrogram is converted to wave spectrogram and show.Specifically, the wave spectrogram that Spectrum Analysis obtains is comprised of effective corresponding amplitude of frequency in 55 channels, and 55 channels have comprised 175 effective frequencies, and the computation process of each effective frequency is all identical.The soft core of IP and 8 combinations of FPGA device hardware, can, to the sliver simulating signal of sensor output after A/D sampling, complete the Fourier transform of sliver signal and spectrum analysis are calculated, with column wave spectrogram formal output.

The present invention adopts DFT frequency sampling new algorithm to replace conventional wave analysis of spectrum mode to realize the analytical calculation to sliver wave spectrum, new algorithm based on DFT frequency sampling is compared with filter method and full frequency band frequency analysis method, when being carried out to Spectrum Analysis, only calculates sliver signal the amplitude of frequency in be concerned about frequency range, and it is carried out to certain processing, finally obtain the wave spectrogram consistent with uster instrument wave spectrogram.Therefore, the method has reduced the complexity of Spectrum Analysis, has reduced operand, has improved the real-time of analytic operation.

In the new algorithm based on DFT frequency sampling, adopt Non-uniform sampling mode.Optionally extract some specific frequency in each channel and carry out DFT calculating; the any frequency in the guard band between two effective frequency ranges is not calculated to DFT; simultaneously because each channel bandwidth is not of uniform size; therefore frequency domain sample is counted also different; the narrower low channel frequency sampling of bandwidth is counted less; the high channel frequency sampling of broader bandwidth is counted more, but each channel selects maximum several DFT values to do average rear output.Irregular Non-uniform sampling mode has like this greatly reduced sampled point number, algorithm calculated amount greatly reduces, the frequency output valve distortion that has also prevented that sampled point is very few simultaneously and caused, makes the sliver signal wave spectrum of proportion sampling method output and the Output rusults of conventional wave spectral analysis method basically identical.

By HDL hardware description language, the sliver Spectrum Analysis new algorithm of DFT frequency domain sample is encapsulated as to the soft core of IP of energy complete independently sliver signal wave analysis of spectrum.By HDL hardware description language, the sliver Spectrum Analysis new algorithm of DFT frequency domain sample is transplanted on FPGA device hardware 8 to the soft core of IP that formation can complete independently sliver signal wave analysis of spectrum.Have than the present invention program with the DSP device hardware platform scheme of sliver Spectrum Analysis: highly versatile, portable good, adopt the advantages such as parallel computation real-time height.

Claims (3)

1. the soft core of sliver Spectrum Analysis IP based on DFT frequency sampling, it is characterized in that, include sliver Spectrum Analysis computing unit, sliver Spectrum Analysis computing unit includes FPGA device hardware (8), in FPGA device hardware (8), utilizing HDL language is the 55 soft cores of passage sliver Spectrum Analysis IP (9) by the sliver Spectrum Analysis algorithm packaging based on DFT frequency sampling, the 55 soft cores of passage sliver Spectrum Analysis IP (9) include centre frequency difference and amount of bandwidth 55 channels not etc., each channel includes a set of IP daughter nucleus (10) based on DFT frequency sampling, IP daughter nucleus (10) includes load module (11), state machine (12), two multipliers (13), two accumulator module (14) and output module (15), load module (11) includes xvalues module (1), real part constant coefficient avalues module (2), imaginary part constant coefficient bvalues module (3), in state machine (12), be provided with state_m module (4), in multiplier (13), be provided with mult module (5), accumulator module (14) includes the cumulative accax module (6) of real part and the cumulative accbx module (7) of imaginary part,

Load module (11) is connected with state machine (12) by wire, state machine (12) is respectively by wire and xvalues module (1), real part constant coefficient avalues module (2), imaginary part constant coefficient bvalues module (3) connects, real part constant coefficient avalues module (2) is by the mult module (5) in wire and a multiplier (13), the real part accax module (6) that adds up, a trigger DFFE connects successively, imaginary part constant coefficient bvalues module (3) is by the mult module (5) in wire and another multiplier (13), the imaginary part accbx module (7) that adds up, another trigger DFFE connects successively, xvalues module (1) is connected respectively with two multipliers (13) by wire.

2. the detection method of the soft core of sliver Spectrum Analysis IP based on DFT frequency sampling, is characterized in that, the soft core of sliver Spectrum Analysis IP based on claim 1 is specifically implemented according to following steps:

Step 1, obtains digital yarns bars:

In the soft core of sliver Spectrum Analysis IP,

1) the simulation sliver signal first evenness of yarn strip detecting sensor being obtained is changed through A/D converter, and simulation sliver signal is converted into digital yarns bars;

2) digital yarns bars is sent into load module (11), the xvalues module (1) in load module (11) is directly that sampling point value is deposited in the inner storer of FPGA device hardware (8) by the digital yarns bars of input;

Step 2, digital yarns bars is carried out DFT conversion:

The digital yarns bars that step 1 is obtained is carried out DFT conversion

1) carry out a DFT computing and will use 6300 sampled values, xvalues module (1) is directly deposited sampled value in the inner storer of FPGA device hardware (8), xvalues module (1) in load module (11), real part constant coefficient avalues module (2), imaginary part constant coefficient bvalues module (3) all according to input sel[12..0] value enter different branches, export different storing values;

2) according to DFT transformation for mula, digital sliver signal is carried out to DFT conversion,

DFT transformation for mula is:

$X\left(k\right)=\mathrm{DEF}\left[x\left(n\right)\right]=\underset{n=0}{\overset{L-1}{\mathrm{\Σ}}}x\left(n\right)e^{-j\frac{2\mathrm{\π}}{P}\mathrm{kn}}=\underset{n=0}{\overset{L-1}{\mathrm{\Σ}}}x\left(n\right)(\cos \frac{2\mathrm{\π}}{P}\mathrm{kn}-j\sin \frac{2\mathrm{\π}}{P}\mathrm{kn})$

In DFT transformation for mula, in frequency domain, the corresponding relation of effective frequency and k is: wherein f represents the frequency values of 175 effective frequencies in frequency domain, and P is that the calculating of segmentation DFT is counted, and L is that block sampling is counted, and fs is time-domain sampling frequency;

Order $a_k\left(n\right)=\cos \frac{2\mathrm{\π}}{P}\mathrm{kn},b_k\left(n\right)=\sin \frac{2\mathrm{\π}}{P}\mathrm{kn},$

DFT transformation for mula can be written as:

$X\left(k\right)=\mathrm{DFT}\left[x\left(n\right)\right]=\underset{n=0}{\overset{L-1}{\mathrm{\Σ}}}x\left(n\right)\×[a_k\left(n\right)-{\mathrm{jb}}_k\left(n\right)]$

As one timing of k value, a _kand b (n) _k(n) be the class value about n, the span of n is [0, L-1], a _kand b (n) _k(n) be L the constant corresponding to 0≤n≤L-1, by a _kand b (n) _k(n) be stored in advance in external memory storage after calculating, when digital yarns bars is inputted by a _kand b (n) _k(n) value is read in participation computing in FPGA device hardware (8);

DFT computing is mainly multiply-accumulate computing, only need be on the basis of multiply-accumulate an additional state machine (12) control the sequential of multiply accumulating; In multiplier (13), be provided with mult module (5), input multiplier and multiplicand correspond respectively to 14 constant coefficient values of 14 input signal values, real part constant coefficient avalues module (6) and imaginary part constant coefficient bvalues module (7), and Output rusults represents by 28 two's complement; Cumulative mould device piece (14) comprises the cumulative accax module (6) of real part and the cumulative accbx module (7) of imaginary part, and the cumulative accax module (6) of real part is identical with the computing of the cumulative accbx module (7) of imaginary part; The cumulative accax module (6) of real part is again the input value ax[27..0 of accumulator module (14) by input clock signal clk, output trigger pip first_d, mult module (5) output valve simultaneously] and the real part accumulation result value accax[36..0 of accumulator module (14)] forms, the real part accax module (6) that adds up is carried out input signal values and real part coefficient a _kthe accumulating operation of product; 6300 sampled values of input are carried out to the result that the real part of DFT computing and imaginary part calculate and add up and export, finally obtain the real part A of 6300 sampled value DFT _kwith imaginary part B _k;

Described 14 input signal values and 14 constant coefficient values are scale-of-two;

When new round accumulation loop starts by upper accumulation result zero clearing once, state machine (12) has 6303 states, corresponding 6302 sel signals and an idle condition, this idle condition is idle state and default state, state machine (12) constantly circulates between 6302 states at 1 state, simultaneously can be to xvalues module (1), real part constant coefficient avalues module (2), a new sel value of imaginary part constant coefficient bvalues module (3) output, because input signal is corresponding one by one with sel signal with constant coefficient, sel signal value of the every output of state machine 12, real part constant coefficient avalues module (2) and imaginary part constant coefficient bvalues module (3) all can be exported a corresponding value, and send in multiplier (13), thereby make corresponding input signal values and constant coefficient do multiplying, finally result of product is sent into accumulator module (14), state machine (12) can be in beginning and the end of each circulation, respectively first signal and follow signal are put to 1, when first signal is 1, accumulator module (14) will be the result zero clearing of last round of circulation, start new round accumulation calculating, when follow signal is 1, trigger DEEF just starts output, with this, reaches the object of controlling output,

Step 3, calculates the amplitude M that Spectrum Analysis is concerned about _k:

According to the real part A that calculates DFT in step 2 _kwith imaginary part B _k, carrying out root mean square computing, formula is as follows, calculates the amplitude M that Spectrum Analysis is concerned about _k;

The amplitude M that Spectrum Analysis is concerned about _kcomputing formula as follows:

$M_k=\sqrt[2]{A_k^2+B_k^2};$

According to 6300 sampled values of the soft core of Spectrum Analysis IP, calculate the amplitude M of 175 frequencies _k;

Step 4, obtains sliver signal full frequency band wave spectrum:

Every 6300 sampled values of the soft core of Spectrum Analysis IP, calculate the amplitude M of 175 frequencies _k, and in 55 channels of the full frequency band of sliver Spectrum Analysis, in each channel, comprise the amplitude M of one or more frequencies _k, the band bandwidth more frequency number in wide channel is just more, and in 55 channels, the final output wave spectrum of each channel be the interior all frequency amplitude M of each channel _kaverage, and the combination of 55 channel wave spectrums is full frequency band sliver signal wave spectrum.

3. the detection method of the soft core of sliver Spectrum Analysis IP based on DFT frequency sampling according to claim 2, is characterized in that, described input signal x (n), real part constant coefficient a _k, imaginary part constant coefficient b _kall use 14 binary code representations, and multiply-accumulate result A _kand B _kby 37 two's complement, represent, time-domain sampling frequency f s is 1KHz, and the block sampling L that counts is 6300, and the calculating of the segmentation DFT P that counts gets 256000, at frequency domain, carries out Non uniform sampling, only needs to calculate the DFT value of 175 frequencies.