CN102810851B - Over-current protective circuit and digital output circuit - Google Patents
Over-current protective circuit and digital output circuit Download PDFInfo
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- CN102810851B CN102810851B CN201210279701.4A CN201210279701A CN102810851B CN 102810851 B CN102810851 B CN 102810851B CN 201210279701 A CN201210279701 A CN 201210279701A CN 102810851 B CN102810851 B CN 102810851B
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Abstract
The invention provides an over-current protective circuit and a digital output circuit. The over-current protective circuit comprises a current limiting circuit, a timing circuit, a voltage regulating circuit and a comparator. When the digital output circuit is at an over-current status, the over-current protective circuit limits the current within a second threshold value by the over-current limiting circuit to determine the current at the over-current status, and outputs a first control signal by the comparator in the voltage regulating unit to control a switch tube to quickly switch off for closing the output, thereby ensuring the high switch-off speed at the over-current status without changing a fuse; when the switch-off time of the switch tube is longer than the first time timed by the timing unit, the voltage regulating unit outputs a second control signal to control the switch tube to switch on; and the switch-on time of the switch tube is the second time timed by the timing unit; and if the output is still at the over-current status, the output is closed again. According to the over-current protective circuit and the digital output circuit, the time for retuning output to normal is determined by repeatedly and periodically trying until the output is not at the over-current status.
Description
Technical field
The present invention relates to digital output circuit field, particularly relate to a kind of current foldback circuit and digital output circuit.
Background technology
In digital output circuit, in order to prevent overcurrent damage device, generally adopt the method for connect in output circuit fuse wire or resettable fuse.
When electric current flows through fuse, the resistance that fuse exists makes fuse generate heat, along with its caloric value of increase of time also increases.And the size of electric current and its resistance determines the speed producing heat, the situation of the structure of fuse and its installation determines the speed of heat dissipation, if when the speed producing heat is less than the speed of heat dissipation, fuse can not fuse.If the speed producing heat equals the speed of heat dissipation, within considerable time, it also can not fuse.Only have when the speed producing heat is greater than the speed of heat dissipation, the heat of generation gets more and more, and when temperature is elevated to more than the fusing point of fuse, fuse just can fuse, and the fuse that must more renew causes use inconvenient.Therefore series connection fuse wire method is when actual overcurrent, because its fusing speed is comparatively slow, so have the protection shortcoming not fast to load equipment.
Resettable fuse by through special processing polymer resin and be distributed in the inside conducting particles form.When circuit is short-circuited or transship, the heat that the big current flowing through resettable fuse produces makes polymer resin melt, and volume increases rapidly, and form high-impedance state, operating current reduces rapidly, thus limits circuit and protect.When after failture evacuation, resettable fuse is crystallisation by cooling again, volume contraction, and conducting particles forms conductive path again, and resettable fuse reverts to low resistive state, thus completes the protection to circuit, need not manually change.The operating principle of resettable fuse is a kind of dynamic equilibrium of energy, when the electric current flowing through resettable fuse series of elements increases or ambient temperature raises, if but the balance of the heat reaching generation and the heat of distributing time, resettable fuse series is still failure to actuate.Only have when electric current or ambient temperature improve again; the heat produced is greater than the heat distributed; resettable fuse series of elements temperature is increased suddenly; these elements are made to be in high resistant guard mode; the increase of impedance limits electric current; thus protective circuit equipment is from damage, as long as the heat that the enough resettable fuse series of elements of heat that the voltage applied produces give out, the resettable fuse series of elements be under variable condition just can be in operate condition (high resistant) always.When only having the loss of voltage when applying, resettable fuse series just can be recovered automatically.Series connection resettable fuse method, when actual overcurrent, be difficult to size of current when determining overcurrent, and the speed of disconnecting consumers equipment is comparatively slow, quick not to the protection of load equipment.And cannot protect the large overcurrent of moment.Although need not change fuse, the recovery time of self-recoverage insurance is difficult to determine.
Summary of the invention
In view of this; the invention provides a kind of current foldback circuit and digital output circuit, to solve in available circuit to load equipment protection not fast, to use the problem being difficult to determine inconvenient, to be difficult to size of current when determining overcurrent and self-recoverage insurance recovery time.
To achieve these goals, the existing scheme proposed is as follows:
A kind of current foldback circuit, is applied to digital output circuit, comprises: flow-restriction, timing unit and voltage regulation unit, wherein:
Described flow-restriction is connected with described timing unit with the power supply of described digital output circuit, switching tube respectively, described switching tube connects ground connection after load, when described source current is greater than Second Threshold, described flow-restriction controls described source current and is not more than described Second Threshold;
Or described flow-restriction is connected with described timing unit with ground, described switching tube respectively, and described switching tube connects power supply after connecing load, when described source current is greater than Second Threshold, described flow-restriction controls described source current and is not more than described Second Threshold;
Described voltage regulation unit is connected with switching tube with described timing unit, flow-restriction respectively, when described source current is greater than first threshold, export the first control signal and control the cut-off of described switching tube, and the deadline of described switching tube is the first timing time of described timing unit; When being greater than the first timing time of described timing unit the deadline of described switching tube, described voltage regulation unit exports the second control signal and controls described switching tube conducting, and the ON time of described switching tube is the second timing time of described timing unit.
Preferably, described flow-restriction comprises: the first switching tube, the first resistance and the second resistance; Wherein:
Described first switching tube is PNP type triode, and its emitter is connected with one end of described first resistance, and its tie point is connected with power supply;
Or described first switching tube is NPN type triode, its emitter is connected with one end of described first resistance, its tie point ground connection;
And, the base stage of described first switching tube is connected with one end of described second resistance, the collector electrode of described first switching tube is connected with voltage regulation unit, and be connected with the grid of described switching tube, the other end of described first resistance is connected with the other end of described second resistance, its tie point is connected with timing unit, and is connected with the source electrode of described switching tube.
Preferably, described timing unit comprises: electric capacity, the first diode, the second diode, the 3rd resistance, the 4th resistance; Wherein:
The negative pole of described first diode is connected with described 3rd resistance, the positive pole of described second diode is connected with described 4th resistance, the positive pole of described first diode is connected with the negative pole of described second diode and is connected with one end of described electric capacity, tie point is connected with voltage regulation unit, the other end of described electric capacity is connected with power supply, or the other end ground connection of described electric capacity, described 3rd resistance is connected with described 4th resistance, and tie point is connected with flow-restriction.
Preferably, described voltage regulation unit comprises: comparator, the 5th resistance, the 6th resistance, the 7th resistance; Wherein:
One end of described 5th resistance connects the normal phase input end of described comparator, the other end of described 5th resistance is connected with the high supply power voltage input port of described comparator, one end of described 6th resistance connects the normal phase input end of described comparator, the other end of described 6th resistance is connected with the output of comparator, described tie point is connected with flow-restriction, and be connected with the grid of described switching tube, one end of described 7th resistance connects the normal phase input end of described comparator, the described other end of the 7th resistance is connected with the low suppling voltage input port of described comparator, the negative-phase input of described comparator is connected with timing unit.
Preferably, the resistance of the 3rd resistance in described timing unit differs 2 ~ 3 orders of magnitude with the resistance of the 4th resistance.
A kind of digital output circuit, comprise current foldback circuit, power supply and switching tube, wherein current foldback circuit comprises: flow-restriction, timing unit and voltage regulation unit; Wherein:
Described flow-restriction is connected with described timing unit with the power supply of described digital output circuit, switching tube respectively, described switching tube connects ground connection after load, when described source current is greater than Second Threshold, described flow-restriction controls described source current and is not more than described Second Threshold;
Or described flow-restriction is connected with described timing unit with ground, described switching tube respectively, and described switching tube connects power supply after connecing load, when described source current is greater than Second Threshold, described flow-restriction controls described source current and is not more than described Second Threshold;
Described voltage regulation unit is connected with switching tube with described timing unit, flow-restriction respectively, when described source current is greater than first threshold, export the first control signal and control the cut-off of described switching tube, and the deadline of described switching tube is the first timing time of described timing unit; When being greater than the first timing time of described timing unit the deadline of described switching tube, described voltage regulation unit exports the second control signal and controls described switching tube conducting, and the ON time of described switching tube is the second timing time of described timing unit.
Preferably, described flow-restriction comprises: the first switching tube, the first resistance and the second resistance; Wherein:
Described first switching tube is PNP type triode, and its emitter is connected with one end of described first resistance, and its tie point is connected with power supply;
Or described first switching tube is NPN type triode, its emitter is connected with one end of described first resistance, its tie point ground connection;
And, the base stage of described first switching tube is connected with one end of described second resistance, the collector electrode of described first switching tube is connected with voltage regulation unit, and be connected with the grid of described switching tube, the other end of described first resistance is connected with the other end of described second resistance, its tie point is connected with timing unit, and is connected with the source electrode of described switching tube.
Preferably, described timing unit comprises: electric capacity, the first diode, the second diode, the 3rd resistance, the 4th resistance; Wherein:
The negative pole of described first diode is connected with described 3rd resistance, the positive pole of described second diode is connected with described 4th resistance, the positive pole of described first diode is connected with the negative pole of described second diode and is connected with one end of described electric capacity, tie point is connected with voltage regulation unit, the other end of described electric capacity is connected with power supply, or the other end ground connection of described electric capacity, described 3rd resistance is connected with described 4th resistance, and tie point is connected with flow-restriction.
Preferably, described voltage regulation unit comprises: comparator, the 5th resistance, the 6th resistance, the 7th resistance; Wherein:
One end of described 5th resistance connects the normal phase input end of described comparator, the other end of described 5th resistance is connected with the high supply power voltage input port of described comparator, one end of described 6th resistance connects the normal phase input end of described comparator, the other end of described 6th resistance is connected with the output of comparator, described tie point is connected with flow-restriction, and be connected with the grid of described switching tube, one end of described 7th resistance connects the normal phase input end of described comparator, the described other end of the 7th resistance is connected with the low suppling voltage input port of described comparator, the negative-phase input of described comparator is connected with timing unit.
Preferably, the resistance of the 3rd resistance in described timing unit differs 2 ~ 3 orders of magnitude with the resistance of the 4th resistance.
As can be seen from above-mentioned technical scheme, in current foldback circuit disclosed by the invention, when digital output circuit overcurrent, current foldback circuit can by described flow-restriction by current limit in Second Threshold, determined size of current during overcurrent; And the first control signal exported by comparator in voltage regulation unit is controlled the cut-off of described switching tube and promptly closes output, and during to ensure overcurrent, turn-off speed is fast, and need not change fuse; When being greater than the first timing time of described timing unit the deadline of described switching tube, described voltage regulation unit exports the second control signal and controls described switching tube conducting, and the ON time of described switching tube is the second timing time of described timing unit, if export and remain over-current state, then again close output, the present invention is by so periodically making repeated attempts, until export no longer overcurrent, making to export the recovery normal time is able to the time and determines.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the circuit block diagram of digital output circuit disclosed by the invention;
Fig. 2 is the circuit block diagram of current foldback circuit disclosed by the invention;
The circuit theory diagrams of Fig. 3 flow-restriction disclosed in the embodiment of the present invention;
Fig. 4 is the schematic diagram of timing unit disclosed in the embodiment of the present invention;
The schematic diagram of Fig. 5 voltage regulation unit disclosed in the embodiment of the present invention;
The schematic diagram of Fig. 6 current foldback circuit disclosed in the embodiment of the present invention;
The schematic diagram of Fig. 7 another kind of flow-restriction disclosed in the embodiment of the present invention;
The schematic diagram of Fig. 8 another kind of current foldback circuit disclosed in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The invention provides a kind of current foldback circuit, to solve in available circuit to load equipment protection not fast, to use the problem being difficult to determine inconvenient, to be difficult to size of current when determining overcurrent and self-recoverage insurance recovery time.
As shown in Figure 2, current foldback circuit disclosed by the invention comprises: flow-restriction, timing unit and voltage regulation unit.
Concrete, flow-restriction as shown in Figure 3, comprising: the first resistance R1, the second resistance R2, the first switching tube VT1, wherein, described first switching tube VT1 is PNP type triode, its emitter is connected with one end of described first resistance R1, its tie point is connected with the power vd D of digital output circuit, the base stage of described first switching tube VT1 is connected with one end of described second resistance R2, the collector electrode of described first switching tube VT1 is connected with voltage regulation unit, and be connected with the grid of switching tube, the other end of described first resistance R1 is connected with the other end of described second resistance R2, its tie point is connected with timing unit, and be connected with the source electrode of switching tube, described switching tube is PMOS transistor.Or as shown in Figure 7, described first switching tube VT1 is NPN type triode, its tie point ground connection that its emitter is connected with described first resistance R1 one end, described switching tube is nmos pass transistor.
Timing unit as shown in Figure 4, comprising: the first diode VD1, the second diode VD2, the 3rd resistance R3, the 4th resistance R4, electric capacity C1; Wherein, the negative pole of described first diode VD1 is connected with described 3rd resistance R3, the positive pole of described second diode VD2 is connected with described 4th resistance R4, the positive pole of described first diode VD1 is connected with the negative pole of described second diode VD2 and is connected with one end of described electric capacity C1, tie point is connected with voltage regulation unit, the other end of described electric capacity C1 is connected with the power vd D of digital output circuit, and described 3rd resistance R3 is connected with described 4th resistance R4, and tie point is connected with flow-restriction.Or when flow-restriction ground connection, the other end also ground connection of described electric capacity C1.
Voltage regulation unit as shown in Figure 5, comprising: comparator U1, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, wherein, one end of described 5th resistance R5 connects the normal phase input end of described comparator U1, the other end of described 5th resistance R5 is connected with the high supply power voltage input port VP of described comparator U1, one end of described 6th resistance R6 connects the normal phase input end of described comparator U1, the other end of described 6th resistance R6 is connected with the output of described comparator U1, tie point is connected with flow-restriction, and be connected with the grid of described switching tube, one end of described 7th resistance R7 connects the normal phase input end of described comparator U1, the other end of described 7th resistance R7 is connected with the low suppling voltage input port VN of described comparator U1, the negative-phase input of described comparator U1 is connected with timing unit.
Overall current foldback circuit schematic diagram is as shown in Fig. 6 or Fig. 8; wherein; the tie point of described flow-restriction first resistance R1 and the second resistance R2 is connected to the tie point of described timing unit the 3rd resistance R3 and the 4th resistance R4; the tie point of described timing unit electric capacity C1 and described first diode VD1 positive pole, the second diode VD2 negative pole is connected to the negative-phase input of described voltage regulation unit comparator U1, and the output of described voltage regulation unit comparator U1 is connected to the grid of switching tube.
The concrete course of work of current foldback circuit is as follows:
When the output current of digital output circuit is under normal circumstances (non-overcurrent), current foldback circuit is inoperative, does not have an impact to the normal function of circuit.When under output circuit generation overcurrent condition, if described source current is greater than first threshold I1, ER effect then through described first resistance R1 is large, its two ends pressure drop UR1 also increases, when described flow-restriction is connected with power vd D, described electric capacity C1 discharges via described first diode VD1 and described 3rd resistance R3, the magnitude of voltage U1N of voltage regulation unit comparator negative-phase input is caused to reduce, until the magnitude of voltage U1N of negative-phase input is less than the magnitude of voltage U1P of normal phase input end, now described comparator U1 exports the first control signal high level VP, input to the grid of described PMOS switch pipe, control the cut-off of described switching tube, then timing unit electric capacity C1 starts to charge via described 4th resistance R4 and described second diode VD2, and the deadline of described switching tube is the first timing time T1 of described timing unit.
When being obtained by Fig. 5 after described switching tube cut-off, described 5th resistance R5 and described 6th resistance R6 is parallel to high supply power voltage VP and normal phase input end, 7th resistance R7 is connected to low suppling voltage VN and normal phase input end, so now U1P=VN+ (VP-VN) * R7/ ((R5//R6)+R7); When comparator overturns, U1N ≈ U1P, ignores the small area analysis in timing unit, first threshold I1 ≈ (VDD-U1P)/R1.
Or when flow-restriction ground connection, if described source current is greater than first threshold I1, first resistance R1 two ends pressure drop UR1 increases, electric current flows through described 4th resistance R4 and described second diode VD2, described electric capacity C1 charges, the magnitude of voltage U1N of voltage regulation unit comparator negative-phase input is caused to raise, until the magnitude of voltage U1N of negative-phase input is higher than the magnitude of voltage U1P of normal phase input end, now described comparator U1 exports the first control signal low level VN, input to the grid of nmos switch pipe, control the cut-off of described switching tube, then timing unit electric capacity C1 starts to discharge via described first diode VD1 and the 3rd resistance R3, and the deadline of described switching tube is the first timing time T1 of described timing unit.
When being obtained by Fig. 5 after described switching tube cut-off, now described 5th resistance R5 is connected to high supply power voltage VP and normal phase input end, described 6th resistance R6 and described 7th resistance R7 is parallel to low suppling voltage VN and normal phase input end, so now U1P=VP-(VP-VN) * R5/ ((R6//R7)+R5); When described comparator upset, U1N ≈ U1P, ignores the small area analysis in timing unit, first threshold I1 ≈ (U1P-GND)/R1.
When flow-restriction and timing unit meet VDD, after experienced by the first timing time TI, described timing unit electric capacity C1 charges and terminates, now the negative-phase input magnitude of voltage U1N of comparator is elevated to and is about to exceed normal phase input end UIP magnitude of voltage, then described comparator U1 exports the second control signal low level VN, input to the grid of PMOS switch pipe, control described switching tube conducting, now electric current flows through described first diode VD1 and described 3rd resistance R3, described timing unit electric capacity C1 starts electric discharge, and the ON time of described switching tube is the second timing time T2 of described timing unit.
Now can be obtained by Fig. 5, described 5th resistance R5 connects high supply power voltage VP and normal phase input end, described 6th resistance R6 and described 7th resistance R7 is parallel in low suppling voltage VN and normal phase input end, so now U1P=VN+ (VP-VN) * (R6//R7)/((R6//R7)+R5).
Or when flow-restriction and timing unit ground connection, after experienced by the first timing time TI, described timing unit electric capacity C1 discharges and terminates, now the negative-phase input magnitude of voltage U1N of comparator is reduced to and is about to lower than normal phase input end UIP magnitude of voltage, then described comparator U1 exports the second control signal high level VP, input to the grid of nmos switch pipe, control described switching tube conducting, now electric current flows through described 4th resistance R4 and described second diode VD2, described timing unit electric capacity C1 starts charging, and the ON time of described switching tube is the second timing time T2 of described timing unit.
Now described 5th resistance R5 and described 6th resistance R6 is parallel to high supply power voltage VP and normal phase input end, described 7th resistance R7 is in connection low suppling voltage VN and normal phase input end, so now U1P=VN+ (VP-VN) * R7/ ((R5//R6)+R7).
Within the second timing time T2, if electric current still overcurrent, then again close output, then after waiting for the first timing time T1, again open output.Periodicity like this makes repeated attempts and opens output, until output current no longer overcurrent.
When electric current becomes large always, if described source current is greater than Second Threshold I2, in described flow-restriction, the pressure drop UR1 at resistance R1 two ends also becomes large thereupon, when UR1 approaches the first switching tube VT1 emitter junction forward voltage drop Veb of PNP type triode, described first switching tube VT1 is in open mode, thus UR1 is limited near Veb, namely output current is limited in the second current threshold I2 of setting, now I2 ≈ Veb/R1, or when flow-restriction ground connection, when UR1 approaches the first switching tube VT1 emitter inverse pressure drop Vbe of NPN type triode, described first switching tube VT1 is in open mode, thus UR1 is limited near Vbe, namely output current is limited in the second current threshold I2 of setting, now I2 ≈ Vbe/R1, it is the same when now the operation principle of unit is only greater than first threshold I1 with output current, repeat no more herein.
Present invention also offers a kind of digital output circuit, as shown in Figure 1, comprise input control, drived control, switching tube and current foldback circuit, wherein current foldback circuit comprises: flow-restriction, timing unit and voltage regulation unit.
Concrete, flow-restriction as shown in Figure 3, comprising: the first resistance R1, the second resistance R2, the first switching tube VT1, wherein, described first switching tube VT1 is PNP type triode, its emitter is connected with one end of described first resistance R1, its tie point is connected with the power vd D of digital output circuit, the base stage of described first switching tube VT1 is connected with one end of described second resistance R2, the collector electrode of described first switching tube VT1 is connected with voltage regulation unit, and be connected with the grid of switching tube, the other end of described first resistance R1 is connected with the other end of described second resistance R2, its tie point is connected with timing unit, and be connected with the source electrode of switching tube, described switching tube is PMOS transistor.Or as shown in Figure 7, described first switching tube VT1 is NPN type triode, its tie point ground connection that its emitter is connected with described first resistance R1 one end, described switching tube is nmos pass transistor.
Timing unit as shown in Figure 4, comprising: the first diode VD1, the second diode VD2, the 3rd resistance R3, the 4th resistance R4, electric capacity C1; Wherein, the negative pole of described first diode VD1 is connected with described 3rd resistance R3, the positive pole of described second diode VD2 is connected with described 4th resistance R4, the positive pole of described first diode VD1 is connected with the negative pole of described second diode VD2 and is connected with one end of described electric capacity C1, tie point is connected with voltage regulation unit, the other end of described electric capacity C1 is connected with the power vd D of digital output circuit, and described 3rd resistance R3 is connected with described 4th resistance R4, and tie point is connected with flow-restriction.Or when flow-restriction ground connection, the other end also ground connection of described electric capacity C1.
Voltage regulation unit as shown in Figure 5, comprising: comparator U1, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, wherein, one end of described 5th resistance R5 connects the normal phase input end of described comparator U1, the other end of described 5th resistance R5 is connected with the high supply power voltage input port VP of described comparator U1, one end of described 6th resistance R6 connects the normal phase input end of described comparator U1, the other end of described 6th resistance R6 is connected with the output of described comparator U1, tie point is connected with flow-restriction, and be connected with the grid of described switching tube, one end of described 7th resistance R7 connects the normal phase input end of described comparator U1, the other end of described 7th resistance R7 is connected with the low suppling voltage input port VN of described comparator U1, the negative-phase input of described comparator U1 is connected with timing unit.
Overall current foldback circuit schematic diagram is as shown in Fig. 6 or Fig. 8; wherein; the tie point of described flow-restriction first resistance R1 and the second resistance R2 is connected to the tie point of described timing unit the 3rd resistance R3 and the 4th resistance R4; the tie point of described timing unit electric capacity C1 and described first diode VD1 positive pole, the second diode VD2 negative pole is connected to the negative-phase input of described voltage regulation unit comparator U1, and the output of described voltage regulation unit comparator U1 is connected to the grid of switching tube.
The concrete course of work of current foldback circuit is as follows:
When the output current of digital output circuit is under normal circumstances (non-overcurrent), current foldback circuit is inoperative, does not have an impact to the normal function of circuit.When under output circuit generation overcurrent condition, if described source current is greater than first threshold I1, ER effect then through described first resistance R1 is large, its two ends pressure drop UR1 also increases, when described flow-restriction is connected with power vd D, described electric capacity C1 discharges via described first diode VD1 and described 3rd resistance R3, the magnitude of voltage U1N of voltage regulation unit comparator negative-phase input is caused to reduce, until the magnitude of voltage U1N of negative-phase input is less than the magnitude of voltage U1P of normal phase input end, now described comparator U1 exports the first control signal high level VP, input to the grid of described PMOS switch pipe, control the cut-off of described switching tube, then timing unit electric capacity C1 starts to charge via described 4th resistance R4 and described second diode VD2, and the deadline of described switching tube is the first timing time T1 of described timing unit.
When being obtained by Fig. 5 after described switching tube cut-off, described 5th resistance R5 and described 6th resistance R6 is parallel to high supply power voltage VP and normal phase input end, 7th resistance R7 is connected to low suppling voltage VN and normal phase input end, so now U1P=VN+ (VP-VN) * R7/ ((R5//R6)+R7); When comparator overturns, U1N ≈ U1P, ignores the small area analysis in timing unit, first threshold I1 ≈ (VDD-U1P)/R1.
Or when flow-restriction ground connection, if described source current is greater than first threshold I1, first resistance R1 two ends pressure drop UR1 increases, electric current flows through described 4th resistance R4 and described second diode VD2, described electric capacity C1 charges, the magnitude of voltage U1N of voltage regulation unit comparator negative-phase input is caused to raise, until the magnitude of voltage U1N of negative-phase input is higher than the magnitude of voltage U1P of normal phase input end, now described comparator U1 exports the first control signal low level VN, input to the grid of nmos switch pipe, control the cut-off of described switching tube, then timing unit electric capacity C1 starts to discharge via described first diode VD1 and the 3rd resistance R3, and the deadline of described switching tube is the first timing time T1 of described timing unit.
When being obtained by Fig. 5 after described switching tube cut-off, now described 5th resistance R5 is connected to high supply power voltage VP and normal phase input end, described 6th resistance R6 and described 7th resistance R7 is parallel to low suppling voltage VN and normal phase input end, so now U1P=VP-(VP-VN) * R5/ ((R6//R7)+R5); When described comparator upset, U1N ≈ U1P, ignores the small area analysis in timing unit, first threshold I1 ≈ (U1P-GND)/R1.
When flow-restriction and timing unit meet VDD, after experienced by the first timing time TI, described timing unit electric capacity C1 charges and terminates, now the negative-phase input magnitude of voltage U1N of comparator is elevated to and is about to exceed normal phase input end UIP magnitude of voltage, then described comparator U1 exports the second control signal low level VN, input to the grid of PMOS switch pipe, control described switching tube conducting, now electric current flows through described first diode VD1 and described 3rd resistance R3, described timing unit electric capacity C1 starts electric discharge, and the ON time of described switching tube is the second timing time T2 of described timing unit.
Now can be obtained by Fig. 5, described 5th resistance R5 connects high supply power voltage VP and normal phase input end, described 6th resistance R6 and described 7th resistance R7 is parallel in low suppling voltage VN and normal phase input end, so now U1P=VN+ (VP-VN) * (R6//R7)/((R6//R7)+R5).
Or when flow-restriction and timing unit ground connection, after experienced by the first timing time TI, described timing unit electric capacity C1 discharges and terminates, now the negative-phase input magnitude of voltage U1N of comparator is reduced to and is about to lower than normal phase input end UIP magnitude of voltage, then described comparator U1 exports the second control signal high level VP, input to the grid of nmos switch pipe, control described switching tube conducting, now electric current flows through described 4th resistance R4 and described second diode VD2, described timing unit electric capacity C1 starts charging, and the ON time of described switching tube is the second timing time T2 of described timing unit.
Now described 5th resistance R5 and described 6th resistance R6 is parallel to high supply power voltage VP and normal phase input end, described 7th resistance R7 is in connection low suppling voltage VN and normal phase input end, so now U1P=VN+ (VP-VN) * R7/ ((R5//R6)+R7).
Within the second timing time T2, if electric current still overcurrent, then again close output, then after waiting for the first timing time T1, again open output.Periodicity like this makes repeated attempts and opens output, until output current no longer overcurrent.
When electric current becomes large always, if described source current is greater than Second Threshold I2, in described flow-restriction, the pressure drop UR1 at resistance R1 two ends also becomes large thereupon, when UR1 approaches the first switching tube VT1 emitter junction forward voltage drop Veb of PNP type triode, described first switching tube VT1 is in open mode, thus UR1 is limited near Veb, namely output current is limited in the second current threshold I2 of setting, now I2 ≈ Veb/R1, or when flow-restriction ground connection, when UR1 approaches the first switching tube VT1 emitter inverse pressure drop Vbe of NPN type triode, described first switching tube VT1 is in open mode, thus UR1 is limited near Vbe, namely output current is limited in the second current threshold I2 of setting, now I2 ≈ Vbe/R1, it is the same when now the operation principle of unit is only greater than first threshold I1 with output current, repeat no more herein.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (8)
1. a current foldback circuit, is characterized in that, is applied to digital output circuit, comprising: flow-restriction, timing unit and voltage regulation unit, wherein:
Described flow-restriction is connected with described timing unit with the power supply of described digital output circuit, switching tube respectively, described switching tube connects ground connection after load, when described source current is greater than Second Threshold, described flow-restriction controls described source current and is not more than described Second Threshold;
Or described flow-restriction is connected with described timing unit with ground, described switching tube respectively, and described switching tube connects power supply after connecing load, when described source current is greater than Second Threshold, described flow-restriction controls described source current and is not more than described Second Threshold;
Described voltage regulation unit is connected with switching tube with described timing unit, flow-restriction respectively, when described source current is greater than first threshold, export the first control signal and control the cut-off of described switching tube, and the deadline of described switching tube is the first timing time of described timing unit; When being greater than the first timing time of described timing unit the deadline of described switching tube, described voltage regulation unit exports the second control signal and controls described switching tube conducting, and the ON time of described switching tube is the second timing time of described timing unit;
Described flow-restriction comprises: the first switching tube, the first resistance and the second resistance; Wherein:
When described flow-restriction is connected with described timing unit with the power supply of described digital output circuit, switching tube respectively, described first switching tube is PNP type triode, and its emitter is connected with one end of described first resistance, and its tie point is connected with power supply;
Or when described flow-restriction is connected with described timing unit with ground, described switching tube respectively, described first switching tube is NPN type triode, and its emitter is connected with one end of described first resistance, its tie point ground connection;
And, the base stage of described first switching tube is connected with one end of described second resistance, the collector electrode of described first switching tube is connected with voltage regulation unit, and be connected with the grid of described switching tube, the other end of described first resistance is connected with the other end of described second resistance, its tie point is connected with timing unit, and is connected with the source electrode of described switching tube.
2. circuit according to claim 1, is characterized in that, described timing unit comprises: electric capacity, the first diode, the second diode, the 3rd resistance, the 4th resistance; Wherein:
When described flow-restriction respectively with the power supply of described digital output circuit, when switching tube is connected with described timing unit, the negative pole of described first diode is connected with described 3rd resistance, the positive pole of described second diode is connected with described 4th resistance, the positive pole of described first diode is connected with the negative pole of described second diode and is connected with one end of described electric capacity, tie point is connected with voltage regulation unit, the other end of described electric capacity is connected with power supply, described 3rd resistance is connected with described 4th resistance, tie point is connected with flow-restriction, or when described flow-restriction respectively with ground, when described switching tube is connected with described timing unit, the negative pole of described first diode is connected with described 3rd resistance, the positive pole of described second diode is connected with described 4th resistance, the positive pole of described first diode is connected with the negative pole of described second diode and is connected with one end of described electric capacity, tie point is connected with voltage regulation unit, the other end ground connection of described electric capacity, described 3rd resistance is connected with described 4th resistance, tie point is connected with flow-restriction.
3. circuit according to claim 1, is characterized in that, described voltage regulation unit comprises: comparator, the 5th resistance, the 6th resistance, the 7th resistance; Wherein:
One end of described 5th resistance connects the normal phase input end of described comparator, the other end of described 5th resistance is connected with the high supply power voltage input port of described comparator, one end of described 6th resistance connects the normal phase input end of described comparator, the other end of described 6th resistance is connected with the output of comparator, described 5th resistance is connected with flow-restriction with the tie point of described 6th resistance, and be connected with the grid of described switching tube, one end of described 7th resistance connects the normal phase input end of described comparator, the described other end of the 7th resistance is connected with the low suppling voltage input port of described comparator, the negative-phase input of described comparator is connected with timing unit.
4. circuit according to claim 2, is characterized in that, the resistance of the 3rd resistance in described timing unit differs 2-3 the order of magnitude with the resistance of the 4th resistance.
5. a digital output circuit, is characterized in that, comprise current foldback circuit, power supply and switching tube, wherein current foldback circuit comprises: flow-restriction, timing unit and voltage regulation unit; Wherein:
Described flow-restriction is connected with described timing unit with the power supply of described digital output circuit, switching tube respectively, described switching tube connects ground connection after load, when described source current is greater than Second Threshold, described flow-restriction controls described source current and is not more than described Second Threshold;
Or described flow-restriction is connected with described timing unit with ground, described switching tube respectively, and described switching tube connects power supply after connecing load, when described source current is greater than Second Threshold, described flow-restriction controls described source current and is not more than described Second Threshold;
Described voltage regulation unit is connected with switching tube with described timing unit, flow-restriction respectively, when described source current is greater than first threshold, export the first control signal and control the cut-off of described switching tube, and the deadline of described switching tube is the first timing time of described timing unit; When being greater than the first timing time of described timing unit the deadline of described switching tube, described voltage regulation unit exports the second control signal and controls described switching tube conducting, and the ON time of described switching tube is the second timing time of described timing unit;
Described flow-restriction comprises: the first switching tube, the first resistance and the second resistance; Wherein:
When described flow-restriction is connected with described timing unit with the power supply of described digital output circuit, switching tube respectively, described first switching tube is PNP type triode, and its emitter is connected with one end of described first resistance, and its tie point is connected with power supply;
Or when described flow-restriction is connected with described timing unit with ground, described switching tube respectively, described first switching tube is NPN type triode, and its emitter is connected with one end of described first resistance, its tie point ground connection;
And, the base stage of described first switching tube is connected with one end of described second resistance, the collector electrode of described first switching tube is connected with voltage regulation unit, and be connected with the grid of described switching tube, the other end of described first resistance is connected with the other end of described second resistance, its tie point is connected with timing unit, and is connected with the source electrode of described switching tube.
6. circuit according to claim 5, is characterized in that, described timing unit comprises: electric capacity, the first diode, the second diode, the 3rd resistance, the 4th resistance; Wherein:
When described flow-restriction respectively with the power supply of described digital output circuit, when switching tube is connected with described timing unit, the negative pole of described first diode is connected with described 3rd resistance, the positive pole of described second diode is connected with described 4th resistance, the positive pole of described first diode is connected with the negative pole of described second diode and is connected with one end of described electric capacity, tie point is connected with voltage regulation unit, the other end of described electric capacity is connected with power supply, described 3rd resistance is connected with described 4th resistance, tie point is connected with flow-restriction, or when described flow-restriction respectively with ground, when described switching tube is connected with described timing unit, the negative pole of described first diode is connected with described 3rd resistance, the positive pole of described second diode is connected with described 4th resistance, the positive pole of described first diode is connected with the negative pole of described second diode and is connected with one end of described electric capacity, tie point is connected with voltage regulation unit, the other end of described electric capacity is connected with power supply, the other end ground connection of described electric capacity, described 3rd resistance is connected with described 4th resistance, tie point is connected with flow-restriction.
7. circuit according to claim 5, is characterized in that, described voltage regulation unit comprises: comparator, the 5th resistance, the 6th resistance, the 7th resistance; Wherein:
One end of described 5th resistance connects the normal phase input end of described comparator, the other end of described 5th resistance is connected with the high supply power voltage input port of described comparator, one end of described 6th resistance connects the normal phase input end of described comparator, the other end of described 6th resistance is connected with the output of comparator, described 5th resistance is connected with flow-restriction with the tie point of described 6th resistance, and be connected with the grid of described switching tube, one end of described 7th resistance connects the normal phase input end of described comparator, the described other end of the 7th resistance is connected with the low suppling voltage input port of described comparator, the negative-phase input of described comparator is connected with timing unit.
8. circuit according to claim 6, is characterized in that, the resistance of the 3rd resistance in described timing unit differs 2-3 the order of magnitude with the resistance of the 4th resistance.
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| JP2018098092A (en) * | 2016-12-15 | 2018-06-21 | オムロン株式会社 | Navigation lamp control system and illumination lamp control system |
| TWI625929B (en) * | 2017-07-20 | 2018-06-01 | 益航電子股份有限公司 | Motor apparatus and motor driving circuit |
| CN107395175B (en) * | 2017-09-04 | 2023-09-22 | 云南电网有限责任公司电力科学研究院 | MOS tube overcurrent protection circuit |
| CN108574259A (en) * | 2018-06-22 | 2018-09-25 | 深圳市高胜科研电子有限公司 | A kind of protective device of direct current supply, system and control method |
| CN109245055B (en) * | 2018-09-30 | 2024-05-31 | 上海鲲悟丰电科技有限公司 | Power conversion system, overcurrent protection circuit and method of power switch tube |
| CN110783884B (en) * | 2019-10-17 | 2022-06-14 | 安徽省航嘉智源科技有限公司 | Short circuit self-recovery method and system |
| CN112234693A (en) * | 2020-08-28 | 2021-01-15 | 珠海格力电器股份有限公司 | Bus charging control device, driver and bus charging control method thereof |
| CN116627205A (en) * | 2022-02-10 | 2023-08-22 | 比亚迪股份有限公司 | Follower circuit, vehicle power supply circuit and vehicle |
| CN116224011B (en) * | 2023-04-25 | 2023-07-21 | 苏州锴威特半导体股份有限公司 | Power tube overcurrent detection circuit |
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