CN102810475A - High-density groove-type power semiconductor structure and manufacturing method thereof - Google Patents
High-density groove-type power semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN102810475A CN102810475A CN2011101422223A CN201110142222A CN102810475A CN 102810475 A CN102810475 A CN 102810475A CN 2011101422223 A CN2011101422223 A CN 2011101422223A CN 201110142222 A CN201110142222 A CN 201110142222A CN 102810475 A CN102810475 A CN 102810475A
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Abstract
The invention provides a high-density groove-type power semiconductor structure and a manufacturing method thereof. The manufacturing method includes the steps of forming at least one grid groove in a basic silicon material, one grid oxide layer covered on a naked surface of the basic silicon material, one polycrystalline silicon grid structure in the grid groove, one insulating layer in the grid groove and covered on the polycrystalline silicon grid structure, and one body area with a first conductivity type; pouring adulterants of a second conductive type in the body areas to from source electrode doped regions; removing part of the grid oxide layers and part of the insulating layers to make the polycrystalline silicon grid structures and the source electrode doped regions naked; forming insulation structures in a certain thickness on side walls of the grid grooves; depositing metal layers on the surfaces of the polycrystalline silicon grid structures and the surfaces of the source electrode doped regions, heating, and forming first self-aligned metal silicide layers on the surfaces of the polycrystalline silicon grid structures and second self-aligned metal silicide layers on the surfaces of the source electrode doped regions; and forming dielectric structures on the first self-aligned metal silicide layers, metal source electrode layers on the dielectric structures and the second self-aligned metal silicide layers.
Description
Technical field
The present invention relates to a kind of power semiconductor structure and manufacturing approach thereof, relate in particular to a kind of high-density, trench formula power semiconductor structure and manufacturing approach thereof.
Background technology
Figure 1A to Fig. 1 C is the part manufacturing approach of a conventional groove formula power semiconductor structure.Below describe is to be example with N type power MOSFET transistor (power MOSFET).Shown in Figure 1A, at first, a N type silicon substrate 110 is provided.Then, utilize a light shield (not shown) to define the position of gate trench 120, and utilize etched mode, in N type silicon substrate 110, produce a plurality of gate trenchs 120.Subsequently, form a grid oxic horizon 130 in the surface that N type silicon substrate 110 exposes.Next, deposit a polysilicon layer and be covered on the grid oxic horizon 130, and fill up gate trench 120.Then, eat-back (etch back) and remove the part polysilicon layer that is positioned at N type silicon substrate 110 tops, to constitute a plurality of polysilicon gate constructions 140.
Then; Shown in Figure 1B, form an insulating barrier 131 and be covered on the polysilicon gate construction 140, next; Mode with comprehensive implanting ions (blanket on implantation) is injected P type alloy in N type silicon substrate 110, to form a heavily doped region (not shown).Then, shown in Fig. 1 C, the manufacture process that drives in (drive-in) with heating spreads the P type alloy of injection downwards, and formation one is positioned at the P type body (body) 150 of N type silicon substrate 110.Subsequently, inject N type alloy in P type body 150, impose the manufacture process that heating drives in again, to form one source pole doped region 160.
For the size of dwindling metal-oxide half field effect transistor to improve element integration (integration), the width of the width of gate trench 120 and source doping region 160 also must dwindle again.Yet, during the reduced width of gate trench 120, can cause the resistance of polysilicon gate construction 140 significantly to promote, and relatively transistorized switch speed caused adverse influence, and then cause the increase of switch cost (switching loss); And during the reduced width of source doping region 160, can cause the contact resistance of source doping region 160 to rise, make transistor conduct resistance significantly promote, and then cause the increase of conduction loss (conduction loss).Thereby how effectively to improve the groove power semiconductor structure, and make it have low grid impedance and transistor conduct resistance (Low Rds (ON)), become urgent problem.
Therefore, seeking a high-density, trench formula power semiconductor structure that has low on-resistance, to overcome the many disadvantages of known technology, is the important problem in present technique field.
Summary of the invention
Technical problem to be solved by this invention is; Deficiency to prior art; A kind of have high-density, trench formula power semiconductor structure and manufacturing approach thereof are provided, can reduce grid impedance and transistor conduct resistance effectively, and then reach the grade that transistor size dwindles again.
The present invention solves the problems of the technologies described above through following scheme:
For achieving the above object, the present invention provides a kind of manufacturing approach of high-density, trench formula power semiconductor structure.Comprise the following steps: to form at least one gate trench earlier in a silicon substrate, then, form the exposed surface that a grid oxic horizon covers this silicon substrate.Next, form a grid polycrystalline silicon structure in this gate trench after, form an insulating barrier again in this gate trench and cover this grid polycrystalline silicon structure.Next, formation has a body of one first conductivity type, then, injects second conductivity type dopant in above-mentioned body, in order to form the one source pole doped region.Next, remove this grid oxic horizon of part and this insulating barrier, with the surface of exposed this grid polycrystalline silicon structure and this source doping region.Subsequently, form the sidewall of an insulation system in this gate trench, this insulation system has a predetermined thickness.Next; Deposit the surface of a metal level in this grid polycrystalline silicon structure and this source doping region; And impose a heating processing, with form this first self-aligned metal silicate layer in the surface of this grid polycrystalline silicon structure and this second self-aligned metal silicate layer in the surface of this source doping region.At last, form a dielectric structure on this first self-aligned metal silicate layer, and form the one source pole metal level on this dielectric structure and this second self-aligned metal silicate layer.Wherein, this insulation system is in order to form one suitably apart between this first self-aligned metal silicate layer and this second self-aligned metal silicate layer.
The present invention also provides a kind of power semiconductor structure of high-density, trench formula.Comprise: a silicon substrate, a plurality of gate trenchs are positioned at this silicon substrate, and wherein each gate trench comprises: a grid oxic horizon, be covered in the inner surface of this gate trench, and
One grid polycrystalline silicon structure is positioned at this gate trench, and, a upper surface of this grid polycrystalline silicon structure and the opening of this gate trench preset distance of being separated by.One body is between this adjacent gate trench.The one source pole doped region is positioned at a top of this body.One insulation system is positioned at this grid polycrystalline silicon superstructure, and covers a sidewall of this gate trench.One first self-aligned metal silicate layer is positioned at a upper surface of this grid polycrystalline silicon structure, the upper surface of this first self-aligned metal silicate layer be positioned at this source class doped region half below the degree of depth.One second self-aligned metal silicate layer is positioned at a upper surface of this source doping region.One dielectric structure is inserted this gate trench, to cover this first self-aligned metal silicate layer.And the one source pole metal level electrically connects this source doping region through this second self-aligned metal silicate layer.
Above general introduction and ensuing detailed description are all exemplary in nature, are in order to further specify claim protection range of the present invention.And about other purposes of the present invention and advantage, will in follow-up explanation and accompanying drawing, set forth.
Description of drawings
Figure 1A to Fig. 1 C is the part manufacturing approach of the groove power semiconductor structure of prior art;
Fig. 2 A to Fig. 2 E is the embodiment one of the manufacture method of groove power semiconductor structure of the present invention;
Fig. 3 A to Fig. 3 B is the embodiment two of the manufacture method of groove power semiconductor structure of the present invention;
Fig. 4 A to Fig. 4 B is the embodiment three of the manufacture method of groove power semiconductor structure of the present invention.
[main element description of reference numerals]
Prior art:
Gate trench 120
Grid oxic horizon 130
Insulating barrier 131
Polysilicon gate construction 140
The present invention:
Silicon substrate 210,310
Gate trench 220,320
Grid oxic horizon 230,330
Insulating barrier 231,334
Insulation system 233,433
Grid polycrystalline silicon structure 240,340
Body 250,450
Source doping region 260,460 '
The second conductivity type doped region 461
Metal silicide layer 270,472 '
Gate metal silicide layer 271
Embodiment
Major technique of the present invention is characterised in that the manufacturing approach of utilizing self-aligned metal silicate (salicide); Form metal silicide on polysilicon gate construction in gate trench and the source doping region; When solving reduction of gate groove and source dopant sector width, grid impedance that is met with and the transistor conduct resistance problem that significantly rises.This is very important problem for the deep-submicron element, because contact resistance and contact area are inversely proportional to, after element dwindles; Contact resistance can relatively increase, and then influences the driving force of element, therefore utilizes the present invention further to reach again and dwindles transistor size; Lift elements integration (integration) in addition, also can be saved the shared area of element in the circuit layout design; Reduce parasitic capacitance, improve the operating at high-frequency characteristic.
Fig. 2 A to Fig. 2 E is the embodiment one of the manufacture method of groove power semiconductor structure of the present invention.Shown in Fig. 2 A, form a plurality of gate trenchs 220 in a silicon substrate 210.Subsequently, form the exposed surface that a grid oxic horizon 230 covers this silicon substrate 210, comprise the inner surface of gate trench 220 and the upper surface of silicon substrate 210.This grid oxic horizon 230 can also be replaced by the material of other insulation.Next; Form a gate polysilicon layer in the last and gate trench 220 of grid oxic horizon 230, and with removing with gate trench 220 interior gate polysilicon layers partly on the silicon substrate 210, to form grid polycrystalline silicon structure 240 in gate trench 220; And the top of this grid polycrystalline silicon structure 240; There is a suitable distance L in surface (shown in the figure dotted line) with silicon substrate 210, and this L distance is about 1000～3000 dusts.Then, form an insulating barrier, and the insulating barrier that silicon substrate 210 tops are unnecessary and grid oxic horizon 230 remove in grid polycrystalline silicon structure 240 and silicon substrate 210 tops, only stay have adequate thickness insulating barrier 231 on grid polycrystalline silicon structure 240.With regard to a preferred embodiment, the aforementioned dielectric layer can be made up of silica, and unnecessary insulating barrier and grid oxic horizon 230 can directly adopt the manufacturing approach of eat-backing (etch back) to remove in the lump.
Subsequently, form a buffer insulation layer 232 on the insulating barrier 231 with silicon substrate 210 on, these buffer insulation layer 232 thickness are about 200～300 dusts, in the time of can preventing follow-up ion implantation step, the pollution that diffusion of impurities caused.Above-mentioned grid oxic horizon 230, insulating barrier 231 also can be same substance with buffer insulation layer 232.
Next, shown in Fig. 2 B, inject first conductivity type dopant in silicon substrate 210, to form a doped region (not shown).Subsequently, to first conductivity type dopant in the doped region, carry out thermal diffusion process.In this thermal diffusion process, the alloy in the doped region spreads downwards, and forms a body 250.Subsequently; Inject second conductivity type dopant in body 250; And impose another road thermal diffusion process, to form source doping region 260 in the surface of silicon substrate 210, the bottom of this source doping region 260 (degree of depth) must be lower than the upper surface of grid polycrystalline silicon structure 240.
Next, shown in Fig. 2 C, remove insulating barrier 231 and buffer insulation layer 232, and expose the upper surface of grid polycrystalline silicon structure 240 and silicon substrate 210, subsequently, form the sidewall that an insulation system 233 exposes in gate trench 220.The thickness of this insulation system 233 is about 700～3000 dusts; When can be used to prevent that the groove power semiconductor physical dimension from dwindling again; The source metal silicide layer touches gate metal silicide layer (being formed in the successive process), causes the damage of groove power semiconductor.With preferred embodiment, the thickness of above-mentioned insulation system 233 is greater than the thickness of grid oxic horizon 230.
Subsequently, shown in Fig. 2 D, deposit a metal level, and impose the processing of the annealing that is rapidly heated for the first time, the intensification temperature is about 760C, makes reaction generation silicide on the interface of metal level and source doping region 260, grid polycrystalline silicon structure 240.As for receiving the source doping region 260 that insulation system 233 is covered, then can not be reacted into metal silicide, so this step is self aligned process with metal level.Subsequently, utilize selective etch again, remove the unreacted metal material, stay the metal silicide layer 270 that forms source doping region 260 tops, with the gate metal silicide layer 271 of grid polycrystalline silicon structure 240 tops.In order further to reduce the resistance of metal silicide, can select to do again secondary intensification annealing in process, at this moment, the intensification temperature is about 850C.Above-mentioned metal level generally is selected from the material crowd of Ti (TiN), Co, Ni and composition thereof, can be different metallic according to demand.In order to prevent that metal silicide layer 270 from touching gate metal silicide layer 271, the vertical range of the surface of above-mentioned gate metal silicide layer 271 and metal silicide layer 270 is preferably greater than the half thickness (shown in dotted line) of source doping region 260.On grid polycrystalline silicon structure 240 and source doping region 260, utilize the self-aligned metal silicate manufacture process to accomplish metal silicide layer, can effectively reduce contact resistance, and the driving force of further lift elements.
Next, shown in Fig. 2 E, the dielectric structure 234 that forms a suitable thickness is covered on the gate metal silicide layer 271, and is last, and deposition one source pole metal level 280 is on dielectric structure 234 and metal silicide layer 270, with electrically connect to source doping region 260.With preferred embodiment, the surface of silicon substrate 210 is approached on the surface of above-mentioned dielectric structure 234, is linked to source metal 280 fully to guarantee metal silicide layer 270.Secondly, in the present embodiment, dielectric structure 234 covers insulation system 233 fully.But, the present invention is not limited to this, and above-mentioned insulation system 233 also can not need all to be covered by dielectric structure 234.
Fig. 3 A to Fig. 3 B is the embodiment two of the manufacture method of groove power semiconductor structure of the present invention.Wherein with the difference place of embodiment one, shown in Fig. 3 A figure, after grid polycrystalline silicon structure 340 is accomplished; Remove earlier and be positioned at partly grid oxic horizons 330 of silicon substrate 310 surface and gate trench 320, subsequently, shown in Fig. 3 B schemes; Form insulating barrier 334 in grid polycrystalline silicon structure 340 and silicon substrate 310 tops; Because the doping content of grid polycrystalline silicon structure 340 is greater than silicon substrate 310, when insulating barrier 334 formed, the growth rate of insulating barrier on the grid polycrystalline silicon structure 340 (oxide layer) can be greater than the insulating barrier on the silicon substrate 310 (oxide layer); Therefore; Insulating barrier 334 on grid polycrystalline silicon structure 340 can have adequate thickness, and to keep out the ion implantation step of follow-up source doping region, the impurity of avoiding source doping region simultaneously is diffused into 340 li on grid polycrystalline silicon structure via the side of gate trench; Later step is identical with embodiment one, does not repeat them here.
Fig. 4 A to Fig. 4 B is the embodiment three of the manufacture method of groove power semiconductor structure of the present invention.Wherein with the difference place of embodiment one, be to form the step of the thermal diffusion process of source doping region, be delayed to the annealing in process that is rapidly heated of metal silicide and accomplish.Shown in Fig. 4 A, after forming body 450, inject second conductivity type dopant in body 450; Form the second conductivity type doped region 461; Next, remove part of grid pole oxide layer and insulating barrier (not shown), and expose the upper surface of grid polycrystalline silicon structure 440; Subsequently, form the sidewall that insulation system 433 exposes in gate trench.Next; Deposit a metal level 472 on the grid polycrystalline silicon structure 440 and the second conductivity type doped region 461, next, shown in Fig. 4 B; Impose the annealing in process that is rapidly heated; Form source doping region 460 ' and metal silicide layer 472 ' simultaneously, later step is identical with embodiment one, does not repeat them here.
As stated, the present invention discloses with preferred embodiment hereinbefore, and those of ordinary skills it should be understood that this embodiment only is used to describe the present invention, and should not be read as restriction scope of the present invention.It should be noted,, all should be made as and be covered by in the category of the present invention such as with the variation and the displacement of this embodiment equivalence.Therefore, protection scope of the present invention is as the criterion when the content that defined with the claim protection range of hereinafter.
Claims (11)
1. the manufacturing approach of a high-density, trench formula power semiconductor structure is characterized in that, comprises the following steps:
Form at least one gate trench in a silicon substrate;
Form the exposed surface that a grid oxic horizon covers this silicon substrate;
Form a grid polycrystalline silicon structure in this gate trench;
Form an insulating barrier in this gate trench and cover this grid polycrystalline silicon structure;
Formation has a body of one first conductivity type;
Inject one second conductivity type dopant in this body, in order to form the one source pole doped region;
Remove this grid oxic horizon of part and this insulating barrier, with the surface of exposed this grid polycrystalline silicon structure and this source doping region;
Form the sidewall of an insulation system in this gate trench, this insulation system has a predetermined thickness;
Deposit the exposed surface of a metal level in this grid polycrystalline silicon structure and this source doping region; And impose a heating processing, with form one first self-aligned metal silicate layer in the surface of this grid polycrystalline silicon structure and one second self-aligned metal silicate layer in the surface of this source doping region;
Form a dielectric structure in this gate trench, to cover this first self-aligned metal silicate layer; And
Form the one source pole metal level on this dielectric structure and this second self-aligned metal silicate layer.
2. the manufacturing approach of high-density, trench formula power semiconductor structure as claimed in claim 1 is characterized in that, wherein, after the step of injecting this second conductivity type dopant, also comprises imposing one source pole doping thermal diffusion process.
3. the manufacturing approach of high-density, trench formula power semiconductor structure as claimed in claim 1; It is characterized in that; Wherein, the vertical range of the upper surface of this first self-aligned metal silicate layer and this second self-aligned metal silicate layer half the greater than the degree of depth of this source class doped region.
4. the manufacturing approach of high-density, trench formula power semiconductor structure as claimed in claim 1 is characterized in that, wherein, this grid oxic horizon, this insulating barrier, this insulation system and this dielectric structure are to be made up of same substance.
5. the manufacturing approach of high-density, trench formula power semiconductor structure as claimed in claim 1; It is characterized in that; Wherein, Remove part this grid oxic horizon and this insulating barrier, comprise: before forming the step of this insulating barrier in this gate trench, remove this grid oxic horizon partly with the sidewall that exposes this gate trench and the surface of this silicon substrate with the step of exposed this grid polycrystalline silicon structure with the surface of this source doping region.
6. the manufacturing approach of high-density, trench formula power semiconductor structure as claimed in claim 1 is characterized in that, wherein, after forming the step of this insulating barrier in this gate trench, also comprises:
Form a buffer insulation layer on this insulating barrier.
7. the power semiconductor structure of a high-density, trench formula is characterized in that, comprising:
One silicon substrate;
A plurality of gate trenchs are positioned at this silicon substrate:
One grid oxic horizon is covered in the inner surface of this gate trench;
One grid polycrystalline silicon structure is positioned at this gate trench, and, a upper surface of this grid polycrystalline silicon structure and the opening of this gate trench preset distance of being separated by;
One body is between this adjacent gate trench;
The one source pole doped region is positioned at a top of this body;
One insulation system is positioned at this grid polycrystalline silicon superstructure, and covers a sidewall of this gate trench;
One first self-aligned metal silicate layer is positioned at a upper surface of this grid polycrystalline silicon structure;
One second self-aligned metal silicate layer is positioned at a upper surface of this source doping region;
One dielectric structure is inserted this gate trench, to cover this first self-aligned metal silicate layer; And
The one source pole metal level electrically connects this source doping region through this second self-aligned metal silicate layer.
8. the power semiconductor structure of high-density, trench formula as claimed in claim 7; It is characterized in that; Wherein, the vertical range of the upper surface of this first self-aligned metal silicate layer and this second self-aligned metal silicate layer half the greater than the degree of depth of this source class doped region.
9. the power semiconductor structure of high-density, trench formula as claimed in claim 7 is characterized in that, wherein, the thickness of this insulation system is greater than the thickness of this grid oxic horizon.
10. the power semiconductor structure of high-density, trench formula as claimed in claim 7 is characterized in that, wherein, this dielectric structure covers this insulation system.
11. the power semiconductor structure of high-density, trench formula as claimed in claim 7 is characterized in that, wherein, this first self-aligned metal silicate layer and this second self-aligned metal silicate layer are to be made up of same substance.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5027185A (en) * | 1988-06-06 | 1991-06-25 | Industrial Technology Research Institute | Polycide gate FET with salicide |
| US6489204B1 (en) * | 2001-08-20 | 2002-12-03 | Episil Technologies, Inc. | Save MOS device |
| US20030168695A1 (en) * | 2002-03-07 | 2003-09-11 | International Rectifier Corp. | Silicide gate process for trench MOSFET |
| US6841830B2 (en) * | 2002-12-31 | 2005-01-11 | Industrial Technology Research Institute | Metal oxide semiconductor field effect transistors (MOSFETS) used in ink-jet head chips and method for making the same |
-
2011
- 2011-05-30 CN CN2011101422223A patent/CN102810475A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5027185A (en) * | 1988-06-06 | 1991-06-25 | Industrial Technology Research Institute | Polycide gate FET with salicide |
| US6489204B1 (en) * | 2001-08-20 | 2002-12-03 | Episil Technologies, Inc. | Save MOS device |
| US20030168695A1 (en) * | 2002-03-07 | 2003-09-11 | International Rectifier Corp. | Silicide gate process for trench MOSFET |
| US6841830B2 (en) * | 2002-12-31 | 2005-01-11 | Industrial Technology Research Institute | Metal oxide semiconductor field effect transistors (MOSFETS) used in ink-jet head chips and method for making the same |
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Application publication date: 20121205 |