CN102809724A - Circuit board assembling process quality evaluation testing component and design method thereof - Google Patents
Circuit board assembling process quality evaluation testing component and design method thereof Download PDFInfo
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- CN102809724A CN102809724A CN2012102740887A CN201210274088A CN102809724A CN 102809724 A CN102809724 A CN 102809724A CN 2012102740887 A CN2012102740887 A CN 2012102740887A CN 201210274088 A CN201210274088 A CN 201210274088A CN 102809724 A CN102809724 A CN 102809724A
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Abstract
The invention discloses a design method of a circuit board assembling process quality evaluation testing component, comprising the design of a testing device and a testing circuit board; the testing device is designed by adopting an encapsulation mode same as that of actual devices on a circuit board to be evaluated, the testing circuit board is designed in accordance with the circuit board to be evaluated, and a pin interconnecting structure of the testing device and a welding pad interconnecting structure of the testing circuit board are designed in accordance with evaluation requirements, then interconnected pins and welding pads are mutually gripped so as to form a series loop; and finally the testing device is encapsulated onto the testing circuit board in accordance with an assembling process of the circuit board to be evaluated so as to obtain the testing component. In this way, the assembling process of an area to be evaluated on the circuit board to be evaluated is reflected to the testing component, and the quality of the assembling process of a circuit board component to be evaluated can be mastered accurately and quantitatively when the testing component is taken as a reliability testing object. With the adoption of the design method of the circuit board assembling process quality evaluation testing component, the testing component can be obtained.
Description
Technical field
The present invention relates to the electronic product reliability technical field of measurement and test, particularly relate to a kind of circuit board assembling processing quality evaluation test assembly and method for designing thereof.
Background technology
On the printed circuit board assembly, the major function of interconnection solder joint (soldered ball) is to realize being electrically connected and forming the mechanical support of components and parts on circuit board between the electronic devices and components.Though the function of solder joint is simple, its influence is most important, and statistics shows: in the failure cause of electronic product, the interconnection solder joint failure is one of electronic package, equipment and machine system cause faults.Therefore, the printed circuit assembly packaging technology quality of how effectively assessing in the electronic product is to guarantee product quality and the necessary condition that guarantees application requirements.
At present, following two kinds of approach are generally taked in the q&r evaluation of assembling solder joint on the printed circuit assembly:
1, screens through checkout equipment
Usually adopt methods such as outside visual inspection and X-Ray detection to carry out sampling Detection, reject the product that obvious mass defect is arranged, like solder joint air entrapment, dewetting, rosin joint, wellability difference etc., this method is especially commonly used under the unsettled situation of packaging technology.
2, through accelerated test check reliability of products
According to the application conditions of product, through adding the inefficacy of tight working stress and environmental stress conditions expedite product, to reach rapid evaluation to product reliability.This kind method relates to the problem of test specimen, and method commonly used at present is in the product of producing in batches, to sample as test specimen.In the process of the test, through regularly carrying out Function detection judges whether product lost efficacy.
The 1st kind of method has following weak point: at first, screen through checkout equipment, can only observe the assembly of obvious mass defect; And because human factor causes random and undulatory property is very big; Simultaneously, unconspicuous to process stabilizing, packaging technology defective, this method is also inapplicable.
Method is carried out fail-test to actual product in the 2nd; The packaging technology quality of reactor product reasonably; But have several technical disadvantages: 1) test findings is the concentrated expression to the actual product reliability; Comprised the problem that many non-packaging technology quality cause, only can't distinguish the product failure problem that processing quality and starting material cause with test findings; 2) the solder joint conducting resistance is very little; Except that solder joint cracking causes the open circuit situation, can't effectively detect the change in resistance that the degeneration of single solder joint causes, therefore; Effectively welding spot reliability, 3 are assembled in quantitative evaluation) can't in process of the test, the butt welding point degenerative process carry out on-line real time monitoring.
Summary of the invention
Based on above-mentioned situation, the present invention proposes a kind of circuit board assembling processing quality evaluation test assembly and method for designing thereof, this test assembly is detected, can assemble processing quality to circuit board and carry out accurately quantitative assessment.
A kind of method for designing of circuit board assembling processing quality evaluation test assembly comprises step:
Analyze the Solder Joint and the distribution of circuit board to be assessed, selected assessment area;
Components and parts type and packing forms in the said assessment area of analysis and arrangement;
Device is used in footprint design test according to components and parts in the said assessment area, and requires the pin interconnection structure of the said test of design with device according to the assessment of circuit board assembling processing quality;
Use circuit board according to said board design test to be assessed; And, make the mutual interlock of said pin interconnection structure and said interconnected structure form series loop according to the interconnected structure of the said test of circuit board assembling processing quality assessment requirement design with circuit board;
Adopt and the identical packaging technology of said circuit board to be assessed, with said test with device package to said test with on the circuit board, obtain the test assembly that said circuit board to be assessed is carried out the packaging technology quality evaluation.
A kind of circuit board assembling processing quality evaluation test assembly comprises testing with device and test and uses circuit board,
Said test is with having the pin interconnection structure corresponding with the assessment area of circuit board to be assessed on the device; Said pin interconnection structure coincidence circuit plate packaging technology quality evaluation requirement, said test is consistent with the packing forms of the components and parts in said circuit board to be assessed zone to be assessed with the packing forms of device;
Said test is with the assessment area corresponding bonding pad interconnection structure that has on the circuit board with circuit board to be assessed, and said interconnected structure meets circuit board group dress processing quality assessment requirement;
Said test with device package said test with circuit board on, packaging technology is identical with the packaging technology of said circuit board to be assessed, the mutual interlock of said pin interconnection structure and said interconnected structure forms series loop.
Circuit board assembling processing quality evaluation test assembly of the present invention; Comprise device and assembled plate, the packing forms of device is identical with the packing forms of circuit board to be assessed, and the packaging technology of device and assembled plate is identical with the packaging technology of circuit board to be assessed; The adjacent solder balls interconnection of device; The interconnection of the adjacent pad of assembled plate, the mutual interlock of the soldered ball of interconnection and the pad of interconnection forms series loop, and what need on series loop and the circuit board to be assessed that emphasis assesses is regional corresponding.So, the packaging technology in zone to be assessed is reflected on this test assembly on the circuit board to be assessed, is subjects with this test assembly, can accurately understand the packaging technology quality of circuit board to be assessed quantitatively.Adopt the method for designing of circuit board assembling processing quality evaluation test assembly of the present invention, can obtain above-mentioned test assembly.
Description of drawings
Fig. 1 is the schematic flow sheet of the method for designing of circuit board assembling processing quality evaluation test assembly of the present invention;
Fig. 2 is a BGA device synoptic diagram of setting up the soldered ball interconnection structure;
Fig. 3 is an assembled plate synoptic diagram of setting up the interconnected structure;
The test assembly synoptic diagram that Fig. 4 forms on the assembled plate for the BGA set of devices installs to.
Embodiment
The present invention proposes a kind of test assembly and method for designing thereof that is used for qualitative assessment circuit board assembling processing quality; Adopt the test assembly of this method design; Can realize accurate, quick, qualitative assessment to printed circuit assembly packaging technology quality; And can realize the whole process monitoring of solder joint failure process, judge according to failure procedure to cause the main technique quality problems that lost efficacy.Below in conjunction with accompanying drawing and the present invention of embodiment illustrated in detail.
The method for designing of circuit board assembling processing quality evaluation test assembly of the present invention, as shown in Figure 1, comprise step:
The Solder Joint and the distribution of step S1, analysis circuit board to be assessed, selected assessment area;
Components and parts type and packing forms in step S2, the said assessment area of analysis and arrangement;
Step S3, use device, and require to design the pin interconnection structure of said test with device according to the assessment of circuit board assembling processing quality according to the test of the footprint design of components and parts in the said assessment area;
Step S4, use circuit board according to said board design to be assessed test; And, make the mutual interlock of said pin interconnection structure and said interconnected structure form series loop according to the interconnected structure of the said test of circuit board assembling processing quality assessment requirement design with circuit board;
Step S5, employing and the identical packaging technology of said circuit board to be assessed, with said test with device package to said test with on the circuit board, obtain the test assembly that said circuit board to be assessed is carried out the packaging technology quality evaluation.
Adopt the design's method, at first of step S 1, be that circuit board to be assessed is analyzed to actual product; Understand the main Solder Joint and the distribution thereof that exist on the plate; Confirm local mechanical or the concentrated zone of thermal stress on the plate, like the rigging position of circuit board periphery, simultaneously; Confirm solder joint type and the position thereof that to pay close attention in the actual product, like ball bar permutation encapsulation (BGA) type high-density packages solder joint.To selected assessment area, the series loop layout of design monitoring solder joint according to overall layout requirement, is carried out interconnect traces design with device and test with circuit board to test respectively then.At last, according to the packaging technology identical test is assembled with circuit board with device and test with actual product.
The design of series loop is the test assembly key for design, is example with the ball bar permutation of 100 pins encapsulation (BGA) device.At first, be one group with 2 soldered balls, 100 soldered ball pins of BGA device are divided into 50 groups; Two soldered balls of every group are realized interconnection through the copper layer that covers on the base plate for packaging, form BGA device interconnected structure as shown in Figure 2, simultaneously; The interconnection structure of corresponding BGA device, design can be covered copper layer conducting structure with the mutual interlock of device interconnected structure forms series loop on assembled plate, and is as shown in Figure 3; At last; Adopt the packaging technology identical will test with device package to test, forms welding spot reliability test assembly as shown in Figure 4, the complete series loop of all solder joints formation in the assembly on the same device with on the circuit board with actual product.Actual product needs the zone of emphasis assessment maybe more than one, and the then final series loop that forms is more than one.
In the series loop of whole interconnection solder joint, conductive material all is good conductor, and resistance in series is less, and therefore, series connection solder joint two ends should be designed to four-wire method resistance test port, monitor the series loop resistance through microhmmeter.
Circuit board assembling processing quality evaluation test assembly of the present invention is the test assembly that adopts above-mentioned designing method to go out, and is as shown in Figure 4, comprises testing and uses circuit board with device and test.
Said test is with having the pin interconnection structure corresponding with the assessment area of circuit board to be assessed on the device; Said pin interconnection structure coincidence circuit plate packaging technology quality evaluation requirement, said test is consistent with the packing forms of the components and parts in said circuit board to be assessed zone to be assessed with the packing forms of device;
Said test is with the assessment area corresponding bonding pad interconnection structure that has on the circuit board with circuit board to be assessed, and said interconnected structure meets circuit board group dress processing quality assessment requirement;
Said test with device package said test with circuit board on, packaging technology is identical with the packaging technology of said circuit board to be assessed, the mutual interlock of said pin interconnection structure and said interconnected structure forms series loop.
The concrete structure of said soldered ball interconnection structure is: adjacent two soldered balls are one group, and every group of two soldered balls link to each other through the copper layer that covers on the said device packaging substrate; The concrete structure of said interconnected structure is: adjacent two pads are one group, and every group of two pads link to each other through the copper layer that covers on the said assembled plate.
The two ends of the series loop that forms in the mutual interlock of said soldered ball interconnection structure and said interconnected structure have four-wire method resistance test port.
The other technologies characteristic of this test assembly is identical with above-mentioned method for designing, does not repeat them here.
Adopt the test assembly of above-mentioned designing method to have the following advantages:
1, can objectively respond the packaging technology quality of actual product, avoid the influence of human factor quality assessment;
2, only estimate, got rid of of the influence of other qualitative factors, make the processing quality evaluation result more accurate evaluation result to the packaging technology quality;
3, adopt the method for designing of series loop, realized detection by quantitative, reached the purpose of qualitative assessment the degeneration of assembling solder joint;
4, can realize the on-line monitoring of butt welding point connected condition through the real-time collection of computer realization data, the degenerative process of accurate recording assembling solder joint.
The above embodiment has only expressed several kinds of embodiments of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to claim of the present invention.Should be pointed out that for the person of ordinary skill of the art under the prerequisite that does not break away from the present invention's design, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with accompanying claims.
Claims (6)
1. the method for designing of a circuit board assembling processing quality evaluation test assembly is characterized in that, comprises step:
Analyze the Solder Joint and the distribution of circuit board to be assessed, selected assessment area;
Components and parts type and packing forms in the said assessment area of analysis and arrangement;
Device is used in footprint design test according to components and parts in the said assessment area, and requires the pin interconnection structure of the said test of design with device according to the assessment of circuit board assembling processing quality;
Use circuit board according to said board design test to be assessed; And, make the mutual interlock of said pin interconnection structure and said interconnected structure form series loop according to the interconnected structure of the said test of circuit board assembling processing quality assessment requirement design with circuit board;
Adopt and the identical packaging technology of said circuit board to be assessed, with said test with device package to said test with on the circuit board, obtain the test assembly that said circuit board to be assessed is carried out the packaging technology quality evaluation.
2. the method for designing of circuit board assembling processing quality evaluation test assembly according to claim 1 is characterized in that,
The concrete structure of said pin interconnection structure is: two soldered balls are one group, every group of two pin through said test with on the device packaging substrate cover the copper layer or bonding wire is realized interconnection;
The concrete structure of said interconnected structure is: two pads are one group, and every group of two pads are realized interconnection through said test with the copper layer that covers on the circuit board.
3. the method for designing of circuit board assembling processing quality evaluation test assembly according to claim 1 and 2 is characterized in that, also comprises step:
The two ends design four-wire method resistance test port of the series loop that forms in the mutual interlock of said pin interconnection structure and said interconnected structure.
4. a circuit board assembling processing quality evaluation test assembly is characterized in that, comprise testing and use circuit board with device and test,
Said test is with having the pin interconnection structure corresponding with the assessment area of circuit board to be assessed on the device; Said pin interconnection structure coincidence circuit plate packaging technology quality evaluation requirement, said test is consistent with the packing forms of the components and parts in said circuit board to be assessed zone to be assessed with the packing forms of device;
Said test is with the assessment area corresponding bonding pad interconnection structure that has on the circuit board with circuit board to be assessed, and said interconnected structure meets circuit board group dress processing quality assessment requirement;
Said test with device package said test with circuit board on, packaging technology is identical with the packaging technology of said circuit board to be assessed, the mutual interlock of said pin interconnection structure and said interconnected structure forms series loop.
5. circuit board assembling processing quality evaluation test assembly according to claim 4 is characterized in that,
The concrete structure of said pin interconnection structure is: two pins are one group, every group of two pin through said test with on the device packaging substrate cover the copper layer or bonding wire links to each other;
The concrete structure of said interconnected structure is: adjacent two pads are one group, and every group of two pads link to each other with the copper layer that covers on the circuit board through said test.
6. according to claim 4 or 5 described circuit boards assembling processing quality evaluation test assemblies, it is characterized in that having four-wire method resistance test port at the two ends of the series loop of the mutual interlock formation of said pin interconnection structure and said interconnected structure.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106932706A (en) * | 2015-12-31 | 2017-07-07 | 中国运载火箭技术研究院 | A kind of ceramic package monolithic integrated circuit structure analysis method |
| CN113597133A (en) * | 2021-07-23 | 2021-11-02 | 惠州西文思技术股份有限公司 | Medical PCB and assembling process thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6677169B1 (en) * | 2001-08-02 | 2004-01-13 | Advanced Micro Devices, Inc. | Method and system for backside device analysis on a ball grid array package |
| CN1624467A (en) * | 2003-12-03 | 2005-06-08 | 华为技术有限公司 | Method of testing oxperimental applicance |
| US20070296068A1 (en) * | 2006-06-26 | 2007-12-27 | Hamilton Sundstrand Corporation | In-situ monitoring and method to determine accumulated printed wiring board thermal and/or vibration stress fatigue using a mirrored monitor chip and continuity circuit |
| CN102576700A (en) * | 2009-09-02 | 2012-07-11 | 莫塞德技术公司 | Using interrupted through-silicon-vias in integrated circuits adapted for stacking |
-
2012
- 2012-07-31 CN CN2012102740887A patent/CN102809724A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6677169B1 (en) * | 2001-08-02 | 2004-01-13 | Advanced Micro Devices, Inc. | Method and system for backside device analysis on a ball grid array package |
| CN1624467A (en) * | 2003-12-03 | 2005-06-08 | 华为技术有限公司 | Method of testing oxperimental applicance |
| US20070296068A1 (en) * | 2006-06-26 | 2007-12-27 | Hamilton Sundstrand Corporation | In-situ monitoring and method to determine accumulated printed wiring board thermal and/or vibration stress fatigue using a mirrored monitor chip and continuity circuit |
| CN102576700A (en) * | 2009-09-02 | 2012-07-11 | 莫塞德技术公司 | Using interrupted through-silicon-vias in integrated circuits adapted for stacking |
Non-Patent Citations (6)
| Title |
|---|
| 万明等: "电路板级互连焊点故障监测和预警", 《半导体技术》 * |
| 任辉等: "BGA焊点的失效分析及热应力模拟", 《第十四届全国混合集成电路学术会议论文集》 * |
| 向可: "热载荷下无铅焊点可靠性电测方法研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 漆学利: "PBGA板级组件焊点随机振动可靠性分析与研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 王文等: "基于比例风险模型的板级无铅焊点跌落寿命分析", 《振动与冲击》 * |
| 王文等: "板级球栅阵列无铅焊点随机振动寿命分析", 《上海交通大学学报》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106932706A (en) * | 2015-12-31 | 2017-07-07 | 中国运载火箭技术研究院 | A kind of ceramic package monolithic integrated circuit structure analysis method |
| CN106932706B (en) * | 2015-12-31 | 2019-11-22 | 中国运载火箭技术研究院 | A kind of ceramic package monolithic integrated circuit structure analysis method |
| CN113597133A (en) * | 2021-07-23 | 2021-11-02 | 惠州西文思技术股份有限公司 | Medical PCB and assembling process thereof |
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Application publication date: 20121205 |