CN102779816B - Electrostatic discharge protective equipment - Google Patents
Electrostatic discharge protective equipment Download PDFInfo
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- CN102779816B CN102779816B CN201110121777.XA CN201110121777A CN102779816B CN 102779816 B CN102779816 B CN 102779816B CN 201110121777 A CN201110121777 A CN 201110121777A CN 102779816 B CN102779816 B CN 102779816B
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Abstract
The invention relates to a kind of electrostatic discharge protective equipment, be electrically connected a weld pad, and comprise K PNP transistor and protection circuit, wherein K is positive integer.The emitter-base bandgap grading of the 1st PNP transistor is electrically connected weld pad, the base stage of i-th PNP transistor is electrically connected the emitter-base bandgap grading of (i+1) individual PNP transistor, and the collector of a described K PNP transistor is electrically connected to earth terminal, i is integer and 1≤i≤(K-1).Between the base stage that protection circuit is electrically connected at K PNP transistor and earth terminal, and provide a discharge path.Wherein, from the electrostatic signal of weld pad by discharge path and described K PNP transistor conducting to earth terminal.By this; the present invention can will by PNP transistor conducting to earth terminal by the electrostatic signal from weld pad; reduce the rated current of bearing needed for protection circuit, and then reduce the layout area of protection circuit, reduce process shifts to the impact of electrostatic discharge protective equipment.
Description
Technical field
The present invention relates to a kind of electrostatic discharge protective equipment, particularly relate to a kind of electrostatic discharge protective equipment with the PNP transistor of serial connection.
Background technology
Static discharge (electrostatic discharge, ESD) is the phenomenon of the electrostatic displacement from non-conducting surfaces, its infringement that the semiconductor in integrated circuit and other circuit can be caused to form.Such as, the human body that carpet is walked, at the machine of encapsulated integrated circuit or the instrument of testing integrated circuits ... wait electrified body, can to chip discharge when touching chip, and the instantaneous power of this static discharge likely causes the integrated circuit in chip damage or lost efficacy.
In order to prevent integrated circuit from damaging because of static discharge phenomenon, the design of electrostatic discharge protective equipment all can be added in integrated circuits.Generally speaking; electrostatic discharge protective equipment has many designs; wherein common mode is exactly the two-stage N-type transistor utilizing serial connection, and reach the effect of electrostatic discharge (ESD) protection, the gate terminal of the two-stage N-type transistor be wherein connected in series all is biased in fixing voltage.But the esd protection ability that this kind of framework provides often is subject to the impact of process shifts, and then reduce the reliability of Esd protection device.
As can be seen here, above-mentioned existing electrostatic discharge protective equipment with in use in structure, obviously still has inconvenience and defect, and is urgently further improved.In order to solve above-mentioned Problems existing, relevant manufactures there's no one who doesn't or isn't seeks solution painstakingly, but have no applicable design for a long time to be completed by development, and common product does not have appropriate structure to solve the problem, this is obviously the anxious problem for solving of relevant dealer always.Therefore how to found a kind of electrostatic discharge protective equipment of new structure, one of current important research and development problem of real genus, also becomes the target that current industry pole need be improved.
Summary of the invention
The object of the invention is to; overcome the defect that existing electrostatic discharge protective equipment exists; and a kind of electrostatic discharge protective equipment of new structure is provided; technical problem to be solved makes it utilize the PNP transistor of serial connection by electrostatic signal conducting to earth terminal, to reduce the rated current of bearing needed for protection circuit.By this, the layout area of protection circuit can be lowered, and then reduces process shifts to the impact of electrostatic discharge protective equipment, is very suitable for practicality.
Another object of the present invention is to; overcome the defect that existing electrostatic discharge protective equipment exists; and a kind of electrostatic discharge protective equipment of new structure is provided; technical problem to be solved makes it utilize the PNP transistor of serial connection to provide multiple individual path, with by electrostatic signal conducting to earth terminal.By this, the rated current of bearing needed for protection circuit can be lowered, and then reduces process shifts to the impact of electrostatic discharge protective equipment, thus is more suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to a kind of electrostatic discharge protective equipment that the present invention proposes, be electrically connected a weld pad, and comprise K PNP transistor and protection circuit, wherein K is positive integer.The emitter-base bandgap grading of the 1st PNP transistor is electrically connected weld pad, the base stage of i-th PNP transistor is electrically connected the emitter-base bandgap grading of (i+1) individual PNP transistor, and the collector of a described K PNP transistor is electrically connected to earth terminal, i is integer and 1≤i≤(K-1).Between the base stage that protection circuit is electrically connected at K PNP transistor and earth terminal, and provide a discharge path.Wherein, from the electrostatic signal of weld pad by discharge path and described K PNP transistor conducting to earth terminal.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid electrostatic discharge protective equipment, wherein said weld pad is in order to receive high voltage signal, and electrostatic discharge protective equipment also comprises first control circuit.Wherein, first control circuit is electrically connected weld pad, and receives supply voltage.In addition, when supply voltage is supplied, first control circuit produces isolation voltage according to high voltage signal, and the specific PNP transistor in protection circuit or a described K PNP transistor, the leakage current of protection circuit or specific PNP transistor is flowed through according to isolation voltage suppression.
Aforesaid electrostatic discharge protective equipment, wherein said first control circuit comprises: one first PMOS transistor, and wherein the source electrode of this first PMOS transistor receives this high voltage signal; One first nmos pass transistor, wherein the drain electrode of this first nmos pass transistor is electrically connected the drain electrode of this first PMOS transistor, and the grid of this first nmos pass transistor receives this supply voltage, and the source electrode of this first nmos pass transistor is electrically connected this earth terminal; And one second PMOS transistor, wherein the source electrode of this second PMOS transistor receives this high voltage signal, the grid of this second PMOS transistor is electrically connected the drain electrode of this first PMOS transistor, the drain electrode of this second PMOS transistor is electrically connected the grid of this first PMOS transistor, and the drain electrode of this second PMOS transistor is in order to produce this isolation voltage.
Aforesaid electrostatic discharge protective equipment, wherein said weld pad is in order to receive high voltage signal, and electrostatic discharge protective equipment also comprises second control circuit.Wherein, second control circuit is electrically connected weld pad, and receives supply voltage.In addition, when supply voltage is supplied, second control circuit produces multiple isolation voltage according to high voltage signal, and protection circuit and part PNP transistor suppress according to these isolation voltages the leakage current flowing through protection circuit and described part PNP transistor.
Aforesaid electrostatic discharge protective equipment, wherein said second control circuit comprises: one the 3rd PMOS transistor, and wherein the source electrode of the 3rd PMOS transistor receives this high voltage signal; One second nmos pass transistor, wherein the drain electrode of this second nmos pass transistor is electrically connected the drain electrode of the 3rd PMOS transistor, and the grid of this second nmos pass transistor receives this supply voltage, and the source electrode of this second nmos pass transistor is electrically connected this earth terminal; And multiple 4th PMOS transistor, wherein the source electrode of those the 4th PMOS transistor receives this high voltage signal, the grid of those the 4th PMOS transistor is electrically connected the drain electrode of the 3rd PMOS transistor, the drain electrode of one of them of those the 4th PMOS transistor is electrically connected the grid of the 3rd PMOS transistor, and the drain electrode of those the 4th PMOS transistor is in order to produce those isolation voltages.
Aforesaid electrostatic discharge protective equipment, wherein said second control circuit comprises: one the 5th PMOS transistor, and wherein the source electrode of the 5th PMOS transistor receives this high voltage signal; One the 3rd nmos pass transistor, wherein the drain electrode of the 3rd nmos pass transistor is electrically connected the drain electrode of the 5th PMOS transistor, and the grid of the 3rd nmos pass transistor receives this supply voltage, and the source electrode of the 3rd nmos pass transistor is electrically connected this earth terminal; One the 6th PMOS transistor, wherein the source electrode of the 6th PMOS transistor receives this high voltage signal, the grid of the 6th PMOS transistor is electrically connected the drain electrode of the 5th PMOS transistor, and the drain electrode of the 6th PMOS transistor is electrically connected the grid of the 5th PMOS transistor; And multiple resistance, the first end of those resistance is electrically connected the drain electrode of the 5th PMOS transistor, and the second end of those resistance is in order to produce those isolation voltages.
Aforesaid electrostatic discharge protective equipment, also comprises multiple diode.Wherein, between the two adjacent PNP transistor that described multiple diode interts respectively in a described K PNP transistor.
Aforesaid electrostatic discharge protective equipment, wherein said protection circuit comprises: one the 4th nmos pass transistor, wherein the drain electrode of the 4th nmos pass transistor is electrically connected the base stage of K PNP transistor, and the grid of the 4th nmos pass transistor receives a supply voltage or an isolation voltage; And one the 5th nmos pass transistor, wherein the drain electrode of the 5th nmos pass transistor is electrically connected the source electrode of the 4th nmos pass transistor, and the grid of the 5th nmos pass transistor receives an earthed voltage, and the source electrode of the 5th nmos pass transistor is electrically connected to this earth terminal.
Aforesaid electrostatic discharge protective equipment; wherein said protection circuit comprises one the 6th nmos pass transistor; and the drain electrode of the 6th nmos pass transistor is electrically connected the base stage of K PNP transistor; the grid of the 6th nmos pass transistor receives an earthed voltage, and the source electrode of the 6th nmos pass transistor is electrically connected to this earth terminal.
Aforesaid electrostatic discharge protective equipment, wherein said protection circuit comprises: one the 7th PMOS transistor, wherein the source electrode of the 7th PMOS transistor is electrically connected the base stage of K PNP transistor, and the grid of the 7th PMOS transistor is electrically connected its source electrode or receives an isolation voltage; And one the 8th PMOS transistor, wherein the source electrode of the 8th PMOS transistor is electrically connected the drain electrode of the 7th PMOS transistor, and the grid of the 8th PMOS transistor receives a supply voltage, and the drain electrode of the 8th PMOS transistor is electrically connected to this earth terminal.
Aforesaid electrostatic discharge protective equipment; wherein said protection circuit comprises one the 9th PMOS transistor; and the source electrode of the 9th PMOS transistor and grid are electrically connected the base stage of K PNP transistor, the drain electrode of the 9th PMOS transistor is electrically connected to this earth terminal.
The object of the invention to solve the technical problems also realizes by the following technical solutions.According to a kind of electrostatic discharge protective equipment that the present invention proposes, be electrically connected a weld pad, and comprise K PNP transistor and protection circuit, wherein K is positive integer.A described K PNP transistor provides K individual path of conducting to earth terminal.In addition, the 1st PNP transistor is electrically connected weld pad.I-th PNP transistor is electrically connected (i+1) individual PNP transistor, and provides i-th individual path.K PNP transistor provides K individual path, and wherein i is integer and 1≤i≤(K-1).Protection circuit is electrically connected at K between PNP transistor and earth terminal, and protection circuit provides a discharge path.Wherein, from the electrostatic signal of weld pad by discharge path and described K individual path conducting to earth terminal.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid electrostatic discharge protective equipment; wherein said weld pad is in order to receive a high voltage signal; and this electrostatic discharge protective equipment also comprises: a first control circuit; be electrically connected this weld pad; and receive a supply voltage; wherein; when this supply voltage is supplied; this first control circuit produces an isolation voltage according to this high voltage signal; and the specific PNP transistor in this protection circuit or those PNP transistor, suppress according to this isolation voltage the leakage current flowing through this protection circuit or this specific PNP transistor.
Aforesaid electrostatic discharge protective equipment; wherein said weld pad is in order to receive a high voltage signal; and this electrostatic discharge protective equipment also comprises: a second control circuit; be electrically connected this weld pad; and receive a supply voltage; wherein; when this supply voltage is supplied; this second control circuit produces multiple isolation voltage according to this high voltage signal, and this protection circuit suppresses according to those isolation voltages the leakage current flowing through this protection circuit and described those PNP transistor of part with those PNP transistor of part.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, electrostatic discharge protective equipment of the present invention at least has following advantages and beneficial effect: multiple PNP transistor of serial connection are electrically connected between weld pad and protection circuit by the present invention.By this, the electrostatic signal from weld pad by PNP transistor conducting to earth terminal, and then will reduce the rated current of bearing needed for protection circuit.In addition, the layout area of protection circuit can diminish along with the reduction of rated current, therefore can reduce the impact of process shifts on electrostatic discharge protective equipment.
In sum, the invention relates to a kind of electrostatic discharge protective equipment, be electrically connected a weld pad, and comprise K PNP transistor and protection circuit, wherein K is positive integer.The emitter-base bandgap grading of the 1st PNP transistor is electrically connected weld pad, the base stage of i-th PNP transistor is electrically connected the emitter-base bandgap grading of (i+1) individual PNP transistor, and the collector of a described K PNP transistor is electrically connected to earth terminal, i is integer and 1≤i≤(K-1).Between the base stage that protection circuit is electrically connected at K PNP transistor and earth terminal, and provide a discharge path.Wherein, from the electrostatic signal of weld pad by discharge path and described K PNP transistor conducting to earth terminal.The present invention has significant progress technically, and has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the electrostatic discharge protective equipment according to the first embodiment of the present invention.
Fig. 2 is the structural representation of electrostatic discharge protective equipment according to a second embodiment of the present invention.
Fig. 3 is the structural representation of electrostatic discharge protective equipment according to the third embodiment of the invention.
Fig. 4 is the structural representation of electrostatic discharge protective equipment according to a fourth embodiment of the invention.
Fig. 5 is the structural representation of electrostatic discharge protective equipment according to a fifth embodiment of the invention.
Fig. 6 is the circuit diagram of the control circuit according to one embodiment of the invention.
Fig. 7 is the circuit diagram of the control circuit according to another embodiment of the present invention.
Fig. 8 is the circuit diagram of the control circuit according to another embodiment of the present invention.
Fig. 9 A ~ Fig. 9 C is the circuit diagram of the protection circuit according to one embodiment of the invention respectively.
100,200,300,400,500: electrostatic discharge protective equipment
101: weld pad
110_1 ~ 110_K:PNP transistor
120,910 ~ 930: protection circuit
121,122,620,720,820,921:NMOS transistor
VD1, VD2, VD4, VD6, VD7, VD8, VD9: supply voltage
VG1, VG91: earthed voltage
I_Total: electrostatic induced current
I (1) ~ I (K), I_ptc: branch current
210,310,410,600,700,800: control circuit
VIO2, VIO3, VIO41 ~ VIO44, VIO6, VIO71 ~ VIO74, VIO81 ~ VIO84, VIO9: isolation voltage
VH2, VH3, VH4, VH6, VH7, VH8: high voltage signal
510: diode
610,630,710,731 ~ 734,810,830,911,912,931:PMOS transistor
R81 ~ R84: resistance
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect; below in conjunction with accompanying drawing and preferred embodiment; to its embodiment of electrostatic discharge protective equipment proposed according to the present invention, structure, feature and effect thereof, be described in detail as follows.
Aforementioned and other technology contents, Characteristic for the present invention, can clearly present in the detailed description of following cooperation with reference to graphic preferred embodiment.For convenience of description, below in an example, identical element represents with identical numbering.
[the first embodiment]
Fig. 1 is the schematic diagram of the electrostatic discharge protective equipment according to the first embodiment of the present invention.Refer to shown in Fig. 1, electrostatic discharge protective equipment 100 is electrically connected a weld pad 101, and comprises K PNP transistor 110_1 ~ 110_K and protection circuit 120, and wherein K is positive integer.Further, protection circuit 120 comprises nmos pass transistor 121 and nmos pass transistor 122.At this, described PNP transistor 110_1 ~ 110_K is bipolar junction transistors (the bipolar junctiontransistor of positive-negative-positive, BJT), and described nmos pass transistor 121 and 122 is the mos field effect transistor (Complementary Metal-Oxide-Semiconductor, CMOS) of N-type.
With regard to protection circuit 120, the drain electrode of nmos pass transistor 121 is electrically connected the base stage of PNP transistor 110_K, and the grid of nmos pass transistor 121 receives a supply voltage VD1.In addition, the drain electrode of nmos pass transistor 122 is electrically connected the source electrode of nmos pass transistor 121, and the grid of nmos pass transistor 122 receives an earthed voltage VG1, and the source electrode of nmos pass transistor 122 is electrically connected to earth terminal.With regard to layout structure, the nmos pass transistor 121 and 122 of two serial connections has parasitic horizontal NPN transistor, and therefore protection circuit 120 can provide a discharge path.
In addition, the emitter-base bandgap grading of the 1st PNP transistor 110_1 is electrically connected weld pad 101, and the base stage of the 1st PNP transistor 110_1 is electrically connected the emitter-base bandgap grading of the 2nd PNP transistor 110_2.In addition, the emitter-base bandgap grading that the base stage of the 2nd PNP transistor 110_2 is electrically connected the emitter-base bandgap grading of the 3rd PNP transistor 110_3, the base stage of the 3rd PNP transistor 110_3 is electrically connected the 4th PNP transistor 110_4 ... etc.By that analogy, the base stage of i-th PNP transistor is electrically connected the emitter-base bandgap grading of (i+1) individual PNP transistor, and i is integer and 1≤i≤(K-1).Moreover the collector of K described PNP transistor 110_1 ~ 110_K is electrically connected to earth terminal, to form K individual path.
In practical application; weld pad 101 is electrically connected to an internal circuit (not showing); electrostatic discharge protective equipment 100 is then under the prerequisite not affecting internal circuit normal running, avoids the electrostatic signal from weld pad 101 to cause damage to internal circuit.Therefore, when supply voltage VD1 is supplied, internal circuit is by normal running.In addition, the grid of nmos pass transistor 122 will receive earthed voltage VG1, and then intercept weld pad 101 conducting to earth terminal.Thus, the leakage current that protection circuit 120 is formed can be suppressed, and then avoid internal circuit to be subject to the impact of electrostatic discharge protective equipment 100.
When electrostatic discharge event occurs, the electrostatic signal from weld pad 101 will impel the p in PNP transistor 110_1 ~ 110_K
+-n junction (that is penetrating-base stage junction) is biased in forward bias voltage drop.By this, the electrostatic signal of a part is by by the p in PNP transistor 110_1 ~ 110_K
+-n-p junction structure (that is individual path) branches to earth terminal, and the electrostatic signal of another part then will be passed to protection circuit 120 by PNP transistor 110_1 ~ 110_K step by step.In addition, the discharge path that the NPN transistor by parasitism is formed by the electrostatic signal being sent to protection circuit 120, and be conducted to earth terminal.
For example, if the electrostatic induced current flowing into weld pad 101 is I_Total, and be respectively I (1), I (2), I (3) ..., I (K) by the branch current that the individual path of PNP transistor 110_1 ~ 110_K is formed, then the branch current I_ptc being sent to protection circuit 120 will such as formula shown in (1):
I_ptc=I_Total-I (1)-I (2)-I (3)-...-I (K) formula (1)
If with common-emitter current gain, that is β=(I
c/ I
b), carry out again expression (1), then formula (1) can be rewritten as:
I_Total=(1+ β)
k× I_ptc formula (2)
Wherein, K is the number of serial connection PNP transistor, and IC is the collected current of PNP transistor, and I
bfor the base current of PNP transistor.
In other words, when electrostatic discharge event occurs, from weld pad 101 electrostatic signal by by the discharge path of protection circuit 120 and the individual path conducting of PNP transistor 110_1 ~ 110_K to earth terminal.Thus, due to PNP transistor 110_1 ~ 110_K conducting can be passed through to earth terminal from the electrostatic signal of weld pad 101, therefore the discharge path of protection circuit 120 need not bear excessive electrostatic induced current, and that is, the rated current of bearing needed for protection circuit 120 can be lowered.Relatively, in the design of circuit layout, the layout area of protection circuit 120 can be lowered, and then reduces process shifts to the impact of electrostatic discharge protective equipment 100.
[the second embodiment]
Fig. 2 is the structural representation of electrostatic discharge protective equipment according to a second embodiment of the present invention.Refer to shown in Fig. 2, the present embodiment is roughly the same with the first embodiment, and in Fig. 2, same or analogous element numbers represents same or analogous element, just repeats no more in the present embodiment.
The present embodiment and the main difference of the first embodiment are: electrostatic discharge protective equipment 200 more comprises control circuit 210, and the grid of nmos pass transistor 121 in protection circuit 120 is in order to receive isolation voltage VIO2.In the present embodiment, control circuit 210 is electrically connected weld pad 101.In addition, when supply voltage VD2 is supplied, be connected to the internal circuit (not showing) of weld pad 101 by normal running, and internal circuit can receive a high voltage signal VH2 by weld pad 101.On the other hand, control circuit 210 now will receive supply voltage VD2 and the high voltage signal VH2 from weld pad 101.
In addition, when supply voltage VD2 is supplied, control circuit 210 can produce isolation voltage VIO2 according to high voltage signal VH2, and the isolation voltage VIO2 wherein described in the present embodiment is high voltage level.Therefore, when the nmos pass transistor 121 in protection circuit 120 receives isolation voltage VIO2, the breakdown voltage (breakdown voltage) of the parasitic p-n junction in nmos pass transistor 121 will be enhanced, and then suppresses the leakage current flowing through protection circuit 120.In other words, in the present embodiment, when supply voltage VD2 is supplied, control circuit 210 can produce isolation voltage VIO2, and protection circuit 120 will suppress according to isolation voltage VIO2 the leakage current flowing through protection circuit 120.Wherein, shown in (2), the reduction along with branch current I_ptc reduces by electrostatic induced current I_Total.In addition, when electrostatic discharge event occurs, voltage source VD2 will not be provided to control circuit 210, and control circuit 210 can not produce isolation voltage VIO2.By this, the grid of nmos pass transistor 121 will be in the state of suspension joint, and then improve the protective capacities of protection circuit 120.
In addition, with the first embodiment similarly, when electrostatic discharge event occurs, from weld pad 101 electrostatic signal by by the discharge path of protection circuit 120 and PNP transistor 110_1 ~ 110_K conducting to earth terminal, and then avoid electrostatic signal to cause damage to internal circuit.In addition, because electrostatic signal can pass through PNP transistor 110_1 ~ 110_K conducting to earth terminal, therefore the layout area of protection circuit 120 can be lowered effectively, and then reduces process shifts to the impact of electrostatic discharge protective equipment 200.
[the 3rd embodiment]
Fig. 3 is the structural representation of electrostatic discharge protective equipment according to the third embodiment of the invention.Refer to shown in Fig. 3, the present embodiment is roughly the same with the first embodiment, and in Fig. 3, same or analogous element numbers represents same or analogous element, just repeats no more in the present embodiment.
The present embodiment and the main difference of the first embodiment are: electrostatic discharge protective equipment 300 more comprises control circuit 310, and the base stage of PNP transistor 110_K more receives isolation voltage VIO3.In the present embodiment, control circuit 310 is electrically connected weld pad 101.In addition, when supply voltage VD1 is supplied, be connected to the internal circuit (not showing) of weld pad 101 by normal running, and internal circuit can receive a high voltage signal VH3 by weld pad 101.On the other hand, control circuit 310 now will receive supply voltage VD1 and the high voltage signal VH3 from weld pad 101.
In addition, when supply voltage VD1 is supplied, control circuit 310 will produce isolation voltage VIO3 according to high voltage signal VH3, and the isolation voltage VIO3 wherein described in the present embodiment is high voltage level.Therefore, when the base stage of PNP transistor 110_K is to reception isolation voltage VIO3, it penetrates-under base stage junction can not be biased in forward bias voltage drop, and then suppress the leakage current flowing through PNP transistor 110_K.In other words, in the present embodiment, when supply voltage VD1 is supplied, control circuit 310 can produce isolation voltage VIO3, and then suppresses the leakage current flowing through PNP transistor 110_K.It is worth mentioning that, although the present embodiment is that isolation voltage VIO3 is sent to PNP transistor 110_K, but the technical staff that this area has usual knowledge also can according to design, isolation voltage VIO3 is sent to a certain PNP transistor in PNP transistor 110_1 ~ 110_K, with the generation causing the PNP transistor receiving isolation voltage VIO3 can suppress leakage current.
In addition, with the first embodiment similarly, when electrostatic discharge event occurs, from weld pad 101 electrostatic signal by by the discharge path of protection circuit 120 and PNP transistor 110_1 ~ 110_K conducting to earth terminal, and then avoid electrostatic signal to cause damage to internal circuit.In addition, because electrostatic signal can pass through PNP transistor 110_1 ~ 110_K conducting to earth terminal, therefore the layout area of protection circuit 120 can be lowered effectively, and then reduces process shifts to the impact of electrostatic discharge protective equipment 300.
[the 4th embodiment]
Fig. 4 is the structural representation of electrostatic discharge protective equipment according to a fourth embodiment of the invention.Refer to shown in Fig. 4, the present embodiment is roughly the same with the first embodiment, and in Fig. 4, same or analogous element numbers represents same or analogous element, just repeats no more in the present embodiment.
The present embodiment and the main difference of the first embodiment are: electrostatic discharge protective equipment 400 more comprises control circuit 410; and the base stage of PNP transistor 110_1 ~ 110_K more receives isolation voltage VIO41 ~ VIO44, and the grid of nmos pass transistor 121 in protection circuit 120 is in order to receive isolation voltage VIO45.In the present embodiment, control circuit 410 is electrically connected weld pad 101.In addition, when supply voltage VD4 is supplied, be connected to the internal circuit (not showing) of weld pad 101 by normal running, and internal circuit can receive a high voltage signal VH4 by weld pad 101.On the other hand, control circuit 410 now will receive supply voltage VD4 and the high voltage signal VH4 from weld pad 101.
In addition, when supply voltage VD4 is supplied, control circuit 410 will produce isolation voltage VIO41 ~ VIO45 according to high voltage signal VH4, and the isolation voltage VIO41 ~ VIO45 wherein described in the present embodiment is high voltage level.Therefore, when the nmos pass transistor 121 in protection circuit 120 receives isolation voltage VIO45, the breakdown voltage of the parasitic p-n junction in nmos pass transistor 121 will be enhanced, and then suppresses the leakage current flowing through protection circuit 120.In addition, when the base stage of PNP transistor 110_1 ~ 110_K receives isolation voltage VIO41 ~ VIO44, it penetrates-under base stage junction can not be biased in forward bias voltage drop, and then suppress the leakage current flowing through PNP transistor 110_1 ~ 110_K.
In other words, in the present embodiment, when supply voltage VD4 is supplied, control circuit 410 can produce isolation voltage VIO41 ~ VIO45, and then suppresses the leakage current flowing through protection circuit 120 and PNP transistor 110_1 ~ 110_K.It is worth mentioning that, although the present embodiment is that isolation voltage VIO41 ~ VIO44 is sent to each PNP transistor, but isolation voltage VIO41 ~ VIO44 also according to design, can be sent to the PNP transistor of part by the technical staff that this area has usual knowledge.
In addition, with the first embodiment similarly, when electrostatic discharge event occurs, from weld pad 101 electrostatic signal by by the discharge path of protection circuit 120 and PNP transistor 110_1 ~ 110_K conducting to earth terminal, and then avoid electrostatic signal to cause damage to internal circuit.In addition, because electrostatic signal can pass through PNP transistor 110_1 ~ 110_K conducting to earth terminal, therefore the layout area of protection circuit 120 can be lowered effectively, and then reduces process shifts to the impact of electrostatic discharge protective equipment 400.
[the 5th embodiment]
Fig. 5 is the structural representation of electrostatic discharge protective equipment according to a fifth embodiment of the invention.Refer to shown in Fig. 5, the present embodiment is roughly the same with the first embodiment, and in Fig. 5, same or analogous element numbers represents same or analogous element, just repeats no more in the present embodiment.
The present embodiment and the main difference of the first embodiment are: electrostatic discharge protective equipment 500 more comprises diode 510.In the present embodiment, the anode of diode 510 is electrically connected to the base stage of PNP transistor 110_1, and the negative electrode of diode 510 is electrically connected to the emitter-base bandgap grading of PNP transistor 110_2.By this, the voltage drop that diode 510 is formed can avoid protection circuit 120 directly to receive too high voltage level.Relatively, in protection circuit 120, the breakdown voltage of parasitic NPN transistor can do corresponding adjustment.It is worth mentioning that, although the present embodiment is an interspersed diode in the PNP transistor 110_1 ~ 110_K of serial connection only, but the technical staff that this area has usual knowledge also can according to design, interspersed multiple diode in the PNP transistor 110_1 ~ 110_K of serial connection.In addition, the technical staff that this area has usual knowledge also can refer to Fig. 5 embodiment, interts one to multiple diode in the PNP transistor 110_1 cited by Fig. 2 to Fig. 4 embodiment ~ 110_K.
In addition, with the first embodiment similarly, when electrostatic discharge event occurs, from weld pad 101 electrostatic signal by by the discharge path of protection circuit 120 and PNP transistor 110_1 ~ 110_K conducting to earth terminal, and then avoid electrostatic signal to cause damage to internal circuit.In addition, because electrostatic signal can pass through PNP transistor 110_1 ~ 110_K conducting to earth terminal, therefore the layout area of protection circuit 120 can be lowered effectively, and then reduces process shifts to the impact of electrostatic discharge protective equipment 500.
[the 6th embodiment]
Fig. 6 is the circuit diagram of the control circuit according to one embodiment of the invention.Refer to shown in Fig. 6, control circuit 600 receives supply voltage VD6 and high voltage signal VH6, and in order to produce isolation voltage VIO6.Therefore, in practical application, the control circuit 210 and 310 cited by Fig. 2 and Fig. 3 embodiment, can utilize the control circuit 600 of Fig. 6 to be realized respectively.
At this, control circuit 600 comprises PMOS transistor 610, nmos pass transistor 620 and PMOS transistor 630.Wherein, the source electrode of PMOS transistor 610 receives high voltage signal VH6.The drain electrode of nmos pass transistor 620 is electrically connected the drain electrode of PMOS transistor 610, and the grid of nmos pass transistor 620 receives supply voltage VD6, and the source electrode of nmos pass transistor 620 is electrically connected to earth terminal.In addition, the source electrode of PMOS transistor 630 receives high voltage signal VH6, the grid of PMOS transistor 630 is electrically connected the drain electrode of PMOS transistor 610, and the drain electrode of PMOS transistor 630 is electrically connected the grid of PMOS transistor 610, and the drain electrode of PMOS transistor 630 is in order to produce isolation voltage VIO6.
Operationally, when supply voltage VD6 and high voltage signal VH6 is supplied, nmos pass transistor 620 by conducting, and then causes the grid of PMOS transistor 630 to receive earthed voltage.By this, PMOS transistor 630 by the conducting according to received earthed voltage, and then produces isolation voltage VIO6 by its drain electrode.In addition, isolation voltage VIO6 will feed back to the grid of PMOS transistor 610, and then PMOS transistor 610 is latched in the state of not conducting.
On the other hand, when electrostatic discharge event occurs, supply voltage VD6 is the state being in floating (floating), and its standard is close to earthed voltage, so time nmos pass transistor 620 cannot conducting.In addition, the grid of PMOS transistor 630 can be coupled to high voltage signal VH6 by its grid to the parasitic capacitance of source electrode, so time PMOS transistor 630 also cannot conducting.Moreover the grid of PMOS transistor 610 is in floating state, and its grid voltage is less than high voltage signal VH6, so time PMOS transistor 610 by conducting, and then breech lock lives control circuit 600, and guarantees that control circuit 600 cannot export any signal.
[the 7th embodiment]
Fig. 7 is the circuit diagram of the control circuit according to another embodiment of the present invention.Refer to shown in Fig. 7, control circuit 700 receives supply voltage VD7 and high voltage signal VH7, and in order to produce multiple isolation voltage VIO71 ~ VIO74.Therefore, in practical application, the control circuit 410 cited by Fig. 4 embodiment can utilize the control circuit 700 of Fig. 7 to be realized.
At this, control circuit 700 comprises PMOS transistor 710, nmos pass transistor 720 and PMOS transistor 731 ~ 734.Wherein, the source electrode of PMOS transistor 710 receives high voltage signal VH7.The drain electrode of nmos pass transistor 720 is electrically connected the drain electrode of PMOS transistor 710, and the grid of nmos pass transistor 720 receives supply voltage VD7, and the source electrode of nmos pass transistor 720 is electrically connected to earth terminal.The source electrode of PMOS transistor 731 ~ 734 receives high voltage signal VH7, and the grid of PMOS transistor 731 ~ 734 is electrically connected the drain electrode of PMOS transistor 710, and the drain electrode of PMOS transistor 731 ~ 734 is in order to produce isolation voltage VIO71 ~ VIO74.In addition, the drain electrode of PMOS transistor 731 is electrically connected the grid of PMOS transistor 710.
Operationally, when supply voltage VD7 and high voltage signal VH7 is supplied, nmos pass transistor 720 by conducting, and then causes the grid of PMOS transistor 731 ~ 734 to receive earthed voltage, and then causes the drain electrode of PMOS transistor 731 ~ 734 to produce isolation voltage VIO71 ~ VIO74.In addition, isolation voltage VIO71 will feed back to the grid of PMOS transistor 710, PMOS transistor 710 to be latched in the state of not conducting.
On the other hand, when electrostatic discharge event occurs, the position brigadier of supply voltage VD7 close to earthed voltage, so time nmos pass transistor 720 cannot conducting.In addition, the grid of PMOS transistor 731 ~ 734 can be coupled to high voltage signal VH7 respectively by its grid to the parasitic capacitance of source electrode, so time PMOS transistor 731 ~ 734 also cannot conducting.Moreover the grid of PMOS transistor 710 is in floating state, and its grid voltage is less than high voltage signal VH7, so time PMOS transistor 710 by conducting, and then breech lock lives control circuit 700, and guarantees that control circuit 700 cannot export any signal.
[the 8th embodiment]
Fig. 8 is the circuit diagram of the control circuit according to another embodiment of the present invention.Refer to shown in Fig. 8, control circuit 800 receives supply voltage VD8 and high voltage signal VH8, and in order to produce multiple isolation voltage VIO81 ~ VIO84.Therefore, in practical application, the control circuit 410 cited by Fig. 4 embodiment also can utilize the control circuit 800 of Fig. 8 to be realized.
At this, control circuit 800 comprises PMOS transistor 810, nmos pass transistor 820, PMOS transistor 830 and multiple resistance R81 ~ R84.Wherein, the source electrode of PMOS transistor 810 receives high voltage signal VH8.The drain electrode of nmos pass transistor 820 is electrically connected the drain electrode of PMOS transistor 810, and the grid of nmos pass transistor 820 receives supply voltage VD8, and the source electrode of nmos pass transistor 820 is electrically connected to earth terminal.In addition, the source electrode of PMOS transistor 830 receives high voltage signal VH8, the grid of PMOS transistor 830 is electrically connected the drain electrode of PMOS transistor 810, and the drain electrode of PMOS transistor 830 is electrically connected the grid of PMOS transistor 810 and the first end of resistance R81 ~ R84.Moreover second end of resistance R81 ~ R84 is in order to produce isolation voltage VIO81 ~ VIO84.
In the present embodiment, the operation mechanism of transistor 810,820 and 830 is identical with the operation mechanism of the transistor 610,620 in Fig. 6 and transistor 630.Therefore, when supply voltage VD8 and high voltage signal VH8 is supplied, nmos pass transistor 820 and PMOS transistor 830 by conducting, and then impel the first end of resistance R81 ~ R84 to receive high voltage signal VH8 respectively.By this, high voltage signal VH8 will distinguish pressure drop on resistance R81 ~ R84, and then impel resistance R81 ~ R84 to produce isolation voltage VIO81 ~ VIO84.In addition, PMOS transistor 810 will be latched in the state of not conducting.On the other hand, when electrostatic discharge event occurs, nmos pass transistor 820 and PMOS transistor 830 cannot conductings, and then impel the first end of resistance R81 ~ R84 to be in floating state.Moreover PMOS transistor 810 is by conducting, and then breech lock lives control circuit 800, and guarantee that control circuit 800 cannot export any signal.
[the 9th embodiment]
Fig. 9 A ~ Fig. 9 C is the circuit diagram of the protection circuit according to one embodiment of the invention respectively.As shown in Figure 9 A, protection circuit 910 is made up of the PMOS transistor 911 and 912 of two serial connections.Wherein, the source electrode of PMOS transistor 911 is electrically connected the base stage of K PNP transistor 110_K.The source electrode of PMOS transistor 912 is electrically connected the drain electrode of PMOS transistor 911, and the grid of PMOS transistor 912 receives a supply voltage VD9, and the drain electrode of PMOS transistor 912 is electrically connected to earth terminal.
In practical application, PMOS transistor 911 is in order to intercept weld pad conducting to earth terminal, and the parasitic lateral PNP transistor in the PMOS transistor 911 and 912 of two serial connections can provide a discharge path.In practical application, the grid of PMOS transistor 911 can be electrically connected to its source electrode or receive isolation voltage VIO9.When the grid of PMOS transistor 911 is electrically connected to its source electrode, the protection circuit 120 cited by Fig. 1, Fig. 3 and Fig. 5 embodiment can utilize the protection circuit 910 of Fig. 9 to be realized.In addition, when the grid of PMOS transistor 911 is when receiving adjustable isolation voltage VIO9, the protection circuit 120 cited by Fig. 2 and Fig. 4 embodiment can utilize the protection circuit 910 of Fig. 9 to be realized.
It is worth mentioning that, the protection circuit 120 cited by Fig. 1 to Fig. 5 embodiment utilizes the nmos pass transistor of two serial connections to realize, and the protection circuit 910 cited by Fig. 9 embodiment is then utilize the PMOS transistor of two serial connections to realize.Wherein, under fixing layout area, the rated transformation ratio PMOS transistor that nmos pass transistor can bear is greater.Therefore, in practical application, protection circuit 910 must expend larger layout area, and its rated current that can bear could be identical with protection circuit 120.In other words, this area there is the technical staff of usual knowledge can according to the rated current needed for protection circuit to adjust the thin portion framework of protection circuit.In addition, although the various embodiments described above are all be connected in series by two MOS transistor that kenel is identical, the technical staff that this area has usual knowledge also can adopt two MOS transistor that kenel is not identical to realize protection circuit.
In addition, protection circuit also can utilize single MOS transistor to realize.For example, as shown in Figure 9 B, protection circuit 920 comprises a nmos pass transistor 921.Wherein, the drain electrode of nmos pass transistor 921 is electrically connected the base stage of K PNP transistor 110_K, and the grid of nmos pass transistor 921 receives an earthed voltage VG91, and the source electrode of nmos pass transistor 921 is electrically connected to earth terminal.In addition, as shown in Figure 9 C, protection circuit 930 comprises a PMOS transistor 931.Wherein, the source electrode of PMOS transistor 931 and grid are electrically connected the base stage of K PNP transistor 110_K, and the drain electrode of PMOS transistor 931 is electrically connected to earth terminal.It is worth mentioning that, under the state that the protection circuit realized by single MOS transistor is mainly biased in not conducting, therefore Fig. 9 B and the protection circuit cited by Fig. 9 C 920 can be applied in Fig. 1, Fig. 3 and Fig. 5 embodiment respectively with protection circuit 930.
In sum, multiple PNP transistor of serial connection are electrically connected between weld pad and protection circuit by the present invention.Thus, the electrostatic signal from weld pad by PNP transistor conducting to earth terminal, and then will reduce the rated current of bearing needed for protection circuit.In addition, the layout area of protection circuit will diminish along with the reduction of rated current, therefore can reduce the impact of process shifts on electrostatic discharge protective equipment.In addition, electrostatic discharge protective equipment of the present invention more can utilize control circuit to produce isolation voltage, with the leakage current suppressing protection circuit or PNP transistor to be formed.
The above, it is only preferred embodiment of the present invention, not any pro forma restriction is done to the present invention, although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, make a little change when the technology contents of above-mentioned announcement can be utilized or be modified to the Equivalent embodiments of equivalent variations, in every case be do not depart from technical solution of the present invention content, according to any simple modification that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (7)
1. an electrostatic discharge protective equipment, is electrically connected a weld pad, it is characterized in that this electrostatic discharge protective equipment comprises:
K PNP transistor, wherein the emitter-base bandgap grading of the 1st PNP transistor is electrically connected this weld pad, the base stage of i-th PNP transistor is electrically connected the emitter-base bandgap grading of (i+1) individual PNP transistor, and the collector of those PNP transistor is electrically connected an earth terminal, K is positive integer, and i is integer and 1≤i≤(K-1);
One protection circuit, is electrically connected between the base stage of K PNP transistor and this earth terminal, and this protection circuit provides a discharge path, wherein from an electrostatic signal of this weld pad by this discharge path and those PNP transistor conductings to this earth terminal; And
One control circuit, be electrically connected this weld pad, and receive a supply voltage, wherein this weld pad is in order to receive a high voltage signal, when this supply voltage is supplied, this control circuit produces multiple isolation voltage according to this high voltage signal, and this protection circuit suppresses according to those isolation voltages the leakage current flowing through this protection circuit and described those PNP transistor of part with those PNP transistor of part;
This control circuit comprises:
One the 3rd PMOS transistor, wherein the source electrode of the 3rd PMOS transistor receives this high voltage signal;
One second nmos pass transistor, wherein the drain electrode of this second nmos pass transistor is electrically connected the drain electrode of the 3rd PMOS transistor, and the grid of this second nmos pass transistor receives this supply voltage, and the source electrode of this second nmos pass transistor is electrically connected this earth terminal; And
Multiple 4th PMOS transistor, wherein the source electrode of those the 4th PMOS transistor receives this high voltage signal, the grid of those the 4th PMOS transistor is electrically connected the drain electrode of the 3rd PMOS transistor, the drain electrode of one of them of those the 4th PMOS transistor is electrically connected the grid of the 3rd PMOS transistor, and the drain electrode of those the 4th PMOS transistor is in order to produce those isolation voltages; Or one the 6th PMOS transistor and multiple resistance, wherein the source electrode of the 6th PMOS transistor receives this high voltage signal, the grid of the 6th PMOS transistor is electrically connected the drain electrode of the 3rd PMOS transistor, and the drain electrode of the 6th PMOS transistor is electrically connected the grid of the 3rd PMOS transistor; The first end of those resistance is electrically connected the drain electrode of the 3rd PMOS transistor, and the second end of those resistance is in order to produce those isolation voltages.
2. electrostatic discharge protective equipment according to claim 1, is characterized in that it also comprises:
Multiple diode, between the two adjacent PNP transistor interted respectively in those PNP transistor.
3. electrostatic discharge protective equipment according to claim 1, is characterized in that wherein said protection circuit comprises:
One the 4th nmos pass transistor, wherein the drain electrode of the 4th nmos pass transistor is electrically connected the base stage of K PNP transistor, and the grid of the 4th nmos pass transistor receives a supply voltage or an isolation voltage; And
One the 5th nmos pass transistor, wherein the drain electrode of the 5th nmos pass transistor is electrically connected the source electrode of the 4th nmos pass transistor, and the grid of the 5th nmos pass transistor receives an earthed voltage, and the source electrode of the 5th nmos pass transistor is electrically connected to this earth terminal.
4. electrostatic discharge protective equipment according to claim 1; it is characterized in that wherein said protection circuit comprises one the 6th nmos pass transistor; and the drain electrode of the 6th nmos pass transistor is electrically connected the base stage of K PNP transistor; the grid of the 6th nmos pass transistor receives an earthed voltage, and the source electrode of the 6th nmos pass transistor is electrically connected to this earth terminal.
5. electrostatic discharge protective equipment according to claim 1, is characterized in that wherein said protection circuit comprises:
One the 7th PMOS transistor, wherein the source electrode of the 7th PMOS transistor is electrically connected the base stage of K PNP transistor, and the grid of the 7th PMOS transistor is electrically connected its source electrode or receives an isolation voltage; And
One the 8th PMOS transistor, wherein the source electrode of the 8th PMOS transistor is electrically connected the drain electrode of the 7th PMOS transistor, and the grid of the 8th PMOS transistor receives a supply voltage, and the drain electrode of the 8th PMOS transistor is electrically connected to this earth terminal.
6. electrostatic discharge protective equipment according to claim 1; it is characterized in that wherein said protection circuit comprises one the 9th PMOS transistor; and the source electrode of the 9th PMOS transistor and grid are electrically connected the base stage of K PNP transistor, the drain electrode of the 9th PMOS transistor is electrically connected to this earth terminal.
7. an electrostatic discharge protective equipment, is electrically connected a weld pad, it is characterized in that this electrostatic discharge protective equipment comprises:
K PNP transistor, K individual path of conducting to earth terminal is provided, wherein the 1st PNP transistor is electrically connected this weld pad, i-th PNP transistor is electrically connected (i+1) individual PNP transistor and provides i-th individual path, and K PNP transistor provides K individual path, K is positive integer, and i is integer and 1≤i≤(K-1);
One protection circuit, is electrically connected between K PNP transistor and this earth terminal, and this protection circuit provides a discharge path, wherein from an electrostatic signal of this weld pad by this discharge path and those individual path conductings to this earth terminal; And
One control circuit, be electrically connected this weld pad, and receive a supply voltage, wherein this weld pad is in order to receive a high voltage signal, when this supply voltage is supplied, this control circuit produces multiple isolation voltage according to this high voltage signal, and this protection circuit suppresses according to those isolation voltages the leakage current flowing through this protection circuit and described those PNP transistor of part with those PNP transistor of part;
This control circuit comprises:
One the 3rd PMOS transistor, wherein the source electrode of the 3rd PMOS transistor receives this high voltage signal;
One second nmos pass transistor, wherein the drain electrode of this second nmos pass transistor is electrically connected the drain electrode of the 3rd PMOS transistor, and the grid of this second nmos pass transistor receives this supply voltage, and the source electrode of this second nmos pass transistor is electrically connected this earth terminal; And
Multiple 4th PMOS transistor, wherein the source electrode of those the 4th PMOS transistor receives this high voltage signal, the grid of those the 4th PMOS transistor is electrically connected the drain electrode of the 3rd PMOS transistor, the drain electrode of one of them of those the 4th PMOS transistor is electrically connected the grid of the 3rd PMOS transistor, and the drain electrode of those the 4th PMOS transistor is in order to produce those isolation voltages; Or one the 6th PMOS transistor and multiple resistance, wherein the source electrode of the 6th PMOS transistor receives this high voltage signal, the grid of the 6th PMOS transistor is electrically connected the drain electrode of the 3rd PMOS transistor, and the drain electrode of the 6th PMOS transistor is electrically connected the grid of the 3rd PMOS transistor; The first end of those resistance is electrically connected the drain electrode of the 3rd PMOS transistor, and the second end of those resistance is in order to produce those isolation voltages.
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| CN201110121777.XA CN102779816B (en) | 2011-05-09 | 2011-05-09 | Electrostatic discharge protective equipment |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877927A (en) * | 1996-10-01 | 1999-03-02 | Intel Corporation | Method and apparatus for providing electrostatic discharge protection for high voltage inputs |
| CN1881582A (en) * | 2005-06-14 | 2006-12-20 | 台湾积体电路制造股份有限公司 | Esd protection circuit and semiconductor structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6353520B1 (en) * | 1999-06-03 | 2002-03-05 | Texas Instruments Incorporated | Shared 5 volt tolerant ESD protection circuit for low voltage CMOS process |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877927A (en) * | 1996-10-01 | 1999-03-02 | Intel Corporation | Method and apparatus for providing electrostatic discharge protection for high voltage inputs |
| CN1881582A (en) * | 2005-06-14 | 2006-12-20 | 台湾积体电路制造股份有限公司 | Esd protection circuit and semiconductor structure |
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