CN102779816A - Electrostatic discharge protecting device - Google Patents
Electrostatic discharge protecting device Download PDFInfo
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- CN102779816A CN102779816A CN201110121777XA CN201110121777A CN102779816A CN 102779816 A CN102779816 A CN 102779816A CN 201110121777X A CN201110121777X A CN 201110121777XA CN 201110121777 A CN201110121777 A CN 201110121777A CN 102779816 A CN102779816 A CN 102779816A
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Abstract
The invention relates to an electrostatic discharge protecting device, which is electrically connected with a welding pad and comprises K PNP (plug-and-play) transistors and a protecting circuit, wherein K is a positive integer, an emitting electrode of the first PNP transistor is electrically connected with the welding pad, a base electrode of the ith PNP transistor is electrically connected with the emitting electrode of the (i+1)th PNP transistor, in addition, a connecting electrode of the Kth PNP transistor is electrically connected with the grounding end, and i is an integer, and is greater than or equal to 1 but is smaller than or equal to (K-1). The protecting circuit is electrically connected between the base electrode of the Kth PNP transistor and the grounding end, and in addition, a discharge path is provided, wherein electrostatic signals of the welding pad are conducted with the Kth PNP transistor to the grounding end through the discharge path. Therefore, the electrostatic discharge protecting device has the advantages that the electrostatic signals from the welding pad can be conducted to the grounding end through the PNP transistor, the rated current born by the protecting circuit is reduced, the layout area of the protecting area is further reduced, and the influence of the process migration on the electrostatic discharge protecting device is reduced.
Description
Technical field
The present invention relates to a kind of electrostatic discharge protective equipment, particularly relate to a kind of transistorized electrostatic discharge protective equipment of PNP with serial connection.
Background technology
(electrostatic discharge ESD) is phenomenon from the electrostatic displacement on non-conductive surface to static discharge, the infringement that it can cause semiconductor and other circuit in the integrated circuit to form.For example; The human body of on carpet, walking, at the machine of encapsulated integrated circuit or the instrument of testing integrated circuits ... wait electrified body; Can be when touching chip to chip discharge, and the instantaneous power of this static discharge might cause integrated circuit in the chip to damage or lost efficacy.
In order to prevent that integrated circuit from damaging because of the static discharge phenomenon, in integrated circuit, all can add the design of electrostatic discharge protective equipment.Generally speaking; Electrostatic discharge protective equipment has many designs; Wherein a kind of common mode is exactly to utilize the two-stage N transistor npn npn of serial connection, reaches the effect of electrostatic discharge (ESD) protection, and wherein the gate terminal of the two-stage N transistor npn npn of serial connection all is biased in fixing voltage.Yet the esd protection ability that this kind framework is provided tends to receive the influence of process shifts, and then reduces the reliability of esd protection device.
This shows that above-mentioned existing electrostatic discharge protective equipment obviously still has inconvenience and defective, and demands urgently further improving in structure and use.In order to solve the problem of above-mentioned existence; Relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly; But do not see always that for a long time suitable design is developed completion, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of electrostatic discharge protective equipment of new structure, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Summary of the invention
The objective of the invention is to; Overcome the defective that existing electrostatic discharge protective equipment exists; And a kind of electrostatic discharge protective equipment of new structure is provided; Technical problem to be solved be make its PNP transistor that utilizes serial connection with the electrostatic signal conducting to earth terminal, to reduce the required rated current of bearing of protection circuit.By this, the layout area of protection circuit can be lowered, and then reduces the influence of process shifts to electrostatic discharge protective equipment, is very suitable for practicality.
Another object of the present invention is to; Overcome the defective that existing electrostatic discharge protective equipment exists; And a kind of electrostatic discharge protective equipment of new structure is provided; Technical problem to be solved is to make it utilize the PNP transistor of serial connection that a plurality of individual paths are provided, with the electrostatic signal conducting to earth terminal.By this, the required rated current of bearing of protection circuit can be lowered, and then reduces the influence of process shifts to electrostatic discharge protective equipment, thereby is suitable for practicality more.
The object of the invention and solve its technical problem and adopt following technical scheme to realize.A kind of electrostatic discharge protective equipment according to the present invention proposes electrically connects a weld pad, and comprises K PNP transistor AND gate protection circuit, and wherein K is a positive integer.The transistorized emitter-base bandgap grading of the 1st PNP electrically connects weld pad, and i transistorized emitter-base bandgap grading of transistorized base stage electric connection (i+1) the individual PNP of PNP, and the transistorized collection utmost point of a said K PNP is electrically connected to earth terminal, i are integer and 1≤i≤(K-1).Protection circuit is electrically connected between K transistorized base stage of PNP and the earth terminal, and a discharge path is provided.Wherein, from the electrostatic signal of weld pad through discharge path and said K PNP transistor turns to earth terminal.
The object of the invention and solve its technical problem and also can adopt following technical measures further to realize.
Aforesaid electrostatic discharge protective equipment, wherein said weld pad is in order to the reception high voltage signal, and electrostatic discharge protective equipment also comprises first control circuit.Wherein, first control circuit electrically connects weld pad, and receives supply voltage.In addition; When supply voltage is supplied; First control circuit produces isolation voltage according to high voltage signal, and the specific PNP transistor in protection circuit or said K the PNP transistor, suppresses to flow through protection circuit or the transistorized leakage current of specific PNP according to isolation voltage.
Aforesaid electrostatic discharge protective equipment, wherein said first control circuit comprises: one the one PMOS transistor, wherein the transistorized source electrode of a PMOS receives this high voltage signal; One first nmos pass transistor, wherein the drain electrode of this first nmos pass transistor electrically connects a PMOS transistor drain, and the grid of this first nmos pass transistor receives this supply voltage, and the source electrode of this first nmos pass transistor electrically connects this earth terminal; And one the 2nd PMOS transistor; Wherein the transistorized source electrode of the 2nd PMOS receives this high voltage signal; The transistorized grid of the 2nd PMOS electrically connects a PMOS transistor drain; The 2nd PMOS transistor drain electrically connects the transistorized grid of a PMOS, and the 2nd PMOS transistor drain is in order to produce this isolation voltage.
Aforesaid electrostatic discharge protective equipment, wherein said weld pad is in order to the reception high voltage signal, and electrostatic discharge protective equipment also comprises second control circuit.Wherein, second control circuit electrically connects weld pad, and receives supply voltage.In addition, when supply voltage was supplied, second control circuit produced a plurality of isolation voltages according to high voltage signal, and protection circuit and part PNP transistor suppress to flow through protection circuit and the transistorized leakage current of said part PNP according to these isolation voltages.
Aforesaid electrostatic discharge protective equipment, wherein said second control circuit comprises: one the 3rd PMOS transistor, wherein the transistorized source electrode of the 3rd PMOS receives this high voltage signal; One second nmos pass transistor, wherein the drain electrode of this second nmos pass transistor electrically connects the 3rd PMOS transistor drain, and the grid of this second nmos pass transistor receives this supply voltage, and the source electrode of this second nmos pass transistor electrically connects this earth terminal; And a plurality of the 4th PMOS transistors; Wherein the transistorized source electrode of those the 4th PMOS receives this high voltage signal; The transistorized grid of those the 4th PMOS electrically connects the 3rd PMOS transistor drain; Transistorized one of them the drain electrode of those the 4th PMOS electrically connects the transistorized grid of the 3rd PMOS, and those the 4th PMOS transistor drain are in order to produce those isolation voltages.
Aforesaid electrostatic discharge protective equipment, wherein said second control circuit comprises: one the 5th PMOS transistor, wherein the transistorized source electrode of the 5th PMOS receives this high voltage signal; One the 3rd nmos pass transistor, wherein the drain electrode of the 3rd nmos pass transistor electrically connects the 5th PMOS transistor drain, and the grid of the 3rd nmos pass transistor receives this supply voltage, and the source electrode of the 3rd nmos pass transistor electrically connects this earth terminal; One the 6th PMOS transistor; Wherein the transistorized source electrode of the 6th PMOS receives this high voltage signal; The transistorized grid of the 6th PMOS electrically connects the 5th PMOS transistor drain, and the 6th PMOS transistor drain electrically connects the transistorized grid of the 5th PMOS; And a plurality of resistance, first end of those resistance electrically connects the 5th PMOS transistor drain, and second end of those resistance is in order to produce those isolation voltages.
Aforesaid electrostatic discharge protective equipment also comprises a plurality of diodes.Wherein, said a plurality of diode interts respectively between the two adjacent PNP transistors in said K PNP transistor.
Aforesaid electrostatic discharge protective equipment; Wherein said protection circuit comprises: one the 4th nmos pass transistor; Wherein the drain electrode of the 4th nmos pass transistor electrically connects K the transistorized base stage of PNP, and the grid of the 4th nmos pass transistor receives a supply voltage or an isolation voltage; And one the 5th nmos pass transistor, wherein the drain electrode of the 5th nmos pass transistor electrically connects the source electrode of the 4th nmos pass transistor, and the grid of the 5th nmos pass transistor receives an earthed voltage, and the source electrode of the 5th nmos pass transistor is electrically connected to this earth terminal.
Aforesaid electrostatic discharge protective equipment; Wherein said protection circuit comprises one the 6th nmos pass transistor; And the drain electrode of the 6th nmos pass transistor electrically connects K the transistorized base stage of PNP; The grid of the 6th nmos pass transistor receives an earthed voltage, and the source electrode of the 6th nmos pass transistor is electrically connected to this earth terminal.
Aforesaid electrostatic discharge protective equipment; Wherein said protection circuit comprises: one the 7th PMOS transistor; Wherein the transistorized source electrode of the 7th PMOS electrically connects K the transistorized base stage of PNP, and the transistorized grid of the 7th PMOS electrically connects its source electrode or receives an isolation voltage; And one the 8th PMOS transistor, wherein the transistorized source electrode of the 8th PMOS electrically connects the 7th PMOS transistor drain, and the transistorized grid of the 8th PMOS receives a supply voltage, and the 8th PMOS transistor drain is electrically connected to this earth terminal.
Aforesaid electrostatic discharge protective equipment; Wherein said protection circuit comprises one the 9th PMOS transistor; And transistorized source electrode of the 9th PMOS and grid electrically connect K the transistorized base stage of PNP, and the 9th PMOS transistor drain is electrically connected to this earth terminal.
The object of the invention and solve its technical problem and also adopt following technical scheme to realize.A kind of electrostatic discharge protective equipment according to the present invention proposes electrically connects a weld pad, and comprises K PNP transistor AND gate protection circuit, and wherein K is a positive integer.Said K PNP transistor provides K individual path of conducting to an earth terminal.In addition, the 1st PNP transistor electrically connects weld pad.I PNP transistor electrically connects (i+1) individual PNP transistor, and i individual path is provided.K PNP transistor provides K individual path, and wherein i is integer and 1≤i≤(K-1).Protection circuit is electrically connected between K the PNP transistor AND gate earth terminal, and protection circuit provides a discharge path.Wherein, from the electrostatic signal of weld pad through discharge path and said K individual path conducting to earth terminal.
The object of the invention and solve its technical problem and also can adopt following technical measures further to realize.
Aforesaid electrostatic discharge protective equipment; Wherein said weld pad is in order to receiving a high voltage signal, and this electrostatic discharge protective equipment also comprises: a first control circuit electrically connects this weld pad; And receive a supply voltage; Wherein, when this supply voltage was supplied, this first control circuit produced an isolation voltage according to this high voltage signal; And the specific PNP transistor in this protection circuit or those PNP transistors suppresses to flow through this protection circuit or the transistorized leakage current of this specific PNP according to this isolation voltage.
Aforesaid electrostatic discharge protective equipment; Wherein said weld pad is in order to receive a high voltage signal; And this electrostatic discharge protective equipment also comprises: a second control circuit electrically connects this weld pad, and receives a supply voltage; Wherein, When this supply voltage was supplied, this second control circuit produced a plurality of isolation voltages according to this high voltage signal, and this protection circuit suppresses to flow through this protection circuit and the transistorized leakage current of those PNP of said part with those PNP transistors of part according to those isolation voltages.
The present invention compared with prior art has tangible advantage and beneficial effect.By technique scheme, electrostatic discharge protective equipment of the present invention has advantage and beneficial effect at least: the present invention is electrically connected at a plurality of PNP transistors that are connected in series between weld pad and the protection circuit.By this, can pass through the PNP transistor turns to earth terminal from the electrostatic signal of weld pad, and then reduce the required rated current of bearing of protection circuit.In addition, the layout area of protection circuit can diminish along with the reduction of rated current, therefore can reduce the influence of process shifts to electrostatic discharge protective equipment.
In sum, the invention relates to a kind of electrostatic discharge protective equipment, electrically connect a weld pad, and comprise K PNP transistor AND gate protection circuit, wherein K is a positive integer.The transistorized emitter-base bandgap grading of the 1st PNP electrically connects weld pad, and i transistorized emitter-base bandgap grading of transistorized base stage electric connection (i+1) the individual PNP of PNP, and the transistorized collection utmost point of a said K PNP is electrically connected to earth terminal, i are integer and 1≤i≤(K-1).Protection circuit is electrically connected between K transistorized base stage of PNP and the earth terminal, and a discharge path is provided.Wherein, from the electrostatic signal of weld pad through discharge path and said K PNP transistor turns to earth terminal.The present invention has obvious improvement technically, and has tangible good effect, really is the new design of a novelty, progress, practicality.
Above-mentioned explanation only is the general introduction of technical scheme of the present invention; Understand technological means of the present invention in order can more to know; And can implement according to the content of specification, and for let of the present invention above-mentioned with other purposes, feature and advantage can be more obviously understandable, below special act preferred embodiment; And conjunction with figs., specify as follows.
Description of drawings
Fig. 1 is the sketch map according to the electrostatic discharge protective equipment of the first embodiment of the present invention.
Fig. 2 is the structural representation of electrostatic discharge protective equipment according to a second embodiment of the present invention.
Fig. 3 is the structural representation of the electrostatic discharge protective equipment of a third embodiment in accordance with the invention.
Fig. 4 is the structural representation of the electrostatic discharge protective equipment of a fourth embodiment in accordance with the invention.
Fig. 5 is the structural representation of electrostatic discharge protective equipment according to a fifth embodiment of the invention.
Fig. 6 is the circuit diagram according to the control circuit of one embodiment of the invention.
Fig. 7 is the circuit diagram according to the control circuit of another embodiment of the present invention.
Fig. 8 is the circuit diagram according to the control circuit of another embodiment of the present invention.
Fig. 9 A～Fig. 9 C is respectively the circuit diagram according to the protection circuit of one embodiment of the invention.
100,200,300,400,500: electrostatic discharge protective equipment
101: weld pad
110_1～110_K:PNP transistor
120,910～930: protection circuit
121,122,620,720,820,921:NMOS transistor
VD1, VD2, VD4, VD6, VD7, VD8, VD9: supply voltage
VG1, VG91: earthed voltage
I_Total: electrostatic induced current
I (1)～I (K), I_ptc: branch current
210,310,410,600,700,800: control circuit
VIO2, VIO3, VIO41～VIO44, VIO6, VIO71～VIO74, VIO81～VIO84, VIO9: isolation voltage
VH2, VH3, VH4, VH6, VH7, VH8: high voltage signal
510: diode
610,630,710,731～734,810,830,911,912,931:PMOS transistor
R81～R84: resistance
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention; Below in conjunction with accompanying drawing and preferred embodiment; To its embodiment of electrostatic discharge protective equipment, structure, characteristic and the effect thereof that proposes according to the present invention, specify as after.
Relevant aforementioned and other technology contents, characteristics and effect of the present invention can clearly appear in the following detailed description that cooperates with reference to graphic preferred embodiment.Explanation for ease, in following embodiment, components identical is represented with identical numbering.
[first embodiment]
Fig. 1 is the sketch map according to the electrostatic discharge protective equipment of the first embodiment of the present invention.See also shown in Figure 1ly, electrostatic discharge protective equipment 100 electrically connects a weld pad 101, and comprises K PNP transistor 110_1～110_K and protection circuit 120, and wherein K is a positive integer.Further, protection circuit 120 comprises nmos pass transistor 121 and nmos pass transistor 122.At this; Two-carrier junction transistor (the bipolar junction transistor that described PNP transistor 110_1～110_K is a positive-negative-positive; BJT); And described nmos pass transistor 121 and 122 be the N type mos field effect transistor (Complementary Metal-Oxide-Semiconductor, CMOS).
With regard to protection circuit 120, the drain electrode of nmos pass transistor 121 electrically connects the base stage of PNP transistor 110_K, and the grid of nmos pass transistor 121 receives a supply voltage VD1.In addition, the drain electrode of nmos pass transistor 122 electrically connects the source electrode of nmos pass transistor 121, and the grid of nmos pass transistor 122 receives an earthed voltage VG1, and the source electrode of nmos pass transistor 122 is electrically connected to earth terminal.With regard to layout structure, the nmos pass transistor 121 and 122 of two serial connections has parasitic horizontal NPN transistor, so protection circuit 120 can provide a discharge path.
In addition, the emitter-base bandgap grading of the 1st PNP transistor 110_1 electrically connects weld pad 101, and the base stage of the 1st PNP transistor 110_1 electrically connects the emitter-base bandgap grading of the 2nd PNP transistor 110_2.In addition, the base stage of the 2nd the PNP transistor 110_2 base stage that electrically connects the emitter-base bandgap grading of the 3rd PNP transistor 110_3, the 3rd PNP transistor 110_3 electrically connects the emitter-base bandgap grading of the 4th PNP transistor 110_4 ... etc.By that analogy, the transistorized base stage of i PNP electrically connects the transistorized emitter-base bandgap grading of (i+1) individual PNP, and i is integer and 1≤i≤(K-1).Moreover the collection utmost point of described K PNP transistor 110_1～110_K is electrically connected to earth terminal, to form K individual path.
In practical application, weld pad 101 is electrically connected to an internal circuit (not showing), and electrostatic discharge protective equipment 100 then is under the prerequisite that does not influence the internal circuit normal running, avoids from the electrostatic signal of weld pad 101 internal circuit being caused damage.Therefore, when supply voltage VD1 was supplied, internal circuit was with normal running.In addition, the grid of nmos pass transistor 122 will receive earthed voltage VG1, and then intercept weld pad 101 conductings to earth terminal.Thus, can suppress protection circuit 120 formed leakage currents, and then avoid internal circuit to receive the influence of electrostatic discharge protective equipment 100.
When electrostatic discharge event takes place, will impel the p among PNP transistor 110_1～110_K from the electrostatic signal of weld pad 101
+-n connects face (that is penetrate-base stage connect face) and is biased in forward bias voltage drop.By this, the electrostatic signal of a part can be through the p among PNP transistor 110_1～110_K
+-n-p structure (that is individual path) branches to earth terminal, and the electrostatic signal of another part then will be passed to protection circuit 120 through PNP transistor 110_1～110_K step by step.In addition, the electrostatic signal that is sent to protection circuit 120 can be passed through the parasitic formed discharge path of NPN transistor, and conducted to earth terminal.
For instance; If flowing into the electrostatic induced current of weld pad 101 is I_Total; And the formed branch current of individual path through PNP transistor 110_1～110_K be respectively I (1), I (2), I (3) ..., I (K), the branch current I_ptc that then is sent to protection circuit 120 will be suc as formula shown in (1):
I_ptc=I_Total-I (1)-I (2)-I (3)-...-I (K) formula (1)
If with the common emitter current gain, that is β=(I
C/ I
B), come again expression (1), then formula (1) can be rewritten as:
I_Total=(1+ β)
K* I_ptc formula (2)
Wherein, K is the transistorized number of serial connection PNP, and IC is the transistorized collected current of PNP, and I
BBe the transistorized base current of PNP.
In other words, when electrostatic discharge event takes place, from the electrostatic signal of weld pad 101 can be through protection circuit 120 the individual path conducting of discharge path and PNP transistor 110_1～110_K to earth terminal.Thus; Because the electrostatic signal from weld pad 101 can be through PNP transistor 110_1～110_K conducting to earth terminal; Therefore the discharge path of protection circuit 120 need not bear excessive electrostatic induced current, that is to say that protection circuit 120 required rated current of bearing can be lowered.Relatively, in the design of circuit layout, the layout area of protection circuit 120 can be lowered, and then reduces the influence of process shifts to electrostatic discharge protective equipment 100.
[second embodiment]
Fig. 2 is the structural representation of electrostatic discharge protective equipment according to a second embodiment of the present invention.See also shown in Figure 2ly, the present embodiment and first embodiment are roughly the same, and same or analogous element numbers is represented same or analogous element among Fig. 2, just repeats no more in the present embodiment.
Present embodiment and the main difference of first embodiment are: electrostatic discharge protective equipment 200 more comprises control circuit 210, and the grid of the nmos pass transistor in the protection circuit 120 121 is in order to receive isolation voltage VIO2.In the present embodiment, control circuit 210 electrically connects weld pad 101.In addition, when supply voltage VD2 was supplied, the internal circuit (not showing) that is connected to weld pad 101 was with normal running, and internal circuit can receive a high voltage signal VH2 through weld pad 101.On the other hand, the control circuit 210 of this moment will receive supply voltage VD2 with from the high voltage signal VH2 of weld pad 101.
In addition, when supply voltage VD2 was supplied, control circuit 210 can produce isolation voltage VIO2 according to high voltage signal VH2, and wherein the described isolation voltage VIO2 of present embodiment is a high voltage level.Therefore, when the nmos pass transistor in the protection circuit 120 121 received isolation voltage VIO2, the breakdown voltage (breakdown voltage) that the parasitic p-n in the nmos pass transistor 121 connects face will be enhanced, and then the leakage current of the protection circuit 120 that suppresses to flow through.In other words, in the present embodiment, when supply voltage VD2 was supplied, control circuit 210 can produce isolation voltage VIO2, and protection circuit 120 will be according to isolation voltage VIO2 suppress the to flow through leakage current of protection circuit 120.Wherein, shown in (2), electrostatic induced current I_Total will reduce along with reducing of branch current I_ptc.In addition, when electrostatic discharge event takes place, voltage source VD2 will not be provided to control circuit 210, and control circuit 210 can not produce isolation voltage VIO2.By this, the grid of nmos pass transistor 121 will be in the state of suspension joint, and then improve the protective capacities of protection circuit 120.
In addition; With first embodiment similarly; When electrostatic discharge event takes place, from the electrostatic signal of weld pad 101 can be through protection circuit 120 discharge path and PNP transistor 110_1～110_K conducting to earth terminal, and then avoid electrostatic signal that internal circuit is caused damage.In addition, because electrostatic signal can be through PNP transistor 110_1～110_K conducting to earth terminal, so the layout area of protection circuit 120 can be lowered effectively, and then reduces the influence of process shifts to electrostatic discharge protective equipment 200.
[the 3rd embodiment]
Fig. 3 is the structural representation of the electrostatic discharge protective equipment of a third embodiment in accordance with the invention.See also shown in Figure 3ly, the present embodiment and first embodiment are roughly the same, and same or analogous element numbers is represented same or analogous element among Fig. 3, just repeats no more in the present embodiment.
Present embodiment and the main difference of first embodiment are: electrostatic discharge protective equipment 300 more comprises control circuit 310, and the base stage of PNP transistor 110_K more receives isolation voltage VIO3.In the present embodiment, control circuit 310 electrically connects weld pad 101.In addition, when supply voltage VD1 was supplied, the internal circuit (not showing) that is connected to weld pad 101 was with normal running, and internal circuit can receive a high voltage signal VH3 through weld pad 101.On the other hand, the control circuit 310 of this moment will receive supply voltage VD1 with from the high voltage signal VH3 of weld pad 101.
In addition, when supply voltage VD1 was supplied, control circuit 310 will produce isolation voltage VIO3 according to high voltage signal VH3, and wherein the described isolation voltage VIO3 of present embodiment is a high voltage level.Therefore, when the base stage of PNP transistor 110_K when receiving isolation voltage VIO3, it penetrates-base stage connects face and will can not be biased under the forward bias voltage drop, and then the leakage current of the PNP transistor 110_K that suppresses to flow through.In other words, in the present embodiment, when supply voltage VD1 was supplied, control circuit 310 can produce isolation voltage VIO3, and then the leakage current of the PNP transistor 110_K that suppresses to flow through.What deserves to be mentioned is; Though present embodiment is that isolation voltage VIO3 is sent to PNP transistor 110_K; But this area has the technical staff of common knowledge also can be according to design; Isolation voltage VIO3 is sent to a certain PNP transistor among PNP transistor 110_1～110_K, can suppresses the generation of leakage current to cause the PNP transistor that receives isolation voltage VIO3.
In addition; With first embodiment similarly; When electrostatic discharge event takes place, from the electrostatic signal of weld pad 101 can be through protection circuit 120 discharge path and PNP transistor 110_1～110_K conducting to earth terminal, and then avoid electrostatic signal that internal circuit is caused damage.In addition, because electrostatic signal can be through PNP transistor 110_1～110_K conducting to earth terminal, so the layout area of protection circuit 120 can be lowered effectively, and then reduces the influence of process shifts to electrostatic discharge protective equipment 300.
[the 4th embodiment]
Fig. 4 is the structural representation of the electrostatic discharge protective equipment of a fourth embodiment in accordance with the invention.See also shown in Figure 4ly, the present embodiment and first embodiment are roughly the same, and same or analogous element numbers is represented same or analogous element among Fig. 4, just repeats no more in the present embodiment.
Present embodiment and the main difference of first embodiment are: electrostatic discharge protective equipment 400 more comprises control circuit 410; And the base stage of PNP transistor 110_1～110_K more receives isolation voltage VIO41～VIO44, and the grid of the nmos pass transistor in the protection circuit 120 121 is in order to receive isolation voltage VIO45.In the present embodiment, control circuit 410 electrically connects weld pad 101.In addition, when supply voltage VD4 was supplied, the internal circuit (not showing) that is connected to weld pad 101 was with normal running, and internal circuit can receive a high voltage signal VH4 through weld pad 101.On the other hand, the control circuit 410 of this moment will receive supply voltage VD4 with from the high voltage signal VH4 of weld pad 101.
In addition, when supply voltage VD4 was supplied, control circuit 410 will produce isolation voltage VIO41～VIO45 according to high voltage signal VH4, and wherein the described isolation voltage VIO41～VIO45 of present embodiment is a high voltage level.Therefore, when the nmos pass transistor in the protection circuit 120 121 received isolation voltage VIO45, the breakdown voltage that the parasitic p-n in the nmos pass transistor 121 connects face will be enhanced, and then the leakage current of the protection circuit 120 that suppresses to flow through.In addition, when the base stage of PNP transistor 110_1～110_K received isolation voltage VIO41～VIO44, it penetrated-base stage connects face and will can not be biased under the forward bias voltage drop, and then the leakage current of the PNP transistor 110_1～110_K that suppresses to flow through.
In other words, in the present embodiment, when supply voltage VD4 was supplied, control circuit 410 can produce isolation voltage VIO41～VIO45, and then the leakage current of suppress to flow through protection circuit 120 and PNP transistor 110_1～110_K.What deserves to be mentioned is; Though present embodiment is that isolation voltage VIO41～VIO44 is sent to each PNP transistor; But having the technical staff of common knowledge, this area also can isolation voltage VIO41～VIO44 be sent to the PNP transistor of part according to design.
In addition; With first embodiment similarly; When electrostatic discharge event takes place, from the electrostatic signal of weld pad 101 can be through protection circuit 120 discharge path and PNP transistor 110_1～110_K conducting to earth terminal, and then avoid electrostatic signal that internal circuit is caused damage.In addition, because electrostatic signal can be through PNP transistor 110_1～110_K conducting to earth terminal, so the layout area of protection circuit 120 can be lowered effectively, and then reduces the influence of process shifts to electrostatic discharge protective equipment 400.
[the 5th embodiment]
Fig. 5 is the structural representation of electrostatic discharge protective equipment according to a fifth embodiment of the invention.See also shown in Figure 5ly, the present embodiment and first embodiment are roughly the same, and same or analogous element numbers is represented same or analogous element among Fig. 5, just repeats no more in the present embodiment.
Present embodiment and the main difference of first embodiment are: electrostatic discharge protective equipment 500 more comprises diode 510.In the present embodiment, the anode of diode 510 is electrically connected to the base stage of PNP transistor 110_1, and the negative electrode of diode 510 is electrically connected to the emitter-base bandgap grading of PNP transistor 110_2.By this, diode 510 formed voltage drops can avoid protection circuit 120 directly to receive too high voltage level.Relatively, the breakdown voltage of parasitic NPN transistor can be done corresponding adjustment in the protection circuit 120.What deserves to be mentioned is; Though present embodiment is interspersed diode in the PNP transistor 110_1～110_K of serial connection only; But this area has the technical staff of common knowledge also can be according to design, interspersed a plurality of diodes in the PNP transistor 110_1～110_K of serial connection.In addition, the technical staff that this area has common knowledge also can intert one to a plurality of diodes with reference to Fig. 5 embodiment in the cited PNP transistor 110_1～110_K of Fig. 2 to Fig. 4 embodiment.
In addition; With first embodiment similarly; When electrostatic discharge event takes place, from the electrostatic signal of weld pad 101 can be through protection circuit 120 discharge path and PNP transistor 110_1～110_K conducting to earth terminal, and then avoid electrostatic signal that internal circuit is caused damage.In addition, because electrostatic signal can be through PNP transistor 110_1～110_K conducting to earth terminal, so the layout area of protection circuit 120 can be lowered effectively, and then reduces the influence of process shifts to electrostatic discharge protective equipment 500.
[the 6th embodiment]
Fig. 6 is the circuit diagram according to the control circuit of one embodiment of the invention.See also shown in Figure 6ly, control circuit 600 receives supply voltage VD6 and high voltage signal VH6, and in order to generation isolation voltage VIO6.Therefore, in practical application, the control circuit 210 and 310 that Fig. 2 and Fig. 3 embodiment are cited can utilize the control circuit 600 of Fig. 6 to realize respectively.
At this, control circuit 600 comprises PMOS transistor 610, nmos pass transistor 620 and PMOS transistor 630.Wherein, the source electrode of PMOS transistor 610 receives high voltage signal VH6.The drain electrode of nmos pass transistor 620 electrically connects the drain electrode of PMOS transistor 610, and the grid of nmos pass transistor 620 receives supply voltage VD6, and the source electrode of nmos pass transistor 620 is electrically connected to earth terminal.In addition; The source electrode of PMOS transistor 630 receives high voltage signal VH6; The grid of PMOS transistor 630 electrically connects the drain electrode of PMOS transistor 610, and the drain electrode of PMOS transistor 630 electrically connects the grid of PMOS transistor 610, and the drain electrode of PMOS transistor 630 is in order to produce isolation voltage VIO6.
In operation, when supply voltage VD6 and high voltage signal VH6 were supplied, nmos pass transistor 620 was conducting, and then caused the grid of PMOS transistor 630 to receive earthed voltage.By this, PMOS transistor 630 will the conducting according to received earthed voltage, and then drains through it and to produce isolation voltage VIO6.In addition, isolation voltage VIO6 will feed back to the grid of PMOS transistor 610, and then PMOS transistor 610 is latched in the state of not conducting.
On the other hand, when electrostatic discharge event took place, supply voltage VD6 was the state that is in float (floating), and its standard is near earthed voltage, so the time nmos pass transistor 620 can't conducting.In addition, the grid of PMOS transistor 630 can be coupled to high voltage signal VH6 through the parasitic capacitance of its grid to source electrode, so the time PMOS transistor 630 also can't conducting.Moreover the grid of PMOS transistor 610 is to be in the state of floating, and its grid voltage is less than high voltage signal VH6, so the time PMOS transistor 610 with conducting, and then breech lock lives control circuit 600, and guarantees that control circuit 600 can't export any signal.
[the 7th embodiment]
Fig. 7 is the circuit diagram according to the control circuit of another embodiment of the present invention.See also shown in Figure 7ly, control circuit 700 receives supply voltage VD7 and high voltage signal VH7, and in order to produce a plurality of isolation voltage VIO71～VIO74.Therefore, in practical application, the control circuit 700 of control circuit 410 Fig. 7 capable of using that Fig. 4 embodiment is cited is realized.
At this, control circuit 700 comprises PMOS transistor 710, nmos pass transistor 720 and PMOS transistor 731～734.Wherein, the source electrode of PMOS transistor 710 receives high voltage signal VH7.The drain electrode of nmos pass transistor 720 electrically connects the drain electrode of PMOS transistor 710, and the grid of nmos pass transistor 720 receives supply voltage VD7, and the source electrode of nmos pass transistor 720 is electrically connected to earth terminal.The source electrode of PMOS transistor 731～734 receives high voltage signal VH7, and the grid of PMOS transistor 731～734 electrically connects the drain electrode of PMOS transistor 710, and the drain electrode of PMOS transistor 731～734 is in order to produce isolation voltage VIO71～VIO74.In addition, the drain electrode of PMOS transistor 731 electrically connects the grid of PMOS transistor 710.
In operation; When supply voltage VD7 and high voltage signal VH7 are supplied; Nmos pass transistor 720 is conducting, and then causes the grid of PMOS transistor 731～734 to receive earthed voltage, and then causes the drain electrode of PMOS transistor 731～734 to produce isolation voltage VIO71～VIO74.In addition, isolation voltage VIO71 will feed back to the grid of PMOS transistor 710, PMOS transistor 710 is latched in the state of not conducting.
On the other hand, when electrostatic discharge event takes place, supply voltage VD7 the position brigadier near earthed voltage, so the time nmos pass transistor 720 can't conducting.In addition, the grid of PMOS transistor 731～734 can be respectively parasitic capacitance through its grid to source electrode be coupled to high voltage signal VH7, so the time PMOS transistor 731～734 also can't conducting.Moreover the grid of PMOS transistor 710 is to be in the state of floating, and its grid voltage is less than high voltage signal VH7, so the time PMOS transistor 710 with conducting, and then breech lock lives control circuit 700, and guarantees that control circuit 700 can't export any signal.
[the 8th embodiment]
Fig. 8 is the circuit diagram according to the control circuit of another embodiment of the present invention.See also shown in Figure 8ly, control circuit 800 receives supply voltage VD8 and high voltage signal VH8, and in order to produce a plurality of isolation voltage VIO81～VIO84.Therefore, in practical application, the cited control circuit 410 of Fig. 4 embodiment also control circuit 800 of Fig. 8 capable of using is realized.
At this, control circuit 800 comprises PMOS transistor 810, nmos pass transistor 820, PMOS transistor 830 and a plurality of resistance R 81～R84.Wherein, the source electrode of PMOS transistor 810 receives high voltage signal VH8.The drain electrode of nmos pass transistor 820 electrically connects the drain electrode of PMOS transistor 810, and the grid of nmos pass transistor 820 receives supply voltage VD8, and the source electrode of nmos pass transistor 820 is electrically connected to earth terminal.In addition; The source electrode of PMOS transistor 830 receives high voltage signal VH8; The grid of PMOS transistor 830 electrically connects the drain electrode of PMOS transistor 810, and the drain electrode of PMOS transistor 830 electrically connects the grid of PMOS transistor 810 and first end of resistance R 81～R84.Moreover second end of resistance R 81～R84 is in order to produce isolation voltage VIO81～VIO84.
In the present embodiment, transistor 810,820 and 830 operation mechanism are identical with the operation mechanism of transistor 610,620 among Fig. 6 and transistor 630.Therefore, when supply voltage VD8 and high voltage signal VH8 were supplied, nmos pass transistor 820 and PMOS transistor 830 be conducting, and then impel first end of resistance R 81～R84 to receive high voltage signal VH8 respectively.By this, it is last at resistance R 81～R84 that high voltage signal VH8 will distinguish pressure drop, and then impel resistance R 81～R84 to produce isolation voltage VIO81～VIO84.In addition, PMOS transistor 810 will be latched in the state of not conducting.On the other hand, when electrostatic discharge event took place, nmos pass transistor 820 and PMOS transistor 830 can't conductings, and then impel first end of resistance R 81～R84 to be in the state of floating.Moreover PMOS transistor 810 is conducting, and then breech lock lives control circuit 800, and guarantees that control circuit 800 can't export any signal.
[the 9th embodiment]
Fig. 9 A～Fig. 9 C is respectively the circuit diagram according to the protection circuit of one embodiment of the invention.Shown in Fig. 9 A, protection circuit 910 is made up of PMOS transistor 911 and 912 of two serial connections.Wherein, the source electrode of PMOS transistor 911 electrically connects the base stage of K PNP transistor 110_K.The source electrode of PMOS transistor 912 electrically connects the drain electrode of PMOS transistor 911, and the grid of PMOS transistor 912 receives a supply voltage VD9, and the drain electrode of PMOS transistor 912 is electrically connected to earth terminal.
In practical application, PMOS transistor 911 is in order to intercepting the weld pad conducting to earth terminal, and the parasitic lateral PNP transistor in the PMOS transistor 911 and 912 of two serial connections can provide a discharge path.In practical application, the grid of PMOS transistor 911 can be electrically connected to its source electrode or receive isolation voltage VIO9.When the grid of PMOS transistor 911 was electrically connected to its source electrode, the cited protection circuit 120 of Fig. 1, Fig. 3 and Fig. 5 embodiment was realized the protection circuit 910 of Fig. 9 capable of using.In addition, when the grid of PMOS transistor 911 is when receiving adjustable isolation voltage VIO9, the cited protection circuit 120 of Fig. 2 and Fig. 4 embodiment is realized the protection circuit 910 of Fig. 9 capable of using.
What deserves to be mentioned is that the cited protection circuit 120 of Fig. 1 to Fig. 5 embodiment is to utilize the nmos pass transistor of two serial connections to realize, the cited protection circuit 910 of Fig. 9 embodiment then is to utilize the PMOS transistor of two serial connections to realize.Wherein, under fixing layout area, the rated transformation ratio PMOS transistor that nmos pass transistor can bear is greater.Therefore, in practical application, protection circuit 910 must expend bigger layout area, and its rated current that can bear could be identical with protection circuit 120.In other words, the technical staff of this area with common knowledge can adjust the thin portion framework of protection circuit according to the required rated current of protection circuit.In addition, though above-mentioned each embodiment is connected in series with two identical MOS transistors of kenel, the technical staff that this area has common knowledge also can adopt kenel two MOS transistors inequality to realize protection circuit.
In addition, protection circuit single MOS transistor also capable of using is realized.For instance, shown in Fig. 9 B, protection circuit 920 comprises a nmos pass transistor 921.Wherein, the drain electrode of nmos pass transistor 921 electrically connects the base stage of K PNP transistor 110_K, and the grid of nmos pass transistor 921 receives an earthed voltage VG91, and the source electrode of nmos pass transistor 921 is electrically connected to earth terminal.In addition, shown in Fig. 9 C, protection circuit 930 comprises a PMOS transistor 931.Wherein, the source electrode of PMOS transistor 931 and grid electrically connect the base stage of K PNP transistor 110_K, and the drain electrode of PMOS transistor 931 is electrically connected to earth terminal.What deserves to be mentioned is that the protection circuit of being realized by single MOS transistor mainly is to be biased under the state of not conducting, so the cited protection circuit 920 of Fig. 9 B and Fig. 9 C can be applied in respectively among Fig. 1, Fig. 3 and Fig. 5 embodiment with protection circuit 930.
In sum, the present invention is electrically connected at a plurality of PNP transistors that are connected in series between weld pad and the protection circuit.Thus, can pass through the PNP transistor turns to earth terminal from the electrostatic signal of weld pad, and then reduce the required rated current of bearing of protection circuit.In addition, the layout area of protection circuit will diminish along with the reduction of rated current, therefore can reduce the influence of process shifts to electrostatic discharge protective equipment.In addition, electrostatic discharge protective equipment of the present invention control circuit more capable of using produces isolation voltage, to suppress protection circuit or the formed leakage current of PNP transistor.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction; Though the present invention discloses as above with preferred embodiment; Yet be not in order to limiting the present invention, anyly be familiar with the professional and technical personnel, in not breaking away from technical scheme scope of the present invention; When the technology contents of above-mentioned announcement capable of using is made a little change or is modified to the equivalent embodiment of equivalent variations; In every case be not break away from technical scheme content of the present invention, to any simple modification, equivalent variations and modification that above embodiment did, all still belong in the scope of technical scheme of the present invention according to technical spirit of the present invention.
Claims (14)
1. an electrostatic discharge protective equipment electrically connects a weld pad, it is characterized in that this electrostatic discharge protective equipment comprises:
K PNP transistor; Wherein the 1st the transistorized emitter-base bandgap grading of PNP electrically connects this weld pad, and i the transistorized base stage of PNP electrically connects the transistorized emitter-base bandgap grading of (i+1) individual PNP, and the transistorized collection utmost point of those PNP electrically connects an earth terminal; K is a positive integer, and i is integer and 1≤i≤(K-1); And
One protection circuit is electrically connected between K the transistorized base stage of PNP and this earth terminal, and this protection circuit provides a discharge path, wherein from an electrostatic signal of this weld pad through this discharge path and those PNP transistor turns to this earth terminal.
2. electrostatic discharge protective equipment according to claim 1 it is characterized in that wherein said weld pad in order to receiving a high voltage signal, and this electrostatic discharge protective equipment comprises also:
One first control circuit; Electrically connect this weld pad, and receive a supply voltage, wherein; When this supply voltage is supplied; This first control circuit produces an isolation voltage according to this high voltage signal, and the specific PNP transistor in this protection circuit or those PNP transistors, suppresses to flow through this protection circuit or the transistorized leakage current of this specific PNP according to this isolation voltage.
3. electrostatic discharge protective equipment according to claim 2 is characterized in that wherein said first control circuit comprises:
One the one PMOS transistor, wherein the transistorized source electrode of a PMOS receives this high voltage signal;
One first nmos pass transistor, wherein the drain electrode of this first nmos pass transistor electrically connects a PMOS transistor drain, and the grid of this first nmos pass transistor receives this supply voltage, and the source electrode of this first nmos pass transistor electrically connects this earth terminal; And
One the 2nd PMOS transistor; Wherein the transistorized source electrode of the 2nd PMOS receives this high voltage signal; The transistorized grid of the 2nd PMOS electrically connects a PMOS transistor drain; The 2nd PMOS transistor drain electrically connects the transistorized grid of a PMOS, and the 2nd PMOS transistor drain is in order to produce this isolation voltage.
4. electrostatic discharge protective equipment according to claim 1 it is characterized in that wherein said weld pad in order to receiving a high voltage signal, and this electrostatic discharge protective equipment comprises also:
One second control circuit; Electrically connect this weld pad; And receive a supply voltage; Wherein when this supply voltage was supplied, this second control circuit produced a plurality of isolation voltages according to this high voltage signal, and this protection circuit suppresses to flow through this protection circuit and the transistorized leakage current of those PNP of said part with those PNP transistors of part according to those isolation voltages.
5. electrostatic discharge protective equipment according to claim 4 is characterized in that wherein said second control circuit comprises:
One the 3rd PMOS transistor, wherein the transistorized source electrode of the 3rd PMOS receives this high voltage signal;
One second nmos pass transistor, wherein the drain electrode of this second nmos pass transistor electrically connects the 3rd PMOS transistor drain, and the grid of this second nmos pass transistor receives this supply voltage, and the source electrode of this second nmos pass transistor electrically connects this earth terminal; And
A plurality of the 4th PMOS transistors; Wherein the transistorized source electrode of those the 4th PMOS receives this high voltage signal; The transistorized grid of those the 4th PMOS electrically connects the 3rd PMOS transistor drain; Transistorized one of them the drain electrode of those the 4th PMOS electrically connects the transistorized grid of the 3rd PMOS, and those the 4th PMOS transistor drain are in order to produce those isolation voltages.
6. electrostatic discharge protective equipment according to claim 4 is characterized in that wherein said second control circuit comprises:
One the 5th PMOS transistor, wherein the transistorized source electrode of the 5th PMOS receives this high voltage signal;
One the 3rd nmos pass transistor, wherein the drain electrode of the 3rd nmos pass transistor electrically connects the 5th PMOS transistor drain, and the grid of the 3rd nmos pass transistor receives this supply voltage, and the source electrode of the 3rd nmos pass transistor electrically connects this earth terminal;
One the 6th PMOS transistor; Wherein the transistorized source electrode of the 6th PMOS receives this high voltage signal; The transistorized grid of the 6th PMOS electrically connects the 5th PMOS transistor drain, and the 6th PMOS transistor drain electrically connects the transistorized grid of the 5th PMOS; And
A plurality of resistance, first end of those resistance electrically connects the 5th PMOS transistor drain, and second end of those resistance is in order to produce those isolation voltages.
7. electrostatic discharge protective equipment according to claim 1 is characterized in that it also comprises:
A plurality of diodes intert respectively between the two adjacent PNP transistors in those PNP transistors.
8. electrostatic discharge protective equipment according to claim 1 is characterized in that wherein said protection circuit comprises:
One the 4th nmos pass transistor, wherein the drain electrode of the 4th nmos pass transistor electrically connects K the transistorized base stage of PNP, and the grid of the 4th nmos pass transistor receives a supply voltage or an isolation voltage; And
One the 5th nmos pass transistor, wherein the drain electrode of the 5th nmos pass transistor electrically connects the source electrode of the 4th nmos pass transistor, and the grid of the 5th nmos pass transistor receives an earthed voltage, and the source electrode of the 5th nmos pass transistor is electrically connected to this earth terminal.
9. electrostatic discharge protective equipment according to claim 1; It is characterized in that wherein said protection circuit comprises one the 6th nmos pass transistor; And the drain electrode of the 6th nmos pass transistor electrically connects K the transistorized base stage of PNP; The grid of the 6th nmos pass transistor receives an earthed voltage, and the source electrode of the 6th nmos pass transistor is electrically connected to this earth terminal.
10. electrostatic discharge protective equipment according to claim 1 is characterized in that wherein said protection circuit comprises:
One the 7th PMOS transistor, wherein the transistorized source electrode of the 7th PMOS electrically connects K the transistorized base stage of PNP, and the transistorized grid of the 7th PMOS electrically connects its source electrode or receives an isolation voltage; And
One the 8th PMOS transistor, wherein the transistorized source electrode of the 8th PMOS electrically connects the 7th PMOS transistor drain, and the transistorized grid of the 8th PMOS receives a supply voltage, and the 8th PMOS transistor drain is electrically connected to this earth terminal.
11. electrostatic discharge protective equipment according to claim 1; It is characterized in that wherein said protection circuit comprises one the 9th PMOS transistor; And transistorized source electrode of the 9th PMOS and grid electrically connect K the transistorized base stage of PNP, and the 9th PMOS transistor drain is electrically connected to this earth terminal.
12. an electrostatic discharge protective equipment electrically connects a weld pad, it is characterized in that this electrostatic discharge protective equipment comprises:
K PNP transistor; K individual path of conducting to an earth terminal is provided; Wherein the 1st PNP transistor electrically connects this weld pad, and i PNP transistor electrically connects (i+1) individual PNP transistor and i individual path is provided, and K PNP transistor provides K individual path; K is a positive integer, and i is integer and 1≤i≤(K-1); And
One protection circuit is electrically connected between K this earth terminal of PNP transistor AND gate, and this protection circuit provides a discharge path, wherein from an electrostatic signal of this weld pad through this discharge path and those individual path conductings to this earth terminal.
13. electrostatic discharge protective equipment according to claim 12 it is characterized in that wherein said weld pad in order to receiving a high voltage signal, and this electrostatic discharge protective equipment comprises also:
One first control circuit; Electrically connect this weld pad, and receive a supply voltage, wherein; When this supply voltage is supplied; This first control circuit produces an isolation voltage according to this high voltage signal, and the specific PNP transistor in this protection circuit or those PNP transistors, suppresses to flow through this protection circuit or the transistorized leakage current of this specific PNP according to this isolation voltage.
14. electrostatic discharge protective equipment according to claim 12 it is characterized in that wherein said weld pad in order to receiving a high voltage signal, and this electrostatic discharge protective equipment comprises also:
One second control circuit; Electrically connect this weld pad; And receive a supply voltage, wherein, when this supply voltage is supplied; This second control circuit produces a plurality of isolation voltages according to this high voltage signal, and this protection circuit suppresses to flow through this protection circuit and the transistorized leakage current of those PNP of said part with those PNP transistors of part according to those isolation voltages.
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| CN201110121777.XA CN102779816B (en) | 2011-05-09 | 2011-05-09 | Electrostatic discharge protective equipment |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877927A (en) * | 1996-10-01 | 1999-03-02 | Intel Corporation | Method and apparatus for providing electrostatic discharge protection for high voltage inputs |
| US20020027755A1 (en) * | 1999-06-03 | 2002-03-07 | Andresen Bernhard H. | Shared 5 volt tolerant ESD protection circuit for low voltage CMOS process |
| CN1881582A (en) * | 2005-06-14 | 2006-12-20 | 台湾积体电路制造股份有限公司 | Esd protection circuit and semiconductor structure |
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2011
- 2011-05-09 CN CN201110121777.XA patent/CN102779816B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877927A (en) * | 1996-10-01 | 1999-03-02 | Intel Corporation | Method and apparatus for providing electrostatic discharge protection for high voltage inputs |
| US20020027755A1 (en) * | 1999-06-03 | 2002-03-07 | Andresen Bernhard H. | Shared 5 volt tolerant ESD protection circuit for low voltage CMOS process |
| CN1881582A (en) * | 2005-06-14 | 2006-12-20 | 台湾积体电路制造股份有限公司 | Esd protection circuit and semiconductor structure |
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