CN102779803A - Integrated circuit chip package and manufacturing method thereof - Google Patents
Integrated circuit chip package and manufacturing method thereof Download PDFInfo
- Publication number
- CN102779803A CN102779803A CN2011101236588A CN201110123658A CN102779803A CN 102779803 A CN102779803 A CN 102779803A CN 2011101236588 A CN2011101236588 A CN 2011101236588A CN 201110123658 A CN201110123658 A CN 201110123658A CN 102779803 A CN102779803 A CN 102779803A
- Authority
- CN
- China
- Prior art keywords
- chip
- lead frame
- array
- layer
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention provides an integrated circuit chip package and a manufacturing method thereof. The integrated circuit chip package comprises a lead frame, at least one circuit rerouting layer and a solder ball array, wherein the lead frame comprises a lead frame array which is composed of a plurality of conductive units, and part of the conductive units are provided with first extension wires; the circuit rerouting layer is provided with a plurality of second extension wires which are used for being electrically connected to the first extension wires or the second extension wires on various circuit rerouting layers; and the solder ball array is provided with a plurality of solder balls which are used for being electrically connected to the guide frame array.
Description
Technical field
The present invention relates to a kind of IC chip encapsulation and manufacturing approach thereof.
Background technology
The leaded package of Figure 1A and 1B demonstration prior art is overlooked and cross-sectional schematic.Shown in Figure 1A, lead frame 10 comprises a plurality of pins 1 (lead), utilizes routing (wire bond) technology, and pin 1 is electrically connected to IC chip 2 via a plurality of leads 3 respectively.Figure 1B shows the cross-sectional schematic of AA ' hatching line among Figure 1A; Shown in Figure 1B; IC chip 2 is attached on the chip template 5 (die paddle) in the lead frame 10, and through behind the routing, IC chip 2 is electrically connected to the pin 1 in the lead frame 10 via lead 3; Then with adhesive layer 4 sealings (molding) IC chip 2, lead frame 10, with lead 3, just accomplish the IC chip encapsulation.Then, pin 1 is fixed on the circuit board 6, just can makes this IC chip 2 become the part of circuit on the circuit board 6.
Evolution along with the IC chip encapsulation technology; In lead frame 10, need be with the spacing between pin and pin (pitch) micro dwindling the size of IC chip encapsulation, but the leaded package of this prior art; On the spacing that shortens between pin and pin; Its bottleneck is arranged, therefore limited the development of leaded package technology on the size micro, can't reduce the space cost of integrated circuit.In addition, in the consumption of lead 3, also can't reduce.
In view of this; The present invention proposes a kind of IC chip encapsulation and manufacturing approach thereof promptly to the deficiency of above-mentioned prior art, can further reduce the IC chip package dimension; And the consumption of minimizing lead, to reduce the cost of whole IC chip encapsulation.
Summary of the invention
The objective of the invention is to overcome the deficiency and the defective of prior art, propose a kind of IC chip encapsulation and manufacturing approach thereof.
For reaching above-mentioned purpose,, the invention provides a kind of IC chip encapsulation with regard to one of them viewpoint speech; In order to encapsulate an IC chip; Comprise: a lead frame, comprise the lead frame array formed by a plurality of conductive unit, wherein the part conductive unit has first extension wire; At least one circuit rerouting layer; Have a plurality of second extension wires; When one deck circuit rerouting layer is only arranged; These a plurality of second extension wires are respectively in order to being electrically connected to first extension wire of this lead frame, and during circuit rerouting layer more than two-layer, these a plurality of second extension wires are respectively in order to first extension wire that is electrically connected to this lead frame or second extension wire of different circuit rerouting layers; And a solder ball array, have a plurality of tin balls, in order to be electrically connected to this lead frame array.
With regard to another viewpoint speech, the invention provides a kind of manufacturing approach of IC chip encapsulation, comprise: a lead frame is provided, and this lead frame comprises the lead frame array be made up of a plurality of conductive unit, and wherein the part conductive unit has first extension wire; Form at least one circuit rerouting layer; Have a plurality of second extension wires; When one deck circuit rerouting layer is only arranged; These a plurality of second extension wires are respectively in order to being electrically connected to first extension wire of this lead frame, and during circuit rerouting layer more than two-layer, these a plurality of second extension wires are respectively in order to first extension wire that is electrically connected to this lead frame or second extension wire of different circuit rerouting layers; And electrically connect one have a plurality of tin balls solder ball array to this lead frame.
In a kind of enforcement kenel, between lead frame and solder ball array, can more comprise the metal pad array of forming by a plurality of metal pad, these a plurality of metal pads are electrically connected to this a plurality of conductive units respectively; And the coating layer of clad metal weld pad array.Wherein, coating layer for example can be but is not limited to anti-welding green lacquer (Solder Mask).
Explain in detail through specific embodiment below, when the effect that is easier to understand the object of the invention, technology contents, characteristics and is reached.
Description of drawings
Figure 1A shows the leaded package schematic top plan view of prior art;
Figure 1B shows the leaded package cross-sectional schematic of prior art;
Fig. 2 A-2F shows first embodiment of the present invention;
Fig. 3 shows an alternative embodiment of the invention;
Fig. 4 shows another embodiment again of the present invention.
Symbol description among the figure
1 pin
2 IC chips
3 leads
4 adhesive layers
5 chip templates
6 circuit boards
10,11 lead frames
12 conductive units
13 first extension wires
14 metal pads
15 coating layers
21 circuit rerouting layers
22 second extension wires
221 first ends
222 second ends
31 chip pad
41 solder ball array
42 tin balls
51 articulamentums
52 coupling bars
53 projections
Embodiment
Illustrate graphic all genus the among the present invention, mainly be intended to represent the relation between each structure division, then according to scale as for shape, thickness and width.
See also Fig. 2 A-2F, show first embodiment of the present invention.Shown in Fig. 2 A, lead frame 11 comprises a lead frame array of being made up of a plurality of conductive units 12, and partially conductive unit 12 has first extension wire 13.Wherein, conductive unit 12 can also be square or other arbitrary shape such as but not limited to circle as shown in the figure; And first extension wire 13 is such as but not limited to shown in Fig. 2 A, and the end of all first extension wires 13 is all extended to the edge of lead frame, and arrangement that can also the sight path rerouting extends to other suitable position with first extension wire 13.
Next see also Fig. 2 B; Circuit rerouting layer 21; Comprise a plurality of second extension wires 22, each second extension wire 22 has first end 221 and second end 222, and wherein second end 222 is respectively in order to the end of first extension wire 13 that is electrically connected to lead frame 11.According to notion of the present invention, circuit rerouting layer 21 can be simple layer or multilayer, but in the present embodiment, simplifies so that the relation between multilayer is easy to come into plain view for making icon, is that simple layer is an example with circuit rerouting layer 21 only.If adopt the execution mode of multilayer line rerouting layer 21, then only need second extension wire 22 of different layers suitably to be connected up and down, and suitably be electrically connected to first extension wire 13 of lead frame 11 according to the needs that electrically connect, get final product.
Then see also Fig. 2 C again; In this schematic top plan view explanation present embodiment, circuit rerouting layer 21 is formed on the lead frame 11, and after the electric connection of accomplishing rerouting layer 21 and lead frame 11; IC chip 2 is arranged on the circuit rerouting layer 21; And on the IC chip 2, have a plurality of chip pad 31, in order to be electrically connected to first end 221 of second extension wire 22 respectively.Look it by schematic top plan view, second end 222 of second extension wire 22, terminal overlapping with first extension wire 13, the layout of this lead is the purpose that electrically connects for facility, electric connection mode wherein will be in the back civilian illustrated.And first end 221 of second extension wire 22, preferably be arranged in IC chip 2 around, in order to being electrically connected to chip pad 31.
Next see also Fig. 2 D again, as shown in the figure, first end 221 of the chip pad 31 and second extension wire 22 electrically connects with routing techniques make use lead 13, or utilizes projection 53 to electrically connect with Flip Chip.Please consult Fig. 2 E simultaneously; The cross-sectional schematic of BB ' hatching line among the displayed map 2D; IC chip 2 is attached on the circuit rerouting layer 21, and through behind the routing, IC chip 2 is electrically connected to first end 221 of second extension wire 22 in the circuit rerouting layer 21 via lead 3; Fig. 2 F shows the cross-sectional schematic of utilizing first end 221 of the projection 53 electric connection chip pad 31 and second extension wire 22 with Flip Chip.Then with adhesive layer 4 sealing IC chips 2, with circuit rerouting layer 21.And second end 222 of extension wire 22 is via the coupling bar in the articulamentum 51 52, to be electrically connected to first extension wire, 13 ends in the lead frame 11.Then, a plurality of tin balls 42 in the solder ball array 41 are connected to a plurality of conductive units 12 respectively, just accomplish the IC chip encapsulation.
Fig. 3 shows an alternative embodiment of the invention; Different with first embodiment is; The IC chip encapsulation of present embodiment; Between lead frame 11 and solder ball array 41, more comprise the metal pad array of being formed by a plurality of metal pads 14, and a plurality of metal pad 14 is electrically connected to a plurality of conductive units 12 in the lead frame array respectively; And the coating layer 15 of clad metal weld pad array.Wherein, coating layer 15 for example can be but is not limited to anti-welding green lacquer.
Fig. 4 shows another embodiment again of the present invention, and different with first embodiment is that present embodiment comprises the circuit rerouting layer 21 of multilayer, and electrically connects with the articulamentum 51 of multilayer.
The present invention is through the mode of single or multiple lift circuit rerouting; Shortened packaging and routing distance, saved the routing cost; And avoided the prior art routing apart from the layout puzzlement that distance differs and caused, and make the spacing between pin and pin be able to micro, reduced the space cost of integrated circuit.
Below to preferred embodiment the present invention being described, is the above, be merely to make those skilled in the art be easy to understand content of the present invention, and be not to be used for limiting interest field of the present invention.Under same spirit of the present invention, those skilled in the art can think and various equivalence changes.For example, lead frame array, solder ball array or metal pad array can also be other shape arrangement arbitrarily except row's shape of rectangle; And for example, the chip pad on the IC chip is not limited to be arranged at the integrated circuit edge, can certainly be arranged at other position on the IC chip.Scope of the present invention should contain above-mentioned and other all equivalences change.
Claims (10)
1. an IC chip encapsulation in order to encapsulate an IC chip, is characterized in that, comprises:
One lead frame comprises the lead frame array be made up of a plurality of conductive unit, and wherein the part conductive unit has first extension wire;
At least one circuit rerouting layer; Have a plurality of second extension wires; When one deck circuit rerouting layer is only arranged; These a plurality of second extension wires are respectively in order to being electrically connected to first extension wire of this lead frame, and during circuit rerouting layer more than two-layer, these a plurality of second extension wires are respectively in order to first extension wire that is electrically connected to this lead frame or second extension wire of different circuit rerouting layers; And
One solder ball array has a plurality of tin balls, in order to be electrically connected to this lead frame array.
2. IC chip as claimed in claim 1 encapsulation wherein, also comprises an adhesive layer, in order to cover this circuit rerouting layer, with this IC chip.
3. IC chip encapsulation as claimed in claim 1 wherein, also comprises:
One metal pad array has a plurality of metal pads, in order to be electrically connected to this lead frame array; And
One coating layer coats this metal pad array.
4. IC chip encapsulation as claimed in claim 3, wherein, this coating layer comprises an anti-welding green lacquer.
5. IC chip encapsulation as claimed in claim 1, wherein, this IC chip has a plurality of chip pad, utilizes routing technology or Flip Chip that this chip pad is electrically connected to this second extension wire.
6. the manufacturing approach of an IC chip encapsulation is characterized in that, comprises:
One lead frame is provided, and this lead frame comprises the lead frame array be made up of a plurality of conductive unit, and wherein the part conductive unit has first extension wire;
Form at least one circuit rerouting layer; Have a plurality of second extension wires; When one deck circuit rerouting layer is only arranged; These a plurality of second extension wires are respectively in order to being electrically connected to first extension wire of this lead frame, and during circuit rerouting layer more than two-layer, these a plurality of second extension wires are respectively in order to first extension wire that is electrically connected to this lead frame or second extension wire of different circuit rerouting layers; And
The solder ball array that electric connection one has a plurality of tin balls is to this lead frame.
7. the manufacturing approach of IC chip as claimed in claim 6 encapsulation wherein, also comprises with an adhesive layer, cover this circuit rerouting layer, with this IC chip.
8. the manufacturing approach of IC chip encapsulation as claimed in claim 6 wherein, also comprises:
One metal pad array is provided, has a plurality of metal pads, in order to be electrically connected to this lead frame array; And
With a coating layer, coat this metal pad array.
9. the manufacturing approach of IC chip encapsulation as claimed in claim 8, wherein, this coating layer comprises an anti-welding green lacquer.
10. the manufacturing approach of IC chip encapsulation as claimed in claim 6 wherein, also comprises and utilizes routing technology or Flip Chip with a plurality of chip pad on this IC chip, is electrically connected to this second extension wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101236588A CN102779803A (en) | 2011-05-10 | 2011-05-10 | Integrated circuit chip package and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101236588A CN102779803A (en) | 2011-05-10 | 2011-05-10 | Integrated circuit chip package and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102779803A true CN102779803A (en) | 2012-11-14 |
Family
ID=47124667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101236588A Pending CN102779803A (en) | 2011-05-10 | 2011-05-10 | Integrated circuit chip package and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102779803A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113257769A (en) * | 2020-02-10 | 2021-08-13 | 台达电子工业股份有限公司 | Packaging structure |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1314708A (en) * | 2000-03-09 | 2001-09-26 | 夏普公司 | Semiconductor device |
| US6448635B1 (en) * | 1999-08-30 | 2002-09-10 | Amkor Technology, Inc. | Surface acoustical wave flip chip |
| US6759752B2 (en) * | 2000-11-06 | 2004-07-06 | St Assembly Test Services Ltd. | Single unit automated assembly of flex enhanced ball grid array packages |
| CN1630066A (en) * | 2003-11-18 | 2005-06-22 | 国际商业机器公司 | High wireability microvia substrate |
| US20090087953A1 (en) * | 2006-10-13 | 2009-04-02 | Hung-Tsun Lin | Manufacturing process of leadframe-based BGA packages |
| US20100127380A1 (en) * | 2008-11-26 | 2010-05-27 | Manolito Galera | Leadframe free leadless array semiconductor packages |
-
2011
- 2011-05-10 CN CN2011101236588A patent/CN102779803A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448635B1 (en) * | 1999-08-30 | 2002-09-10 | Amkor Technology, Inc. | Surface acoustical wave flip chip |
| CN1314708A (en) * | 2000-03-09 | 2001-09-26 | 夏普公司 | Semiconductor device |
| US6759752B2 (en) * | 2000-11-06 | 2004-07-06 | St Assembly Test Services Ltd. | Single unit automated assembly of flex enhanced ball grid array packages |
| CN1630066A (en) * | 2003-11-18 | 2005-06-22 | 国际商业机器公司 | High wireability microvia substrate |
| US20090087953A1 (en) * | 2006-10-13 | 2009-04-02 | Hung-Tsun Lin | Manufacturing process of leadframe-based BGA packages |
| US20100127380A1 (en) * | 2008-11-26 | 2010-05-27 | Manolito Galera | Leadframe free leadless array semiconductor packages |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113257769A (en) * | 2020-02-10 | 2021-08-13 | 台达电子工业股份有限公司 | Packaging structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106158819A (en) | There is the encapsulation base material of horizontal turning circuit | |
| CN1901178B (en) | Relay board and semiconductor device having the relay board | |
| TWI599009B (en) | Semiconductor chip package, semiconductor module, method of fabricating the semiconductor chip package and method of fabricating the semiconductor module | |
| CN102790042B (en) | The stacking structure of semiconductor chip | |
| US9629241B2 (en) | Printed circuit board, ball grid array package and wiring method of printed circuit board | |
| US5990547A (en) | Semiconductor device having plated contacts and method thereof | |
| CN105304584B (en) | Interposer substrate and method of manufacturing the same | |
| CN108054152A (en) | Integrated circuit package structure | |
| US20090179318A1 (en) | Multi-channel stackable semiconductor device and method for fabricating the same, and stacking substrate applied to the semiconductor device | |
| CN103199075A (en) | Wafer level semiconductor encapsulation structure with stacking chips and manufacturing method thereof | |
| JPS63306633A (en) | Film carrier | |
| CN104078435A (en) | Pop packaging structure | |
| CN104051405A (en) | Circuit board structure provided with electronic assemblies in embedded manner and manufacturing method thereof | |
| CN101131978A (en) | Integrated circuit packaging construction and multi-layer conducting wire holder used for it | |
| US20120273931A1 (en) | Integrated circuit chip package and manufacturing method thereof | |
| CN102779803A (en) | Integrated circuit chip package and manufacturing method thereof | |
| CN101764126A (en) | Multi-chip semiconductor package structure without outer leads and lead frame thereof | |
| CN107301954A (en) | Manufacturing method of packaging substrate | |
| CN106298709B (en) | Low cost is fanned out to formula encapsulating structure | |
| CN104966708A (en) | Semiconductor package structure | |
| CN105990259A (en) | Semiconductor memory device | |
| CN104167403A (en) | Lead frame for multi-pin encapsulation | |
| CN101351876A (en) | Strip for integrated circuit packages having a maximized usable area | |
| CN207966971U (en) | General-purpose built-up circuit layer for semiconductor package | |
| CN106876340B (en) | Semiconductor packaging structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20121114 |