CN102779481A - Drive circuit for OLED (Organic Light Emitting Diode) panel - Google Patents
Drive circuit for OLED (Organic Light Emitting Diode) panel Download PDFInfo
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- CN102779481A CN102779481A CN2012103090405A CN201210309040A CN102779481A CN 102779481 A CN102779481 A CN 102779481A CN 2012103090405 A CN2012103090405 A CN 2012103090405A CN 201210309040 A CN201210309040 A CN 201210309040A CN 102779481 A CN102779481 A CN 102779481A
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Abstract
The invention provides a drive circuit for an OLED (Organic Light Emitting Diode) panel. The drive circuit comprises a line buffer and an output buffer. The input end of the line buffer is used for receiving a data voltage signal; the output buffer is electrically connected to the line buffer, a first multiplexer of the output buffer outputs one of the data voltage signal and the reference voltage signal through a first enable signal, and a second multiplexer of the output buffer outputs the other one of the data voltage signal and the reference voltage signal through a second enable signal. The first multiplexer outputs the data voltage signal and the reference voltage signal in a staggered manner, and the second multiplexer outputs the reference voltage signal and the data voltage signal in a staggered manner. With the adoption of the drive circuit provided by the invention, the first multiplexer and the second multiplexer of the output buffer output the data voltage signal and the reference voltage signal in a staggered manner, so that two channels can be used for the charge sharing operation when the first multiplexer and the second multiplexer are switched, since each channel only takes charge of half voltage variation when sharing charges, dynamic loss of the circuit can be reduced effectively, and the work temperature of the circuit can be reduced.
Description
Technical field
The present invention relates to oled panel, relate in particular to the source electrode drive circuit in this oled panel.
Background technology
Current; OLED (Organic Light Emitting Diode) display is owing to have the characteristic of self-lighting; Weight, volume and the power consumption that can save module backlight; Therefore have not only that (operating voltage more can be reduced to 2V to 10V for Liquid Crystal Display, LCD) thinner thickness than LCD.In addition; The visual angle of OLED is wide, picture responds fast (as less than 10ms) and color representation is outstanding than LCD; More have flexible characteristic, make its range of application extremely wide, be used in display panel at present such as hand-held electronic products such as mobile phone, personal digital assistants.
Like what we knew, oled panel be with Organic Light Emitting Diode as luminescence component, and Organic Light Emitting Diode is a kind of assembly that is driven by electric current, its luminosity can change along with the electric current through Organic Light Emitting Diode.Particularly; In traditional oled panel; Its panel luminance is directly proportional with the electric current of the Organic Light Emitting Diode of flowing through; And OLED electric current and corresponding thin film transistor (TFT) (Thin Film Transistor, the Ids that Vgs TFT) (gate source voltage) is produced is relevant, thereby final panel luminance can be expressed as:
T
OLED＝β×I
OLED＝β×k×(V
GS-V
TH)
2
Wherein, β, k are constant, V
GSBe the grid of TFT and the voltage difference between the source electrode, V
THBe the cut-in voltage of TFT, I
OLEDBe the electric current of the Organic Light Emitting Diode of flowing through, T
OLEDBrightness for oled panel.But, owing to have processing procedure difference between a plurality of TFT, causing easily to show uneven phenomenon, a solution of traditional oled panel is to be: at first, discharge the remaining electric charge of OLED and TFT by reset signal; Then, bucking voltage is stored in the pixel capacitance; Then, data voltage is write this pixel capacitance; At last, the electric capacity of being stored by pixel capacitance determines the V of TFT
GS, and then the flow through size of current of OLED of decision, to regulate the brightness of oled panel.Thus; Need export a reference voltage at reseting stage and compensated stage; And need export a data voltage in the data write phase, and cause the output terminal of operational amplifier between reference voltage and data voltage, to switch constantly, cause bigger dynamic loss and higher temperature rise.
In view of this, how designing driving circuit a kind of novelty, that be used for oled panel, to reduce the dynamic loss of Source drive, reduce its working temperature, is a problem needing to be resolved hurrily of person skilled in the industry.
Summary of the invention
To the existing above-mentioned defective of driving circuit that is used for oled panel of the prior art, the invention provides driving circuit a kind of novelty, that be used for oled panel, to reduce the dynamic loss of circuit, reduce its working temperature.
According to one aspect of the present invention, a kind of driving circuit that is used for oled panel is provided, comprising:
One line buffer has an input end, and the input end of said line buffer is in order to receive a data voltage signal; And
One output buffer; Be electrically connected to said line buffer; Said output buffer comprises one first multiplexer and one second multiplexer; Said first multiplexer one of is exported in a said data voltage signal and the reference voltage signal person by one first enable signal, and said second multiplexer is exported another person in said data voltage signal and the said reference voltage signal by one second enable signal
Wherein, said first multiplexer is exported said data voltage signal and said reference voltage signal alternately, and said second multiplexer is exported said reference voltage signal and said data voltage signal alternately.
In one embodiment; Driving circuit also comprises: one the one RS latch, have a set end, a reset terminal and an output terminal, and said set end connects one first asserts signal; Said reset terminal connects one second asserts signal, and said output terminal is exported said first enable signal; And one the 2nd RS latch, having a set end, a reset terminal and an output terminal, said set end connects said second asserts signal, and said reset terminal connects said first asserts signal, and said output terminal is exported said second enable signal.
In one embodiment, first asserts signal and second asserts signal are periodic signal, and have a preset delay time between first asserts signal and second asserts signal.
In one embodiment, driving circuit also comprises a clock signal, and said first asserts signal is corresponding to the negative edge of said clock signal, and said second asserts signal is corresponding to said rising edge of clock signal.Further, when first asserts signal is negative edge, this data voltage signal of first multiplexer output, this reference voltage signal of second multiplexer output.When second asserts signal is negative edge, this reference voltage signal of first multiplexer output, this data voltage signal of second multiplexer output.
In one embodiment, this data voltage signal is more than or equal to this reference voltage signal.
According to another aspect of the present invention, a kind of driving circuit that is used for oled panel is provided, comprising:
Time schedule controller, this time schedule controller comprises a plurality of Frames, and each data frame dividing is one first subframe and one second subframe, and said first subframe is in order to import one first data voltage signal, and said second subframe is in order to import one second data voltage signal;
One output buffer; Be electrically connected to said time schedule controller; Said output buffer comprises one first multiplexer and one second multiplexer; Said first multiplexer one of is exported in said first data voltage signal and the reference voltage signal person by one first enable signal, and said second multiplexer is exported another person in said second data voltage signal and the said reference voltage signal by one second enable signal
Wherein, said first multiplexer is exported said first data voltage signal and said reference voltage signal alternately, and said second multiplexer is exported said reference voltage signal and said second data voltage signal alternately.
In one embodiment; This driving circuit also comprises: one the one RS latch, have a set end, a reset terminal and an output terminal, and said set end connects one first asserts signal; Said reset terminal connects one second asserts signal, and said output terminal is exported said first enable signal; And one the 2nd RS latch, having a set end, a reset terminal and an output terminal, said set end connects said second asserts signal, and said reset terminal connects said first asserts signal, and said output terminal is exported said second enable signal.
In one embodiment, first asserts signal and second asserts signal are periodic signal, and have a preset delay time between first asserts signal and second asserts signal.
Adopt the driving circuit that is used for oled panel of the present invention; One of come in output data voltage signal and the reference voltage signal person by first multiplexer in the output buffer; And second multiplexer come another person in output data voltage signal and the reference voltage signal; Make data voltage signal and reference voltage signal can adopt two passages to carry out the electric charge sharing operation when switching; Because each passage only was responsible for half the change in voltage when electric charge was shared, thereby can reduce the dynamic loss of circuit effectively, and then reduce the working temperature of circuit.
Description of drawings
The reader with reference to advantages after the embodiment of the present invention, will become apparent various aspects of the present invention.Wherein,
Fig. 1 illustrates the structural representation that is used for the driving circuit of oled panel of the prior art;
Fig. 2 illustrates according to an embodiment of the present invention, is used for the structural representation of the driving circuit of oled panel;
Fig. 3 (a) illustrates in the driving circuit of Fig. 2, is used to control the circuit diagram of first enable signal of first multiplexer;
Fig. 3 (b) illustrates in the driving circuit of Fig. 2, is used to control the circuit diagram of second enable signal of second multiplexer;
Fig. 4 illustrates in the driving circuit of Fig. 2, the odd chanel of clock signal, first asserts signal, second asserts signal, line buffer and the signal waveform synoptic diagram of even-numbered channels; And
Fig. 5 illustrates in the driving circuit of Fig. 2, the data waveform synoptic diagram of the strange passage amplifier of clock signal, first asserts signal, second asserts signal, output buffer and the output of even passage amplifier.
Embodiment
For technology contents that the application is disclosed is more detailed and complete, can be with reference to accompanying drawing and following various specific embodiments of the present invention, identical mark is represented same or analogous assembly in the accompanying drawing.Yet the embodiment that those of ordinary skill in the art should be appreciated that hereinafter to be provided is used for limiting the scope that the present invention is contained.In addition, accompanying drawing only is used for schematically explaining, does not draw according to its life size.
With reference to the accompanying drawings, the embodiment of various aspects of the present invention is done further to describe in detail.
Fig. 1 illustrates the structural representation of the driving circuit of the OLED of being used for of the prior art (Organic Light Emitting Diode, Organic Light Emitting Diode) panel.With reference to Fig. 1, the traditional driving circuit comprises source electrode driver 10 and image element circuit 20 two parts.Wherein, source electrode driver 10 comprises multiplexer 101 (MUX) and operational amplifier 103 (OP), and the input end of operational amplifier 103 is electrically connected to the output terminal of multiplexer 101.In addition, multiplexer 101 also comprises two input ends, and an input end wherein is used to receive a data voltage signal Vdata, and another input end is used to receive a reference voltage signal Vref.
Usually, data voltage signal Vdata is more than or equal to reference voltage signal, and when multiplexer 101 was selected data voltage signal as the output signal, 103 pairs of these data voltage signal of operational amplifier were handled; When multiplexer 101 was selected reference voltage signal as the output signal, 103 pairs of these reference voltage signals of operational amplifier were handled.As shown in Figure 1, the data module 201 of image element circuit 20 is used for data voltage signal Vdata after handling or reference voltage signal Vref are delivered to the thin film transistor (TFT) of back level, and then produces electric current I
OLEDAs previously mentioned; In traditional circuit framework; In reseting stage and compensated stage, image element circuit 20 needs to produce a reference voltage, and need produce a data voltage in the data write phase; Will cause the output terminal of operational amplifier 103 constantly between reference voltage Vref and data voltage Vdata, to switch like this, thereby cause bigger dynamic loss and higher temperature rise.
In order to solve the dynamic loss problem in the existing driving circuit effectively, Fig. 2 illustrates according to an embodiment of the present invention, is used for the structural representation of the driving circuit of oled panel.
With reference to Fig. 2, in this embodiment, the driving circuit that is used for oled panel comprises a line buffer 30 and an output buffer 40.Wherein, line buffer 30 has an input end, in order to receive a data voltage signal Data.Output buffer 40 is electrically connected to line buffer 30.Output buffer 40 comprises one first multiplexer 401, one first operational amplifier 403, one second multiplexer 405 and one second operational amplifier 407; Wherein, First operational amplifier 403 is electrically connected to the output terminal of first multiplexer 401, and second operational amplifier 407 is electrically connected to the output terminal of second multiplexer 405.In addition, the output terminal of first operational amplifier 403 is connected to a pixel storage capacitor Cst via a switch, and the output terminal of second operational amplifier 407 is connected to another pixel storage capacitor Cst via another switch.This data voltage signal of output terminal output when first operational amplifier 403; When the output terminal of second operational amplifier 407 is exported this reference voltage signal; Opening or conducting of control respective switch makes circuit working share (Charge Sharing, CS) state in electric charge.
It is pointed out that the pulse number according to clock signal, line buffer 30 can comprise an odd number output channel and an even number output channel accordingly.For example, when the clock signal is negative edge, produce one first asserts signal STB1, by this first asserts signal STB1, this data voltage signal of the odd number output channel of line buffer 30 output (is labeled as V
Data_o, corresponding odd data); When the clock signal is rising edge, produce one second asserts signal STB2, by this second asserts signal STB2, this data voltage signal of the even number output channel of line buffer 30 output (is labeled as V
Data_e, corresponding even data).Those skilled in the art is to be understood that; The above-mentioned schematic example that is merely source electrode drive circuit of the present invention, in other embodiment, also can be when clock signal be rising edge; Produce asserts signal STB1, and export this data voltage signal by the odd number output channel; And when clock signal is negative edge, produce asserts signal STB2, and export this data voltage signal by the even number output channel.
In one embodiment, first multiplexer 401 is exported this data voltage signal V alternately
Data_oWith this reference voltage signal V
Ref, second multiplexer 405 is exported this data voltage signal V alternately
Data_eWith this reference voltage signal V
RefIn addition, first multiplexer 401 also can comprise a control end Sel_o, and second multiplexer 405 also can comprise a control end Sel_e, comes to control respectively the output signal of first multiplexer 401 and 405 through control end Sel_o and Sel_e.Specifically can combine Fig. 3 (a) and Fig. 3 (b) of back to be elaborated.
In one embodiment, this driving circuit also comprises a time schedule controller and an output buffer.The exportable a plurality of Frames of this time schedule controller, each data frame dividing are one first subframe and one second subframe, and first subframe is in order to corresponding one first data voltage signal, and second subframe is in order to corresponding one second data voltage signal.For example; The pulse width of first data voltage signal and second data voltage signal is all identical with amplitude; In the corresponding input data voltage signal of the preceding field of Frame to this first multiplexer 401, and in the corresponding input data voltage signal of the back field of Frame to this second multiplexer 405.First multiplexer 401 one of is exported in this data voltage signal and this reference voltage signal the person according to one of input control end Sel_o first control signal (or being called enable signal), and second multiplexer 405 is exported another person in this data voltage signal and this reference voltage signal according to one of input control end Sel_e second control signal (or being called enable signal).That is to say, when first multiplexer, 401 output data voltage signals, second multiplexer, 405 output reference voltage signals, when first multiplexer, 401 output reference voltage signals, second multiplexer, 405 output data voltage signals.
Fig. 3 (a) illustrates in the driving circuit of Fig. 2, is used to control the circuit diagram of first enable signal of first multiplexer, and Fig. 3 (b) illustrates in the driving circuit of Fig. 2, is used to control the circuit diagram of second enable signal of second multiplexer.
With reference to Fig. 3 (a) and Fig. 3 (b), in this embodiment, driving circuit also comprises RS latch 501 (Rest-Set latch, or be called the SR latch) and RS latch 503.Wherein, RS latch 501 is corresponding to first multiplexer 401, and RS latch 503 is corresponding to second multiplexer 403.
Particularly, RS latch 501 has a set end set, a reset terminal reset and an output terminal.This set end set connects one first asserts signal STB_1, and this reset terminal reset connects one second asserts signal STB2, this this first enable signal of output terminal output Sel_o.Similarly, RS latch 503 has a set end set, a reset terminal reset and an output terminal.This set end set connects one first asserts signal STB2, and this reset terminal reset connects one second asserts signal STB1, this this second enable signal of output terminal output Sel_e.For example, when asserts signal STB1 is negative edge, first multiplexer, 401 output data voltage signals, second multiplexer, 403 output reference voltage signals; When asserts signal STB2 is negative edge, first multiplexer, 401 output reference voltage signals, second multiplexer, 403 output data voltage signals, as shown in Figure 4.
In one embodiment, n/2 latch (latch) can be set as aforesaid line buffer 30 before the position quasi displacement circuit in the driving circuit.In the operation, when asserts signal STB1 was rising edge, the latch in the driving circuit was delivered to aforementioned output buffer 40 via position quasi displacement circuit with odd data, and even data is delivered to aforesaid line buffer 30.When asserts signal STB1 is negative edge, the data voltage signal of the corresponding odd data of first operational amplifier, 403 outputs in the aforementioned output buffer 40, the corresponding reference voltage signal of second operational amplifier, 407 outputs in the aforementioned output buffer 40.
In addition; When asserts signal STB2 is rising edge; Line buffer 30 is delivered to aforementioned output buffer 40 via position quasi displacement circuit with even data; And when asserts signal STB2 is negative edge, the data voltage signal of the corresponding even data of second operational amplifier, 407 outputs in the output buffer 40, the corresponding reference voltage signal of first operational amplifier, 403 outputs.
On the other hand; Aforementioned output buffer 40 also can be arranged in the time schedule controller (Tcon); In time schedule controller, odd data and even data are arranged or be configured to data again, and odd data and even data export respectively at different time, data rate is phase strain twice also.
For instance; During single picture (frame), export odd data; And when asserts signal STB 1 was rising edge, latch was delivered to output buffer 40 with odd data, and when asserts signal STB1 is negative edge; The data voltage signal of the corresponding odd data of first operational amplifier, 403 outputs in the output buffer 40, the corresponding reference voltage signal of second operational amplifier, 407 outputs in the aforementioned output buffer 40.Then; During same picture (frame), export even data; And when asserts signal STB2 was rising edge, latch was delivered to output buffer 40 with even data, and when asserts signal STB2 is negative edge; The data voltage signal of the corresponding even data of second operational amplifier, 407 outputs in the output buffer 40, the corresponding reference voltage signal of first operational amplifier, 403 outputs.
In one embodiment, the first asserts signal STB1 and the second asserts signal STB2 are periodic signal, and have a preset delay time between the first asserts signal STB1 and the second asserts signal STB2.For example, this timing period is corresponding to the pulse width of clock signal, and is as shown in Figure 5.
Adopt the driving circuit that is used for oled panel of the present invention; One of come in output data voltage signal and the reference voltage signal person by first multiplexer in the output buffer; And second multiplexer come another person in output data voltage signal and the reference voltage signal; Make data voltage signal and reference voltage signal can adopt two passages to carry out the electric charge sharing operation when switching; Because each passage only was responsible for half the change in voltage when electric charge was shared, thereby can reduce the dynamic loss of circuit effectively, and then reduce the working temperature of circuit.
In the preceding text, illustrate and describe embodiment of the present invention.But those skilled in the art can understand, and under situation without departing from the spirit and scope of the present invention, can also specific embodiments of the invention do various changes and replacement.These changes and replacement all drop in claims of the present invention institute restricted portion.
Claims (10)
1. driving circuit that is used for OLED (Organic Light Emitting Diode, Organic Light Emitting Diode) panel is characterized in that said driving circuit comprises:
One line buffer has an input end, and the input end of said line buffer is in order to receive a data voltage signal; And
One output buffer; Be electrically connected to said line buffer; Said output buffer comprises one first multiplexer and one second multiplexer; Said first multiplexer one of is exported in a said data voltage signal and the reference voltage signal person by one first enable signal, and said second multiplexer is exported another person in said data voltage signal and the said reference voltage signal by one second enable signal
Wherein, said first multiplexer is exported said data voltage signal and said reference voltage signal alternately, and said second multiplexer is exported said reference voltage signal and said data voltage signal alternately.
2. driving circuit according to claim 1 is characterized in that, said driving circuit also comprises:
One the one RS latch has a set end, a reset terminal and an output terminal, and said set end connects one first asserts signal, and said reset terminal connects one second asserts signal, and said output terminal is exported said first enable signal; And
One the 2nd RS latch has a set end, a reset terminal and an output terminal, and said set end connects said second asserts signal, and said reset terminal connects said first asserts signal, and said output terminal is exported said second enable signal.
3. driving circuit according to claim 2 is characterized in that, said first asserts signal and said second asserts signal are periodic signal, and has a preset delay time between said first asserts signal and said second asserts signal.
4. driving circuit according to claim 3 is characterized in that, said driving circuit also comprises a clock signal, and said first asserts signal is corresponding to the negative edge of said clock signal, and said second asserts signal is corresponding to said rising edge of clock signal.
5. driving circuit according to claim 4 is characterized in that, when said first asserts signal was negative edge, said first multiplexer was exported said data voltage signal, and said second multiplexer is exported said reference voltage signal.
6. driving circuit according to claim 4 is characterized in that, when said second asserts signal was negative edge, said first multiplexer was exported said reference voltage signal, and said second multiplexer is exported said data voltage signal.
7. according to claim 5 or 6 described driving circuits, it is characterized in that said data voltage signal is more than or equal to said reference voltage signal.
8. driving circuit that is used for OLED (Organic Light Emitting Diode, Organic Light Emitting Diode) panel is characterized in that said driving circuit comprises:
Time schedule controller; Said time schedule controller comprises a plurality of Frames; Each data frame dividing is one first subframe and one second subframe, and said first subframe is in order to import one first data voltage signal, and said second subframe is in order to import one second data voltage signal;
One output buffer; Be electrically connected to said time schedule controller; Said output buffer comprises one first multiplexer and one second multiplexer; Said first multiplexer one of is exported in said first data voltage signal and the reference voltage signal person by one first enable signal, and said second multiplexer is exported another person in said second data voltage signal and the said reference voltage signal by one second enable signal
Wherein, said first multiplexer is exported said first data voltage signal and said reference voltage signal alternately, and said second multiplexer is exported said reference voltage signal and said second data voltage signal alternately.
9. driving circuit according to claim 8 is characterized in that, said driving circuit also comprises:
One the one RS latch has a set end, a reset terminal and an output terminal, and said set end connects one first asserts signal, and said reset terminal connects one second asserts signal, and said output terminal is exported said first enable signal; And
One the 2nd RS latch has a set end, a reset terminal and an output terminal, and said set end connects said second asserts signal, and said reset terminal connects said first asserts signal, and said output terminal is exported said second enable signal.
10. driving circuit according to claim 8 is characterized in that, said first asserts signal and said second asserts signal are periodic signal, and has a preset delay time between said first asserts signal and said second asserts signal.
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|---|---|---|---|
| CN2012103090405A CN102779481A (en) | 2012-08-27 | 2012-08-27 | Drive circuit for OLED (Organic Light Emitting Diode) panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105099432A (en) * | 2014-05-19 | 2015-11-25 | 奇景光电股份有限公司 | Output buffer |
| CN105814823A (en) * | 2013-12-12 | 2016-07-27 | 哉英电子股份有限公司 | Signal multiplexer |
| CN107293259A (en) * | 2016-03-29 | 2017-10-24 | 乐金显示有限公司 | Organic light emitting diode display |
| CN109493807A (en) * | 2017-09-13 | 2019-03-19 | 乐金显示有限公司 | Organic light emitting display |
| CN110491344A (en) * | 2019-07-30 | 2019-11-22 | 武汉华星光电半导体显示技术有限公司 | For driving the driving chip and display product of display panel |
| CN111432520A (en) * | 2020-04-02 | 2020-07-17 | 广东晟合技术有限公司 | Balancing method for driving O L ED panel with low power consumption |
| CN111698814A (en) * | 2020-07-02 | 2020-09-22 | 东莞市华彩威科技有限公司 | LED driving circuit with double-line input and output and transmission method thereof |
| TWI771774B (en) * | 2020-10-20 | 2022-07-21 | 大陸商北京集創北方科技股份有限公司 | Bias voltage compensation circuit, OLED display device and information processing device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105814823A (en) * | 2013-12-12 | 2016-07-27 | 哉英电子股份有限公司 | Signal multiplexer |
| US10574228B2 (en) | 2013-12-12 | 2020-02-25 | Thine Electronics, Inc. | Signal multiplexer |
| CN105814823B (en) * | 2013-12-12 | 2018-12-04 | 哉英电子股份有限公司 | signal multiplexing device |
| CN105099432B (en) * | 2014-05-19 | 2019-04-30 | 奇景光电股份有限公司 | Output buffer |
| CN105099432A (en) * | 2014-05-19 | 2015-11-25 | 奇景光电股份有限公司 | Output buffer |
| CN107293259B (en) * | 2016-03-29 | 2019-07-12 | 乐金显示有限公司 | Organic light emitting diode display |
| CN107293259A (en) * | 2016-03-29 | 2017-10-24 | 乐金显示有限公司 | Organic light emitting diode display |
| CN109493807A (en) * | 2017-09-13 | 2019-03-19 | 乐金显示有限公司 | Organic light emitting display |
| CN109493807B (en) * | 2017-09-13 | 2022-05-10 | 乐金显示有限公司 | Organic light emitting display |
| CN110491344A (en) * | 2019-07-30 | 2019-11-22 | 武汉华星光电半导体显示技术有限公司 | For driving the driving chip and display product of display panel |
| CN110491344B (en) * | 2019-07-30 | 2020-11-06 | 武汉华星光电半导体显示技术有限公司 | Driving chip for driving display panel and display product |
| CN111432520A (en) * | 2020-04-02 | 2020-07-17 | 广东晟合技术有限公司 | Balancing method for driving O L ED panel with low power consumption |
| CN111432520B (en) * | 2020-04-02 | 2022-04-19 | 晟合微电子(肇庆)有限公司 | Equalization method for driving OLED panel with low power consumption |
| CN111698814A (en) * | 2020-07-02 | 2020-09-22 | 东莞市华彩威科技有限公司 | LED driving circuit with double-line input and output and transmission method thereof |
| TWI771774B (en) * | 2020-10-20 | 2022-07-21 | 大陸商北京集創北方科技股份有限公司 | Bias voltage compensation circuit, OLED display device and information processing device |
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Application publication date: 20121114 |