CN102759974A - Computer mainboard - Google Patents
Computer mainboard Download PDFInfo
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- CN102759974A CN102759974A CN2011101052777A CN201110105277A CN102759974A CN 102759974 A CN102759974 A CN 102759974A CN 2011101052777 A CN2011101052777 A CN 2011101052777A CN 201110105277 A CN201110105277 A CN 201110105277A CN 102759974 A CN102759974 A CN 102759974A
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- negative pole
- weld
- row
- layer ceramic
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Abstract
The invention provides a computer mainboard, comprising a chip holder, a power layer, a ground layer and a plurality of chip multi-layer ceramic capacitors (MLCC). The power layer comprises a current path area by which current can flows into the chip holder. The plurality of MLCCs are distributed into an array and arranged on the chip holder; each MLCC comprises an anode and a cathode; each anode is connected to the current path area through at least one power via hole, each cathode is connected to the ground layer through at least one grounding via hole. Power via holes corresponding to each column of MLCCs arranged in a current inflow direction are arranged into one column in the current inflow direction, and the corresponding grounding via holes are also arranged into one column in the current inflow direction. In this way, for each column of MLCCs, the current flows into the downstream power via holes along a channel formed between one column of power via holes and one column of grounding via holes, thus charging the MLCCs located at downstream part of the current in the column of MLCCs; therefore, the performance of fast transient response of the chips is improved.
Description
Technical field
The present invention relates to a kind of computer motherboard, particularly a kind of have sheet type multi-layer ceramic capacitance (multi-layer ceramic capacitor, MLCC) computer motherboard of array.
Background technology
The central processing unit of computer motherboard (central processing unit; CPU) socket (socket) is provided with the MLCC array usually; Be used for when the CPU operate as normal, charging and rapid discharge when CPU fast transient response (transit response), provide the response of CPU fast transient required of short duration high voltage.The MLCC array is arranged on the current path of CPU socket, and the positive pole of each MLCC and negative pole are connected with ground plane with the bus plane of computer motherboard through via hole (via hole) respectively.The bus plane of computer motherboard is destroyed by via hole; Therefore; If the MLCC array is put unreasonable; The via hole of MLCC that is positioned at the electric current inflow direction front (the electric current upper reaches) of CPU socket will hinder the via hole of the MLCC of current direction back (electric current downstream), and just to hinder the flow direction downstream the same like being in stone in the current, cause the MLCC of back to charge and be affected; Respond required of short duration high-tension efficient thereby influence whole M LCC array supply CPU fast transient, the fast transient response performance of CPU is poor.
Summary of the invention
In view of this, be necessary to provide a kind of computer motherboard that improves chip fast transient response performance.
A kind of computer motherboard, it comprises a chip carrier, a bus plane, a ground plane and a plurality of MLCC.This bus plane comprises that a power supply stream flows into the current path district of this chip carrier.These a plurality of MLCC are array distribution and are arranged on this chip carrier, and each MLCC comprises a positive pole and a negative pole.Each positive pole is connected to this current path district through at least one power vias.Each negative pole is connected to this ground plane through at least one ground connection via hole.Every row are arranged to row along the corresponding power vias of the MLCC of electric current inflow direction setting along the electric current inflow direction, and corresponding ground connection via hole also is arranged to row along the electric current inflow direction.
So, for every row MLCC, electric current can be listed as the power vias that the passage that forms between the ground connection via hole flows to the electric current downstream swimmingly with corresponding one along a corresponding row power vias, for being positioned at the MLCC charging in electric current downstream among these row MLCC.No matter permutation MLCC is positioned at the upstream and downstream of electric current, responds required of short duration high voltage for the chip on this chip carrier provides fast transient effectively thereby can charge effectively, thereby improves the performance of chip fast transient response.
Description of drawings
Fig. 1 is the partial top view of the computer motherboard of preferred embodiments of the present invention.
Fig. 2 is the part sectioned view of the computer motherboard of Fig. 1 along the II-II direction.
The main element symbol description
| |
10 |
| |
100 |
| Weld pad is right | 102 |
| Anodal |
104 |
| The negative |
106 |
| |
200 |
| The |
202 |
| |
300 |
| |
400 |
| Anodal | 402 |
| |
404 |
| |
500 |
| The ground connection via |
600 |
Following embodiment will combine above-mentioned accompanying drawing to further specify the present invention.
Embodiment
See also Fig. 1 and Fig. 2, the computer motherboard 10 of preferred embodiments of the present invention comprises a chip carrier 100, bus plane 200, a ground plane 300 and an a plurality of MLCC 400.This bus plane 200 comprises that a power supply stream flows into the current path district 202 of this chip carrier 100.These a plurality of MLCC 400 are array distribution and are arranged on this chip carrier 100, and each MLCC 400 comprises a positive pole 402 and a negative pole 404.Each anodal 402 is connected to this current path district 202 through at least one power vias 500.Each negative pole 404 is connected to this ground plane 300 through at least one ground connection via hole 600.Every row are arranged to row along the MLCC 400 corresponding power vias 500 that electric current inflow direction (in Fig. 1, representing with dotted arrow) is provided with along the electric current inflow direction, and corresponding ground connection via hole 600 also is arranged to row along the electric current inflow direction.
So; For every row MLCC 400; Electric current can be listed as the power vias 500 that passage between the ground connection via hole 600 flows to the electric current downstream swimmingly along a corresponding row power vias 500 and with corresponding one, is that the MLCC 400 that is positioned at the electric current downstream among these row MLCC 400 charges.Permutation MLCC 400, no matter are positioned at the electric current upstream and downstream, thereby can charge effectively effectively for the chip on this chip carrier 100 (figure does not show) provides the fast transient response required of short duration high voltage, thereby improve the performance of chip fast transient response.
Particularly, this chip carrier 100 can be to be used to be installed with central processing unit (central processing unit, CPU socket CPU) are provided with a plurality of weld pads to 102.Each weld pad is used for the corresponding MLCC 400 of welding to 102, comprises an anodal weld pad 104 and a negative pole weld pad 106 that is used to weld a corresponding negative pole 404 that is used to weld a corresponding positive pole 402.Each anodal 402 at least one corresponding power vias 500 connects corresponding anodal weld pad 104 to this bus plane 200.Each negative pole 404 at least one corresponding ground connection via hole 600 connects corresponding negative pole weld pad 106 to this ground plane 300.So, each MLCC 400 is welded to a corresponding weld pad to after 102, its anodal 402 and negative pole 404 be connected to this bus plane 200 and this ground plane 300 through at least one power vias 500 and at least one ground connection via hole 600 of correspondence respectively.Every row MLCC 400 corresponding a plurality of anodal weld pads 104 link to each other and are provided with, and corresponding a plurality of negative pole weld pads 106 also link to each other and are provided with.So, can improve the path that current direction is positioned at the power vias 500 in electric current downstream.
This bus plane 200 is arranged between this chip carrier 100 and this ground plane 300, and this ground connection via hole 600 runs through this bus plane 200.The negative pole 404 shared row ground connection via holes 600 of adjacent two row MLCC 400 are connected to this ground plane 300.Particularly, the corresponding two row negative pole weld pads 106 of adjacent two row MLCC 400 can adjacent and continuous setting, a shared row ground connection via hole 600.So, can reduce destruction, improve the path that current direction is positioned at the power vias 500 in electric current downstream this bus plane 200.
Be appreciated that; Be provided with insulation course 700 between this chip carrier 100, this bus plane 200 and this ground plane 300; Therefore, the anodal weld pad 104 on this chip carrier 100 and this negative pole weld pad 106 just need to be connected with this bus plane 200 and this ground plane 300 respectively through this power vias 500 and this ground connection via hole 600.In the practical application, this computer motherboard 10 can also include signals layer or more bus plane (figure does not show).
In this embodiment; These a plurality of MLCC 400 are arranged in three row; Each positive pole 402 is connected with this bus plane 200 through two power vias 500; Each negative pole 404 is connected with this ground plane 300 through two ground connection via holes 600, the negative pole 404 shared row ground connection via holes 600 of the two row MLCC 400 on the right.Certainly, the number of these a plurality of MLCC 400, arrange and be not limited to this embodiment, can look specific requirement and decide with the bind mode of this bus plane 200 and this ground plane.
In a word; Those skilled in the art will be appreciated that; Above embodiment only is to be used for explaining the present invention; And be not to be used as qualification of the present invention, as long as within connotation scope of the present invention, appropriate change that above embodiment did is all dropped within the scope that the present invention requires to protect with changing.
Claims (4)
1. a computer motherboard is characterized in that comprising a chip carrier, a bus plane, a ground plane and a plurality of sheet type multi-layer ceramic capacitance; This bus plane comprises that a power supply stream flows into the current path district of this chip carrier; These a plurality of sheet type multi-layer ceramic capacitances are array distribution and are arranged on this chip carrier, and each sheet type multi-layer ceramic capacitance comprises a positive pole and a negative pole; Each positive pole is connected to this current path district through at least one power vias; Each negative pole is connected to this ground plane through at least one ground connection via hole; Every row are arranged to row along the corresponding power vias of the sheet type multi-layer ceramic capacitance of electric current inflow direction setting along the electric current inflow direction, and corresponding ground connection via hole also is arranged to row along the electric current inflow direction.
2. computer motherboard as claimed in claim 1 is characterized in that it is right that this chip carrier is provided with a plurality of weld pads; Each weld pad comprises an anodal weld pad and a negative pole weld pad that is used to weld a corresponding negative pole that is used to weld a corresponding positive pole to being used for the corresponding sheet type multi-layer ceramic capacitance of welding; Each anodal at least one corresponding power vias connects corresponding anodal weld pad to this current path district; At least one ground connection via hole that each negative pole is corresponding connects corresponding negative pole weld pad to this ground plane; The a plurality of anodal weld pad that every row sheet type multi-layer ceramic capacitance is corresponding links to each other and is provided with, and corresponding a plurality of negative pole weld pads also link to each other and are provided with.
3. computer motherboard as claimed in claim 1 is characterized in that, this bus plane is arranged between this chip carrier and this ground plane, and this ground connection via hole runs through this bus plane; The shared row ground connection via hole of the negative pole of adjacent two row sheet type multi-layer ceramic capacitances is connected to this ground plane.
4. computer motherboard as claimed in claim 3 is characterized in that it is right that this chip carrier is provided with a plurality of weld pads; Each weld pad comprises an anodal weld pad and a negative pole weld pad that is used to weld a corresponding negative pole that is used to weld a corresponding positive pole to being used for the corresponding sheet type multi-layer ceramic capacitance of welding; Adjacent and the continuous setting of two row negative pole weld pads that adjacent two row sheet type multi-layer ceramic capacitances are corresponding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101052777A CN102759974A (en) | 2011-04-26 | 2011-04-26 | Computer mainboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101052777A CN102759974A (en) | 2011-04-26 | 2011-04-26 | Computer mainboard |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102759974A true CN102759974A (en) | 2012-10-31 |
Family
ID=47054448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011101052777A Pending CN102759974A (en) | 2011-04-26 | 2011-04-26 | Computer mainboard |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102759974A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115500008A (en) * | 2022-08-30 | 2022-12-20 | 超聚变数字技术有限公司 | Computing node and computing equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020195700A1 (en) * | 2002-02-01 | 2002-12-26 | Intel Corporation | Electronic assembly with vertically connected capacitors and manufacturing method |
| US20060225916A1 (en) * | 2004-09-14 | 2006-10-12 | Jerimy Nelson | Routing vias in a substrate from bypass capacitor pads |
| US20100290173A1 (en) * | 2009-05-12 | 2010-11-18 | Jung Rag Yoon | Multi layer ceramic capacitor and DC-Link capacitor module using the same |
-
2011
- 2011-04-26 CN CN2011101052777A patent/CN102759974A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020195700A1 (en) * | 2002-02-01 | 2002-12-26 | Intel Corporation | Electronic assembly with vertically connected capacitors and manufacturing method |
| US20060225916A1 (en) * | 2004-09-14 | 2006-10-12 | Jerimy Nelson | Routing vias in a substrate from bypass capacitor pads |
| US20100290173A1 (en) * | 2009-05-12 | 2010-11-18 | Jung Rag Yoon | Multi layer ceramic capacitor and DC-Link capacitor module using the same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115500008A (en) * | 2022-08-30 | 2022-12-20 | 超聚变数字技术有限公司 | Computing node and computing equipment |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20121031 |