CN102752081A - Parallel cyclic redundancy check method and device in high-speed Ethernet - Google Patents

Abstract

The invention discloses a parallel cyclic redundancy check method in a high-speed Ethernet, which is used in a cyclic redundancy check (CRC) module to carry out parallel cyclic redundancy check. The parallel cyclic redundancy check method comprises the following steps of: at first, carrying out bit width matching on data frames according to a pre-set bit width; then sending matched data flow to the universal bit width pre-setting parallel cyclic redundancy check module and calculating a check value; and finally, carrying out inverse operation on the check value obtained through the calculation according to the last effective data bit, so as to obtain a final CRC result. The invention further discloses a parallel cyclic redundancy check device, comprising the CRC module for pre-setting the bit width, a register and a last data inverse operation module. The device provided by the invention has a simple structure. With the adoption of the CRC module with the certain bit width, the high-speed parallel data CRC can be realized. Furthermore, the method provided by the invention is applicable to the high-speed parallel data CRC with the random bit width and has a wide application range.

Description

Parallel cyclic redundancy check method and device in a kind of Fast Ethernet

Technical field

The present invention relates to communication and computer data transmission error control technical field, particularly relate to parallel CRC computational methods in a kind of Fast Ethernet communication.

Background technology

In data communication, generally with data packet transmission, carry out error control coding, to guarantee the correctness of transmission in additional frame verification sequence (FCS, Frame Check Sequence) thereafter.In the realization of Frame Check Sequence, CRC CRC (Cyclic RedundancyCode) has obtained extensive use with its high efficiency, high-performance, is a kind of method that improves data communication reliability that generally adopts in the present data transmission procedure.

In the real time high-speed communication system, tradition is based on the generation of the serial CRC of position and the requirement that checking circuit can not satisfy information processing high speed, parallelization for a long time.Must adopt parallel CRC check to improve the verification speed of CRC; Most of Parallel CRC verification computational methods all are the generator polynomials through CRC; Derive check value previous state and next state the matrix operation relation; Carry out N time matrix operation and can draw the relation of N state and the 0th state, promptly can realize the parallel processing of N position, satisfy the demand of high speed bandwidth.

Inner in data communication system; The Ethernet data bag is generally all huger; Need be divided into N and clap parallel transmission, generally with chip or FPGA, the engineer generally can reach the purpose that the rational bit wide of frequency configuration reaches raising chip processing speed according to chip or FPGA in inner parallel processing.Because the length of Ethernet data bag is at random, the data length that causes last bat so also is unfixing.With the 10Gbps Fast Ethernet is example, and data bit width adopts 64 bits just can reach processing requirements.Calculate crc value this moment, adopts 64 CRC32 parallel computation circuit, claps length for last and do not fix, and more than 1 ~ 7 kind of situation arranged; Valid data figure place according to last bat when therefore carrying out CRC check uses 8,16,24,32; 40,48,56,64 Parallel CRC 32 verification modules are calculated; Often will take many logical resources, sequential requires also to have satisfied not, and this also becomes the bottleneck in the Fast Ethernet system.So the necessary additive method that finds can be simplified its processing, preferably only be suitable for a kind of verification unit of bit wide.

Publication number is Parallel CRC 32 methods of calibration and the device that the Chinese invention patent application of CN 102158316A discloses a kind of 64bit bit wide; Frame is carried out the bit wide coupling with 64bit; If judge the not enough 64bit of Frame; Then low 8i Bit data filling bit in the preset 56bit data is added to the afterbody of Frame; Obtain the 64bit data, adopt 64 CRC32 modules to calculate to it then, then that the check results that obtains is corresponding with filling bit CRC check value compares to be judged.This similar method all is to adopt completion method, compare then and carry out CRC check, but these class methods all can only be fit to fixing 64 CRC check, narrow application range after design.

Summary of the invention

The purpose of this invention is to provide a kind of parallel cyclic redundancy check method and device, take more logical resource and the narrow problem of the scope of application to solve in the prior art.

Parallel cyclic redundancy check method in a kind of Fast Ethernet is applied to the CRC that walks abreast of cyclic redundancy check (CRC) module, comprises;

Step 1, Frame is carried out the bit wide coupling with preset bit wide;

Step 2, the data flow after will mating are sent into the parallel CRC module of general preset bit wide and are calculated check value;

Step 3, according to the valid data figure place of last bat, the check value that step 2 is calculated carries out inverse operation, obtains final CRC check result.

Further, said step 3 comprises:

Read the valid data figure place information of last bat, the number of times of decision inverse operation;

Extract the preceding 8 bit invalid datas of current state;

Carry out 8 inverse operations;

If the inverse operation number of times is not intact, continue to extract the preceding 8 bit invalid datas of current state, carry out inverse operation, up to accomplishing inverse operation, obtain final CRC check result.

Further, said preset bit wide is 64, and the parallel CRC module of said preset bit wide is 64 CRC32 modules.

Further, said 8 inverse operation formula are:

$C(i-8)={\mathrm{<figure-callout\; id="8"\; label="H"\; filenames="HDA00001844829200012.png"\; state="\{\{state\}\}">H</figure-callout>}}^8\&CircleTimes;C\left(i\right)\&CirclePlus;\left[\begin{array}{cccc}{\mathrm{<figure-callout\; id="7"\; label="H"\; filenames="HDA00001844829200012.png"\; state="\{\{state\}\}">H</figure-callout>}}^7\&CircleTimes;U& {\mathrm{<figure-callout\; id="6"\; label="H"\; filenames="HDA00001844829200012.png"\; state="\{\{state\}\}">H</figure-callout>}}^6\&CircleTimes;U& \&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;& U\end{array}\right]\&CircleTimes;D\left(8\right),$

Wherein C (i) is a CRC32 state matrix under the current state i, and H is an adjacent states inverse operation check matrix, and U is an adjoint matrix, and D (8) is preceding 8 Bit datas of current state.

Further, if the valid data figure place of last bat is 7 bytes, then need carries out an inverse operation and obtain final CRC check result; And the like, if the valid data figure place of last bat is 1 byte, then need carries out 7 inverse operations and obtain final CRC check result.

The invention also discloses in a kind of Fast Ethernet parallel CRC device, be used for the cyclic redundancy CRC check that walks abreast of Fast Ethernet data, said device comprises:

The CRC check module of preset bit wide is used for that Frame is carried out CRC and calculates check value;

Register is used to store said check value;

Last beat of data inverse operation module is used for clapping the effective word joint number according to last, and said check value is carried out inverse operation, obtains final CRC check result.

Further, said last beat of data inverse operation module is 8 inverse operation modules, and said 8 inverse operation module inverse operation formula are:

$C(i-8)={\mathrm{<figure-callout\; id="8"\; label="H"\; filenames="HDA00001844829200012.png"\; state="\{\{state\}\}">H</figure-callout>}}^8\&CircleTimes;C\left(i\right)\&CirclePlus;\left[\begin{array}{cccc}{\mathrm{<figure-callout\; id="7"\; label="H"\; filenames="HDA00001844829200012.png"\; state="\{\{state\}\}">H</figure-callout>}}^7\&CircleTimes;U& {\mathrm{<figure-callout\; id="6"\; label="H"\; filenames="HDA00001844829200012.png"\; state="\{\{state\}\}">H</figure-callout>}}^6\&CircleTimes;U& \&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;& U\end{array}\right]\&CircleTimes;D\left(8\right),$

Wherein C (i) is a CRC32 state matrix under the current state i, and H is an adjacent states inverse operation check matrix, and U is an adjoint matrix, and D (8) is preceding 8 Bit datas of current state.

Further, said preset bit wide is 64, and the CRC check module of said preset bit wide is 64 a CRC32 module.If the valid data figure place of last bat is 7 bytes, then need carries out an inverse operation and obtain final CRC check result; And the like, if the valid data figure place of last bat is 1 byte, then need carries out 7 inverse operations and obtain final CRC check result.

CRC check method of the present invention; Through the inverse operation of carrying out CRC less than last beat of data of predetermined width is drawn correct operation result; Even calculating cyclic redundancy value under the bigger situation of computing bit wide; Also can realize upper frequency, reduce CRC and calculated the logical resource that is consumed.Method of the present invention is applicable to the parallel data CRC check of any bit wide, and the scope of application is quite extensive.

CRC check device of the present invention only needs the CRC module of a preset bit wide and one 8 inverse operation module, just can realize the verification of the CRC of high-speed parallel data, and simple in structure, cost is low.

Description of drawings

The flow chart that Fig. 1 provides for the embodiment of the invention;

Fig. 2 is the structure chart of the realization of predetermined width module;

Fig. 3 is the generator polynomial structure chart of CRC32.

Embodiment

In order to make technical scheme of the present invention and advantage clearer, below in conjunction with accompanying drawing and embodiment, the present invention is carried out further detailed explanation, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.

In the present embodiment, be 64 with the operation bandwidth of data, adopting 64 CRC32 verification modules is that example comes the present invention is set forth in detail.As shown in Figure 1, Parallel CRC method of calibration of the present invention comprises step:

Step 101, Frame is carried out bit wide coupling with the 64bit bit wide, confirm the valid data figure place of last bat;

Step 102, Frame is sent into 64 general cyclic redundancy check (CRC) 32 modules calculate check value, process range is from the frame head to the postamble;

Step 103, according to the valid data figure place of last bat, check results is carried out inverse operation, obtain final CRC check result.

Further explain in the face of said method down.

Particularly, at first obtain Frame to be verified, comprise frame head sof in the Frame, postamble eof, data are effectively indicated dval, and the index signals such as effective word joint number dmod of last bat.

Because the indefinite length of Frame, carry out 64bit bit wide coupling after, the effective word joint number of last bat is smaller or equal to predetermined width.According to the effective word joint number dmod of last bat, last bat is divided into 7 kinds of situation, i.e. the effective word joint number of last bat is 8bit, 16bit, 24bit, 32bit, 40bit, 48bit, 56bit.When the effective word joint number of last bat is 64bit, directly calculate the CRC check result, therefore no longer tired in the present embodiment stating.

No matter how many effective word joint numbers of last bat is; Directly adopt the CRC module of preset bit wide to carry out CRC check; The preset bit wide of present embodiment is 64, adopts 64 CRC32 modules that Frame is directly carried out 64 CRC32 calculating, promptly no matter how many effective word joint numbers of last bat is; The CRC32 that carries out 64 calculates, and obviously slack byte is also counted.

Need to prove that if last bat comprises slack byte, the check value that then calculates is inaccurate, real effectively CRC check value should be the state before the slack byte.

According to the CRC32 multinomial; Can derive two relations between adjacent states; Concern according to adjacent states; Derive the check matrix of the CRC32 of adjacent states relation, also can derive the inverse operation relation between adjacent states similarly, and derive the CRC32 inverse operation check matrix of adjacent states relation.

Particularly, the generator polynomial of present embodiment CRC32 verification module is:

g(x)=x ³²+x ²⁶+x ²³+x ²²+x ¹⁶+x ¹²+x ¹¹+x ¹⁰+x ⁸+x ⁷+x ⁵+x ⁴+x ²+x+1 （1）

According to generator polynomial, the circuit structure that can draw CRC32 is as shown in Figure 2, and establishing d (i) is the Frame bit, c _j(i+1) state value of expression shift register j after i information code imported, wherein i is an input information sign indicating number sequence number, its span be (0,1 ..., 63); J is a shift register numbering, its span be (0,1 ..., 31).Can know the relation of adjacent states by Fig. 2:

$c_0\left(i\right)=c_{31}(i-1)\&CirclePlus;d(i-1)$ $c_8\left(i\right)=c_{31}(i-1)\&CirclePlus;d(i-1)\&CirclePlus;c_7(i-1)$

$c_1\left(i\right)=c_{31}(i-1)\&CirclePlus;d(i-1)c_0(i-1)$ c ₉(i)＝c ₈(i-1)

$c_2\left(i\right)=c_{31}(i-1)\&CirclePlus;d(i-1)\&CirclePlus;c_1(i-1)$ $c_{10}\left(i\right)=c_{31}(i-1)\&CirclePlus;d(i-1)\&CirclePlus;c_9(i-1)$

c ₃(i)＝c ₂(i-1) $c_{11}\left(i\right)=c_{31}(i-1)\&CirclePlus;d(i-1)\&CirclePlus;c_{10}(i-1)$

$c_4\left(i\right)=c_{31}(i-1)\&CirclePlus;d(i-1)\&CirclePlus;c_3(i-1)$ $c_{12}\left(i\right)=c_{31}(i-1)\&CirclePlus;d(i-1)\&CirclePlus;c_{11}(i-1)$

$c_5\left(i\right)=c_{31}(i-1)\&CirclePlus;d(i-1)\&CirclePlus;c_4(i-1)$ c ₁₃(i)＝c ₁₂(i-1)

c ₆(i)＝c ₅(i-1) c ₁₄(i)＝c ₁₃(i-1)

$c_7\left(i\right)=c_{31}(i-1)\&CirclePlus;d(i-1)\&CirclePlus;c_6(i-1)$ c ₁₅(i)＝c ₁₄(i-1)

$c_{16}\left(i\right)=c_{31}(i-1)\&CirclePlus;d(i-1)\&CirclePlus;c_{15}(i-1)$ c _2?4(i)＝c _2?3(-i?1)

c ₁₇(i)＝c ₁₆(i-1) c _2?5(i)＝c _2?4(-i?1)

c ₁₈(i)＝c ₁₇(i-1)

c ₁₉(i)＝c ₁₈(i-1) c _2?7(i)＝c _2?6(-i?1)

c ₂₀(i)＝c ₁₉(i-1) c _2?8(i)＝c _2?7(-i?1)

c ₂₁(i)＝c ₂₀(i-1) c _2?9(i)＝c _2?8(-i?1)

$c_{22}\left(i\right)=c_{31}(i-1)\&CirclePlus;d(i-1)\&CirclePlus;c_{21}(i-1)$ c _3?0(i)＝c _2?9(-i?1)

$c_{23}\left(i\right)=c_{31}(i-1)\&CirclePlus;d(i-1)\&CirclePlus;c_{22}(i-1)$ c _3?1(i)＝c _3?0(-i?1)

According to the relational matrix of adjacent states, can obtain the formula of following inverse operation:

$c_0(i-1)=c_0\left(i\right)\&CirclePlus;c_1\left(i\right)$ c ₈(i-1)＝c ₉(i)

$c_1(i-1)=c_0\left(i\right)\&CirclePlus;c_2\left(i\right)$ $c_9(i-1)=c_0\left(i\right)\&CirclePlus;c_{10}\left(i\right)$

c ₂(i-1)＝c ₃(i) $c_{10}(i-1)=c_0\left(i\right)\&CirclePlus;c_{11}\left(i\right)$

$c_3(i-1)=c_0\left(i\right)\&CirclePlus;c_4\left(i\right)$ $c_{11}(i-1)=c_0\left(i\right)\&CirclePlus;c_{12}\left(i\right)$

$c_4(i-1)=c_0\left(i\right)\&CirclePlus;c_5\left(i\right)$ c ₁₂(i-1)＝c ₁₃(i)

c ₅(i-1)＝c ₆(i) c ₁₃(i-1)＝c ₁₄(i)

$c_6(i-1)=c_0\left(i\right)\&CirclePlus;c_7\left(i\right)$ c ₁₄(i-1)＝c ₁₅(i)

$c_7(i-1)=c_0\left(i\right)\&CirclePlus;c_8\left(i\right)$ $c_{15}(i-1)=c_0\left(i\right)\&CirclePlus;c_{16}\left(i\right)$

c ₁₆(i-1)＝c ₁₇(i) c ₂₄(i-1)＝c ₂₅(i)

c ₁₇(i-1)＝c ₁₈(i) $c_{25}(i-1)=c_0\left(i\right)\&CirclePlus;c_{26}\left(i\right)$

c ₁₈(i-1)＝c ₁₉(i) c ₂₆(i-1)＝c ₂₇(i)

c ₁₉(i-1)＝c ₂₀(i) c ₂₇(i-1)＝c ₂₈(i)

c ₂₀(i-1)＝c ₂₁(i) c ₂₈(i-1)＝c ₂₉(i)

$c_{21}(i-1)=c_0\left(i\right)\&CirclePlus;c_{22}\left(i\right)$ c ₂₉(i-1)＝c ₃₀(i)

$c_{22}(i-1)=c_0\left(i\right)\&CirclePlus;c_{23}\left(i\right)$ c ₃₀(i-1)＝c ₃₁(i)

c ₂₃(i-1)＝c ₂₄(i) $c_{31}(i-1)=c_0\left(i\right)\&CirclePlus;d(i-1)$

Make C (i)=[c ₀(i) c ₁(i) ... c ₁₅(i) ... c ₃₀(i) c ₃₁(i)] ^T, with "

" representative replaces multiplying with " position with " computing in the matrix multiplication process, with "

" representative " position XOR ", then the inverse operation between adjacent states can be expressed as following form:

$C(i-1)=H\&CircleTimes;C\left(i\right)\&CirclePlus;U\&CircleTimes;d(i-1)---\left(2\right)$

Adjoint matrix U is in the formula:

$U={\left[\begin{array}{ccccc}0& 0& ...& 0& 1\end{array}\right]}_{32x1}^T,$

The CRC32 inverse operation check matrix H of adjacent states is:

It is thus clear that the inverse operation formula according to above-mentioned carries out inverse operation to step 102 result of calculation, just can draw the CRC check value of Frame.

Last bat of Frame is divided into 7 kinds of situation, and its effective word joint number is respectively 1,2,3; 4,5,6,7; Each byte comprises 8bit, if the effective word joint number of last bat is 7 bytes, then only needs the relational matrix according to adjacent states; Derive the polynomial relation of C (i) and C (i-8), carry out an inverse operation, just can draw final CRC check result.

Therefore, the present invention passes through one 8 inverse operation module, according to C (i) and the polynomial relation of C (i-8) and the value of dmod, carries out corresponding inverse operation, just can draw final CRC check result.If the effective word joint number is 7, then only need an inverse operation, if the effective word joint number is 6, then need twice inverse operation, by that analogy,, then need carry out 7 inverse operations this time when effective byte number is 1, obtain final CRC check result.

Suppose that the final state of CRC32 was C (i) when step 102 finished, invalid bit number is m, just need know m bit CRC check data before, i.e. the relation of C (i) and C (i-m).Can draw according to the inverse operation derivation of equation:

$C(i-m)=H^m\&CircleTimes;C\left(i\right)\&CirclePlus;\left[\begin{array}{cccc}{H}^{m-1}\&CircleTimes;U& H^{m-2}\&CircleTimes;U& \&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;& U\end{array}\right]\&CircleTimes;D\left(m\right)---\left(3\right)$

Data information matrix D (m)=[d (i-1) wherein ... D (i-m-1)] ^T

Particularly, because above-mentioned invalid bit number m is 56 to the maximum, minimum is 8, adopts 8 inverse operation module to carry out the inverse operation of corresponding number of times according to the invalidation word joint number, just can draw final CRC check value.Therefore only need know the relational expression of C (i) and C (i-8), just can carry out inverse operation by a byte ground extraction of byte invalid data.

According to formula (3), the relation of deriving C (i) and C (i-8) is following:

$C(i-8)=H^{\&prime;}\&CircleTimes;C\left(i\right)\&CirclePlus;U^{\&prime;}\&CircleTimes;D\left(8\right),---\left(4\right)$

Wherein:

$U^{\&prime;}={\left[\begin{array}{cccccccccccccccccccccccccccccccc}O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& 1& O& O& O& O& O& O& O\\ O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& 1& O& O& O& O& O& O\\ O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& 1& O& O& O& O& O\\ O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& 1& O& O& O& O\\ O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& 1& O& O& O\\ O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& 1& O& O\\ O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& 1& O\\ O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& O& 1\end{array}\right]}^T$

D(8)＝[d(i-1)……d(i-7)] ^T

What derivation drew here is the CRC inverse operation Matrix Formula of 8bit parallel computation; According to this matrix relationship; Result of calculation to step 102 is carried out inverse operation, if the effective word joint number is 7, then carries out an inverse operation and just can draw right value; If the effective word joint number is that 1 needs just can draw right value 7 times, by that analogy ...For preset bit wide in the present embodiment is 64 bits, and effective word joint number scope is 1 to 7, can obtain a result for maximum 7 times.

Need to prove that when carrying out inverse operation, data information matrix all is 8 at every turn, different is that each data are respectively the invalid data values of preceding 8 bit of current state.

Need to prove, in actual design,, derive corresponding inverse operation matrix, just can realize any width, the CRC check of any high-frequency data according to the multinomial of the verification module of different preset bit wide and employing.

The present invention has proposed in a kind of Fast Ethernet parallel CRC device simultaneously, is used for the cyclic redundancy CRC check that walks abreast of Fast Ethernet data, and is as shown in Figure 3, comprising:

The CRC check module of preset bit wide is specially CRC32 64 parallel-by-bit computing modules, is used for that Frame is carried out CRC and calculates check value;

Register is used to store check value;

Last beat of data inverse operation module is used for clapping the effective word joint number according to last, and said check value is carried out inverse operation, obtains final CRC check result.

The preset bit wide of present embodiment is 64; Adopt 64 CRC32 modules to carry out CRC check; At first the input complete data frame is carried out verification, draw check value, then through last beat of data inverse operation module; Last beat of data inverse operation module is 8 inverse operation modules, carries out inverse operation according to the valid data figure place of last bat and obtains final CRC result.If the valid data of last bat are 7 bytes, then need carry out an inverse operation and obtain final CRC check result; And the like, if the valid data figure place of last bat is 1 byte, then need carries out 7 inverse operations and obtain final CRC check result.

Above embodiment is only in order to technical scheme of the present invention to be described but not limit it; Under the situation that does not deviate from spirit of the present invention and essence thereof; Those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.

Claims (10)

1. parallel cyclic redundancy check method in the Fast Ethernet is applied to the CRC that walks abreast of cyclic redundancy check (CRC) module, it is characterized in that, comprises;

Step 1, Frame is carried out the bit wide coupling with preset bit wide;

Step 2, the data flow after will mating are sent into the parallel CRC module of general preset bit wide and are calculated check value;

Step 3, according to the valid data figure place of last bat, said check value is carried out inverse operation, obtain final CRC check result.

2. parallel cyclic redundancy check method in the Fast Ethernet as claimed in claim 1 is characterized in that said step 3 comprises:

Read the valid data figure place information of last bat, the number of times of decision inverse operation;

Extract the preceding 8 bit invalid datas of current state;

Carry out 8 inverse operations;

If the inverse operation number of times is not intact, continue to extract the preceding 8 bit invalid datas of current state, carry out inverse operation, up to accomplishing inverse operation, obtain final CRC check result.

3. parallel cyclic redundancy check method in according to claim 1 or claim 2 the Fast Ethernet is characterized in that said preset bit wide is 64, and the parallel CRC module of said preset bit wide is 64 CRC32 modules.

4. parallel cyclic redundancy check method in the Fast Ethernet as claimed in claim 3 is characterized in that said 8 inverse operation formula are:

$C(i-8)=H^8\&CircleTimes;C\left(i\right)\&CirclePlus;\left[\begin{array}{cccc}{H}^7\&CircleTimes;U& H^6\&CircleTimes;U& \&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;& U\end{array}\right]\&CircleTimes;D\left(8\right),$

Wherein C (i) is a CRC32 state matrix under the current state i, and H is an adjacent states inverse operation check matrix, and U is an adjoint matrix, and D (8) is preceding 8 Bit datas of current state.

5. parallel cyclic redundancy check method is characterized in that in the Fast Ethernet as claimed in claim 4, if the valid data figure place of last bat is 7 bytes, then need carries out an inverse operation and obtain final CRC check result; And the like, if the valid data figure place of last bat is 1 byte, then need carries out 7 inverse operations and obtain final CRC check result.

6. parallel CRC device in the Fast Ethernet is used for the cyclic redundancy CRC check that walks abreast of Fast Ethernet data is characterized in that said device comprises:

The CRC check module of preset bit wide is used for that Frame is carried out CRC and calculates check value;

Register is used to store said check value;

Last beat of data inverse operation module is used for clapping the effective word joint number according to last, and said check value is carried out inverse operation, obtains final CRC check result.

7. parallel CRC device is characterized in that said last beat of data inverse operation module is 8 inverse operation modules in the Fast Ethernet as claimed in claim 6.

8. parallel CRC device in the Fast Ethernet as claimed in claim 7 is characterized in that said 8 inverse operation module inverse operation formula are:

$C(i-8)=H^8\&CircleTimes;C\left(i\right)\&CirclePlus;\left[\begin{array}{cccc}{H}^7\&CircleTimes;U& H^6\&CircleTimes;U& \&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;& U\end{array}\right]\&CircleTimes;D\left(8\right),$

Wherein C (i) is a CRC32 state matrix under the current state i, and H is an adjacent states inverse operation check matrix, and U is an adjoint matrix, and D (8) is preceding 8 Bit datas of current state.

9. parallel CRC device is characterized in that said preset bit wide is 64 in the Fast Ethernet as claimed in claim 8, and the CRC check module of said preset bit wide is 64 a CRC32 module.

10. parallel CRC device is characterized in that in the Fast Ethernet as claimed in claim 9, if the valid data figure place of last bat is 7 bytes, then need carries out an inverse operation and obtain final CRC check result; And the like, if the valid data figure place of last bat is 1 byte, then need carries out 7 inverse operations and obtain final CRC check result.

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