CN102751258B - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit Download PDFInfo
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- CN102751258B CN102751258B CN201110244035.6A CN201110244035A CN102751258B CN 102751258 B CN102751258 B CN 102751258B CN 201110244035 A CN201110244035 A CN 201110244035A CN 102751258 B CN102751258 B CN 102751258B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction.
Description
Cross-Reference to Related Applications
This application claims the priority of the korean patent application No.10-2011-0037482 of the submission of on April 21st, 2011,
Entire contents merge herein by quoting.
Technical field
The exemplary embodiment of the present invention is related to a kind of quasiconductor designing technique, has three-dimensional more particularly to a kind of
(3D) semiconductor integrated circuit of package-on-package structure.
Background technology
The encapsulation technology of semiconductor integrated circuit is just further towards miniaturization and installation reliability aspect development.In order to
The high-performance of Electrical and Electronic product is adapted to while pursuing the miniaturization of Electrical and Electronic product, laminate packaging skill has been used
Art.
Here, " stacking " refer to vertically be laminated at least two or more semiconductor chip or packaging body.When half
When conductor memory uses laminate packaging, it is possible to obtain the product with twice or the memory capacity of more times.In addition, stacking
Package parts not only increase memory span, and also increase packaging density and the efficiency using erection space.Therefore, layer
Folded encapsulation technology is useful.
Here it is possible to manufacture laminate packaging according to following method.According to first method, single half can be first laminated
Conductor chip, then disposably encapsulates.According to second method, the single semiconductor chip for having encapsulated can be laminated.Tool
There is each semiconductor chip for the semiconductor packages being laminated via metal wire or break-through silicon hole (TSV) electric coupling.Using TSV
Laminate packaging have by being formed in each semiconductor chip in TSV vertically realizing the physics between semiconductor chip
With the structure of electric coupling.
Fig. 1 is the side cross-sectional view of existing semiconductor integrated circuit.Fig. 2 is the flat of the 4th semiconductor chip shown in Fig. 1
Face figure.
Referring to Fig. 1 and Fig. 2, semiconductor integrated circuit 100 includes first to fourth semiconductor chip 110 to 140, Duo Ge
One break-through chip through hole 150A to 150C, multiple second break-through chip through hole 160A to 160C, multiple 3rd break-through chip through holes
170A to 170E and multiple coupling pad BP11 to BP13.First to fourth semiconductor chip 110 to 140 is vertically laminated.It is many
Individual first break-through chip through hole 150A to 150C wears in multiple first position corresponding with each the first break-through chip through hole
Lead to first to fourth semiconductor chip 110 to 140 and be vertically formed, and be configured to as the first power supply Power1
Interface and operate.Multiple second break-through chip through hole 160A to 160C are corresponding with each the second break-through chip through hole more
The individual semiconductor chip 110 to 140 of second position break-through first to fourth and be vertically formed, and be configured to as being used for
The interface of second source Power2 and operate.Multiple 3rd break-through chip through hole 170A to 170E with each the 3rd break-through chip
The semiconductor chip 110 to 140 of break-through first to fourth at corresponding multiple 3rd positions of through hole and be vertically formed, and quilt
It is configured to be operated as the interface for various signals.Multiple coupling pad BP11 to BP13 are arranged on each break-through chip
Between through hole 150A to 150C, 160A to 160C and 170A to 170E, and it is configured to corresponding break-through chip through hole electricity
Coupling.
First to fourth semiconductor chip 110 to 140 can be manufactured using identical technique.In this case, locate
The first master chip 110 at undermost position is used as master chip, and other semiconductor chips 120 to 140 are used as from core
Piece.
Because multiple break-through chip through hole 150A to 150C, 160A to 160C and 170A to 170E are configured to as being used for
The interface of power supply and signal and operate, therefore they can be formed by the metal with satisfactory electrical conductivity.It is, for example possible to use copper
(Cu).Multiple first to the 3rd break-through chip through hole 150A to 150C, 160A to 160C and 170A to 170E include TSV.
In addition, multiple coupling pad BP11 to BP13 refer to bump pad.
According to semiconductor integrated circuit 100 arranged as described above, via the first to the 3rd break-through chip through hole 150A
Various signals and power supply are transmitted to 150C, 160A to 160C and 170A to 170E.Therefore, it can prolong current drain and signal
It is minimum late, and operating characteristics can be strengthened with improved bandwidth.
However, existing semiconductor integrated circuit 100 has following feature.
Each in first to fourth semiconductor chip 110 to 140 includes the active layer for being formed on the upper surface of which,
And the various circuits being arranged in active layer.However, according to highly integrated trend, the circuit of minimum number is only left, and
Unwanted circuit is eliminated, to reduce the size of first to fourth semiconductor chip 110 to 140.The circuit for generally being removed
Can include for the circuit of stabilized power source (for example, storage (reservoir capacitor)).In addition, be used for
First break-through chip through hole 150A to 150C of power interface and the second break-through chip through hole 160A to 160C has vertically coupling
Vertical structure, wherein the vertical structure is easily affected by ohm voltage drop.Here, with the semiconductor chip being laminated
Quantity increases, and also to increase with the quantity of the break-through chip through hole of semiconductor chip coupling.For being layered in wearing for upper position
For obturator piece through hole, they can access relatively low power supply because of the inevitable ohm voltage drop for occurring.In this case,
Break down because of unstable signal transmission, and can not correctly hold because of unstable asynchronous nature
Row high speed operation.
In addition, existing semiconductor integrated circuit 100 possibly cannot correctly be analyzed via multiple the under encapsulation state
Mistake during three break-through chip through hole 170A to 170E transmission signals.
The content of the invention
One embodiment of the present of invention for it is a kind of can keep stable power supply and while not increasing the quasiconductor of size
Integrated circuit.
An alternative embodiment of the invention can be performed accurately under encapsulation state for one kind via signal monitoring
Signal transmits the semiconductor integrated circuit of failure analysis.
According to one embodiment of present invention, a kind of semiconductor integrated circuit includes：Semiconductor chip；Multiple first break-through
Chip through hole, the plurality of first break-through chip through hole break-through semiconductor chip is vertically formed, and is configured to as
The interface of one power supply and operate；And first common conductive layer, first common conductive layer be arranged on semiconductor chip it
On, and the plurality of first break-through chip through hole is coupled to each other in the horizontal direction.
According to another embodiment of the invention, a kind of semiconductor integrated circuit includes：What is be vertically stacked is multiple
Semiconductor chip；Multiple first break-through chip through holes, the plurality of semiconductor core of the plurality of first break-through chip through hole break-through
Piece is vertically formed, and is configured to be operated as the interface of the first power supply；And first common conductive layer, described first
Common conductive layer is arranged on the semiconductor core being laminated at most upperstratum position among the semiconductor chip of the plurality of stacking
On piece, and the plurality of first break-through chip through hole is coupled to each other in the horizontal direction.
According to another embodiment of the invention, a kind of semiconductor integrated circuit includes：What is be vertically stacked is multiple
Semiconductor chip；Multiple first break-through chip through holes, the plurality of first break-through chip through hole respectively with first break-through
The corresponding the plurality of semiconductor chip of multiple first position break-through of chip through hole and be vertically formed, and be configured to
Operate as the interface of the first power supply；First common conductive layer, first common conductive layer is arranged on the plurality of half
On the semiconductor chip being laminated at most upperstratum position among conductor chip, and the plurality of first break-through chip is led to
Hole couples in the horizontal direction；Multiple second break-through chip through holes, the plurality of second break-through chip through hole is respectively with described
The corresponding the plurality of semiconductor chip of multiple second position break-through of two break-through chip through holes and be vertically formed, and quilt
It is configured to be operated as the interface of second source；And multiple coupling pads, the plurality of coupling pad is disposed in and institute
State and coupled in the first common conductive layer identical layer and respectively with the second break-through chip through hole.
Description of the drawings
Fig. 1 is the side cross-sectional view of existing semiconductor integrated circuit.
Fig. 2 is the plane graph of the 4th semiconductor chip shown in Fig. 1.
Fig. 3 is the side cross-sectional view of the semiconductor integrated circuit of first embodiment of the invention.
Fig. 4 is the plane graph of the superiors for including the first common conductive layer and the second common conductive layer shown in Fig. 3.
Fig. 5 is the side cross-sectional view of semiconductor integrated circuit according to the second embodiment of the present invention.
Fig. 6 is to include the first common conductive layer and the second common conductive layer and multiple coupling pads shown in Fig. 5 most
The plane graph on upper strata.
Specific embodiment
The exemplary embodiment of the present invention is described more fully below with reference to accompanying drawings.However, the present invention can be with not
With mode implementing, and should not be construed as limited to embodiments set forth herein.Exactly, there is provided these enforcements
Example is in order that this specification will be apparent and complete, and the model of the present invention will be fully passed on to those skilled in the art
Enclose.In this manual, identical reference represents identical part in each drawings and Examples of the present invention.
Accompanying drawing is not necessarily drawn to scale, and in some cases in order to the Characteristic Contrast example that embodiment is explicitly described is done
Exaggerate process.When refer to ground floor the second layer " on " or substrate " on " when, it not only represents that ground floor is formed directly into
Situation on the second layer or substrate, is also represented by ground floor and the second layer or between ground floor and substrate the presence of the feelings of third layer
Condition.
In an embodiment of the present invention, in case of will be to be laminated four semiconductor chips.
Fig. 3 is the sectional view of semiconductor integrated circuit according to an embodiment of the invention.Fig. 4 is included shown in Fig. 3
The first common conductive layer and the second common conductive layer the superiors plane graph.
Referring to Fig. 3 and Fig. 4, semiconductor integrated circuit 200 includes first to fourth semiconductor chip 210 to 240, Duo Ge
One break-through chip through hole 250A to 250C, the first common conductive layer 280A, multiple first contact portion 291A to 291C, Duo Ge
Two break-through chip through hole 260A to 260C, the second common conductive layer 280B, multiple second contact portion 293A to 293C, Duo Ge
Three break-through chip through hole 270A to 270E and multiple bump pad BP21 to BP23.First to fourth semiconductor chip 210 to 240
Vertically it is laminated.Multiple first break-through chip through hole 250A to 250C are corresponding with each the first break-through chip through hole multiple
The semiconductor chip 110 to 140 of first position break-through first to fourth and be vertically formed, and be configured to as the
The interface of one power supply and operate.First common conductive layer 280A is arranged among first to fourth semiconductor chip 210 to 240
The 4th semiconductor chip 240 being layered at most upperstratum position on, and be configured to lead to the plurality of break-through chip
Hole 250A to 250C is coupled in the horizontal direction.Multiple first contact portion 291A to 293C are configured to the first common conductive layer
280A is mutually coupled respectively with the plurality of first break-through chip through hole 250A to 250C.Multiple second break-through chip through hole 260A are extremely
260C is in multiple second position break-through first to fourth semiconductor chip 210 corresponding with each the second break-through chip through hole
It is vertically formed to 240, and is configured to be operated as the interface for second source.Second common conductive layer 280B
It is arranged on the 4th semiconductor chip 240, and is configured to the plurality of break-through chip through hole 260A to 260C edges
Horizontal direction is coupled to each other.Multiple second contact portion 293A to 293C be configured to by the second common conductive layer 280B respectively with
The plurality of second break-through chip through hole 260A to 260C is mutually coupled.Multiple 3rd break-through chip through hole 270A to 270E are configured
To operate as the interface for various signals.Multiple bump pad BP21 to BP23 are arranged on each break-through chip through hole
Between 250A to 250C, 260A to 260C and 270A to 270E, and it is configured to corresponding break-through chip through hole electric coupling.
First to fourth semiconductor chip 210 to 240 can be manufactured using identical technique.Here, positioned at orlop
First semiconductor chip 210 of position as master chip, and other second to four semiconductor chip 220 to 240 as from
Chip.That is, the first semiconductor chip 210 is configured to that second will be sent to from the outside various signals for applying and power supply
To the 4th semiconductor chip 220 to 240, and the second to the 4th semiconductor chip 220 to 240 is configured to be led according to the first half
The control of body chip 210 is performing predetermined operation.
Because the multiple first to the 3rd break-through chip through hole 250A to 250C, 260A to 260C and 270A to 270E are configured
To operate as the interface for power supply or signal, therefore they can be formed by the metal with satisfactory electrical conductivity.For example, may be used
With using copper (Cu).Multiple first to the 3rd break-through chip through hole 250A to 250C, 260A to 260C and 270A to 270E include
TSV.In this embodiment, the quantity of the first break-through chip through hole 250A to 250C, the second break-through chip through hole 260A to 260C
Quantity and the quantity of the 3rd break-through chip through hole 270A to 270E be separately arranged as 3,3 and 5.However, being not limited to
This, can essentially arrange hundreds of or thousands of break-through chip through holes.
First common conductive layer 280A and the second common conductive layer 280B are set within the same layer, and are formed into phase
Same height.In addition, referring to Fig. 4, the first common conductive layer 280A and the second common conductive layer 280B be spaced it is desired away from
From D1.That is, ground floor 280A and second layer 280B are electrically isolated from one.Now, the first common conductive layer 280A and second
The distance between common conductive layer 280B D1 defines the gap for being formed as concaveconvex shape.By this structure, it is arranged to flat
Row in a direction the first break-through chip through hole 250A to 250C and the second break-through chip through hole 260A to 260C can with it is every
Individual isolated from power couples same power supply.That is, the first common conductive layer 280A and the second common conductive layer 280B quilt
It is set to power grid (power supply mesh) device, the power grid device is used to vertically to couple
Multiple first break-through chip through hole 250A to 250C and multiple second break-through chip through hole 260A to 260C are in the horizontal direction each other
Coupling.
Multiple first contact portion 291A to 291C and multiple second contact portion 293A to 293C are respectively supplied to first
Break-through chip through hole 250A to 250C and the second break-through chip through hole 260A to 260C, and be essentially used for connecing first respectively
Contact portion point 291A to 291C and the second contact portion 293A to 293C and the first common conductive layer 280A and the second common conductive layer
280B is coupled.Multiple first contact portion 291A to 291C and multiple second contact portion 293A to 293C and first public lead
Electric layer 280A and the second common conductive layer 280B can be formed by metal.
The semiconductor integrated circuit 200 of first embodiment of the invention, in break-through chip through hole vertically coupling
It is coupled to each other in the horizontal direction via common conductive layer from the farthest break-through chip through hole of power supply in the break-through chip structure for connecing.Cause
This, it is possible to achieve effective power grid structure.Power supply can refer to the power supply for being for example supplied to the first semiconductor chip 210.
Vertically in break-through chip through-hole structure, under the abundant ability for providing power supply can be because of the ohm voltage drop towards its distal end
Drop.Therefore, when in the horizontal direction being coupled the break-through chip through hole positioned at distal end using common conductive layer, can be because of resistance value
The reason of decline fully provides for power supply.In addition, defining parasitism between the first common conductive layer and the second common conductive layer
Electric capacity, and parasitic electricity can be formed between the topmost metal layer of the first and second common conductive layers and the 4th semiconductor chip
Hold.When using the power grid structure, the parasitic capacitance for being formed in this way can promote power good.That is, posting
Raw electric capacity is operated as storage.
In the first embodiment of the present invention, it has been described that the first and second common conductive layers are arranged on the superiors.
However, the first and second common conductive layers can also be arranged between semiconductor chip.In addition, corresponding with each power supply is convex
Block pad is mutually coupled with the first common conductive layer or the second common conductive layer.In this case, there is provided significantly more efficient electricity
Source network.Here it is possible to be manufactured the first and second common conductive layers by identical technique.
Fig. 5 is the side cross-sectional view of semiconductor integrated circuit according to the second embodiment of the present invention.Fig. 6 is to include Fig. 5 institutes
The first and second common conductive layers shown and the plane graph of the superiors of multiple coupling pads.
The second embodiment of the present invention is characterised by, in addition to the technical characteristic of first embodiment, quasiconductor is integrated
Circuit can transmit mistake with signal Analysis.Therefore, in this embodiment, will focus on description with the first embodiment of the present invention not
Same feature.
Referring to Fig. 5 and Fig. 6, semiconductor integrated circuit according to the second embodiment of the present invention also includes multiple coupling pads
381C, 383C, 385C, 387C and 389C, and multiple 3rd contact portion 395A to 395E.Multiple coupling pad 381C,
383C, 385C, 387C and 389C are disposed on the 4th semiconductor chip 340, and with multiple break-through chip through hole 370A
Couple to 370E phases, the plurality of break-through chip through hole 370A to 370E is configured to be grasped as the interface for various signals
Make.Multiple 3rd contact portion 395A to 395E substantially respectively by multiple coupling pad 381C, 383C, 385C, 387C and
389C is coupled with multiple 3rd break-through chip through hole 370A to 370E.
It is multiple coupling pad 381C, 383C, 385C, 387C and 389C be arranged on the first and second common layers 380A and
In 380B identical layers, and it is isolated with the first and second common layers 380A and 380B, as shown in Figure 6.Now, due to multiple
Coupling pad 381C, 383C, 385C, 387C and 389C are used as the pad of probe test (probe test), therefore they
The size for being able to carry out probe test can be formed with.
Multiple 3rd contact portion 395A to 395E are respectively set at multiple coupling pad 381C, 383C, 385C, 387C
And 389C and multiple 3rd break-through chip through hole 370A to 370E between, to correspond.Multiple 3rd contact portions 395A are extremely
395E is essentially used for respectively leading to multiple coupling pad 381C, 383C, 385C, 387C and 389C with multiple 3rd break-through chips
Hole 370A to 370E is coupled.3rd contact portion 395A to 395E and multiple coupling pad 381C, 383C, 385C, 387C and
389C can be formed by metal.
Even if semiconductor integrated circuit according to the second embodiment of the present invention can also be via respectively under encapsulation state
Probe test is performed with the coupling pad of the break-through chip through hole electric coupling for signal.In other words, even if in encapsulation state
Under can also be appropriately carried out via signal monitoring signal transmission failure analysis.Therefore, because can in advance detect potential
Signal transmission failure, therefore the process time of manufacture semiconductor integrated circuit can be shortened, and it is integrated to improve quasiconductor
The operational stability of circuit.
In the second embodiment of the present invention, it has been described that the first common conductive layer and the second common conductive layer are only set
Put in the superiors.However, being not limited to this, the first common conductive layer and the second common conductive layer can also be arranged on each
Between semiconductor chip.In such a case, it is possible to realize significantly more efficient power grid structure.
Embodiments in accordance with the present invention, being in via conductive layers couple the most upperstratum position of laminated semiconductor chip is used for
The break-through chip through hole of same power supplies.Therefore, can realize while the size of laminated semiconductor chip is not increased effectively
Power grid structure.Therefore, semiconductor integrated circuit can resist power supply noise, while having and the integrated electricity of existing quasiconductor
Road identical size.Therefore, it is possible to substantially prevent failure by stable signal transmission, and by allow high speed operation come
Obtain enough operating characteristics.
Further, since there is provided for probe test pad and the conductive layer for power grid, even if therefore
Encapsulation state can also perform Signal Fail analysis.The pad is electrically insulated with conductive layer.Therefore, because can in advance detect latent
Signal transmission failure, therefore process time of manufacture semiconductor integrated circuit can be shortened, and quasiconductor can be obtained
The sufficient operating reliability of integrated circuit.
Although the present invention has had been described with reference to specific embodiments, it will be apparent to one skilled in the art that
On the premise of the spirit and scope of the invention limited without departing from claims, variations and modifications can be carried out.
Claims (17)
1. a kind of semiconductor integrated circuit, including：
Semiconductor chip；
Multiple first break-through chip through holes, the vertical landform of semiconductor chip described in the plurality of first break-through chip through hole break-through
Into, and be configured to be operated as the interface for the first power supply；
First common conductive layer, first common conductive layer is arranged on the semiconductor chip, and will be described many
Individual first break-through chip through hole is coupled to each other in the horizontal direction；
Multiple second break-through chip through holes, the vertical landform of semiconductor chip described in the plurality of second break-through chip through hole break-through
Into, and be configured to be operated as the interface for second source；And
Second common conductive layer, second common conductive layer is arranged on the semiconductor chip, and will be described many
Individual second break-through chip through hole is coupled to each other in the horizontal direction,
Wherein, first common conductive layer and second common conductive layer are arranged on identical level, and with many
Individual protuberance, the plurality of protuberance is projected in the horizontal direction towards the bearing of trend of the semiconductor chip,
Wherein, the plurality of protrusion of the plurality of protuberance of first common conductive layer and second common conductive layer
Portion is opened with desired separating distance and is alternately arranged,
Wherein, first power supply is supplied to each in the plurality of protuberance of first common conductive layer, and
The second source is supplied to each in the plurality of protuberance of second common conductive layer.
2. semiconductor integrated circuit as claimed in claim 1, also including multiple first contact portions, the plurality of first contact
Part mutually couples first common conductive layer with the plurality of first break-through chip through hole.
3. semiconductor integrated circuit as claimed in claim 2, wherein, first common conductive layer and the plurality of first connects
Contact portion point is formed by metal.
4. semiconductor integrated circuit as claimed in claim 1, also including multiple second contact portions, the plurality of second contact
Part mutually couples second common conductive layer with the plurality of second break-through chip through hole.
5. semiconductor integrated circuit as claimed in claim 4, wherein, second common conductive layer and the plurality of second connects
Contact portion point is formed by metal.
6. semiconductor integrated circuit as claimed in claim 1, wherein, first common conductive layer is public with described second to be led
Electric layer is separated each other by gap, and the gap is in opposite first common conductive layer and the described second public conduction
There is constant width in the whole length of layer.
7. semiconductor integrated circuit as claimed in claim 1, wherein, first common conductive layer is public with described second to be led
Electric layer is separated each other by gap, and the gap is in opposite first common conductive layer and the described second public conduction
There is constant width in the whole length of layer.
8. semiconductor integrated circuit as claimed in claim 7, wherein, first common conductive layer is public with described second to be led
Gap between electric layer forms concaveconvex shape in first common conductive layer and second common conductive layer.
9. semiconductor integrated circuit as claimed in claim 1, wherein, the plurality of first break-through chip through hole and the plurality of
Second break-through chip through hole includes break-through silicon hole.
10. a kind of semiconductor integrated circuit, including：
The multiple semiconductor chips being vertically stacked；
Multiple first break-through chip through holes, the plurality of semiconductor chip of the plurality of first break-through chip through hole break-through is vertically
Formed, and be configured to be operated as the interface for the first power supply；
First common conductive layer, first common conductive layer is arranged on the layer among multiple semiconductor chips of the stacking
It is stacked on the semiconductor chip at most upperstratum position, and by the plurality of first break-through chip through hole in the horizontal direction each other
Coupling；
Multiple second break-through chip through holes, the semiconductor chip of stacking is vertical described in the plurality of second break-through chip through hole break-through
Ground is formed, and is configured to be operated as the interface for second source；And
Second common conductive layer, second common conductive layer is arranged on the layer among multiple semiconductor chips of the stacking
It is laminated on the semiconductor chip at most upperstratum position, and by the plurality of second break-through chip through hole in the horizontal direction each other
Coupling,
Wherein, first common conductive layer and second common conductive layer are arranged on identical level, and with many
Individual protuberance, the plurality of protuberance is projected in the horizontal direction towards the bearing of trend of the semiconductor chip,
Wherein, the plurality of protrusion of the plurality of protuberance of first common conductive layer and second common conductive layer
Portion is opened with desired separating distance and is alternately arranged,
Wherein, first power supply is supplied to each in the plurality of protuberance of first common conductive layer, and
The second source is supplied to each in the plurality of protuberance of second common conductive layer.
11. semiconductor integrated circuit as claimed in claim 10, also including multiple first contact portions, the plurality of first connects
Contact portion point mutually couples first common conductive layer with the plurality of first break-through chip through hole.
12. semiconductor integrated circuit as claimed in claim 11, wherein, first common conductive layer and the plurality of first
Contact portion is formed by metal.
A kind of 13. semiconductor integrated circuit, including：
The multiple semiconductor chips being vertically stacked；
Multiple first break-through chip through holes, the plurality of first break-through chip through hole respectively with the first break-through chip through hole
The corresponding the plurality of semiconductor chip of multiple first position break-through and be vertically formed, and be configured to as being used for
The interface of the first power supply and operate；
First common conductive layer, first common conductive layer is arranged on being layered in most among the plurality of semiconductor chip
On semiconductor chip at topside position, and the plurality of first break-through chip through hole is coupled to each other in the horizontal direction；
Multiple second break-through chip through holes, the plurality of second break-through chip through hole respectively with the second break-through chip through hole
The corresponding the plurality of semiconductor chip of multiple second position break-through and be vertically formed, and be configured to as being used for
The interface of second source and operate；
Multiple coupling pads, the plurality of coupling pad is disposed in and the first common conductive layer identical level, and
Couple with the second break-through chip through hole respectively；
Multiple 3rd break-through chip through holes, the plurality of 3rd break-through chip through hole respectively with the plurality of 3rd break-through chip
The plurality of semiconductor chip of break-through at corresponding multiple 3rd positions of through hole and be vertically formed, and be configured to conduct
Operate for the interface of signal；And
Second common conductive layer, second common conductive layer be arranged on the semiconductor chip that is laminated at most upperstratum position it
On, and the plurality of second break-through chip through hole is coupled to each other,
Wherein, first common conductive layer and second common conductive layer are arranged on identical level, and with many
Individual protuberance, the plurality of protuberance is projected in the horizontal direction towards the bearing of trend of the semiconductor chip,
Wherein, the plurality of protrusion of the plurality of protuberance of first common conductive layer and second common conductive layer
Portion separates within a predetermined distance and is alternately arranged,
Wherein, first power supply is supplied to each in the plurality of protuberance of first common conductive layer, and
The second source is supplied to each in the plurality of protuberance of second common conductive layer.
14. semiconductor integrated circuit as claimed in claim 13, also including multiple first contact portions, the plurality of first connects
Contact portion point mutually couples first common conductive layer with the plurality of first break-through chip through hole.
15. semiconductor integrated circuit as claimed in claim 13, also including multiple second contact portions, the plurality of second connects
Contact portion point mutually couples the second break-through chip through hole with the plurality of coupling pad.
16. semiconductor integrated circuit as claimed in claim 15, first common conductive layer and the plurality of first contact
Part and the plurality of second contact portion are formed by metal.
17. semiconductor integrated circuit as claimed in claim 13, wherein, the plurality of coupling pad is included for probe test
Pad.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2011-0037482 | 2011-04-21 | ||
| KR1020110037482A KR101211046B1 (en) | 2011-04-21 | 2011-04-21 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102751258A CN102751258A (en) | 2012-10-24 |
| CN102751258B true CN102751258B (en) | 2017-05-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110244035.6A Active CN102751258B (en) | 2011-04-21 | 2011-08-24 | Semiconductor integrated circuit |
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| US (1) | US8564138B2 (en) |
| KR (1) | KR101211046B1 (en) |
| CN (1) | CN102751258B (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9559086B2 (en) | 2015-05-29 | 2017-01-31 | Micron Technology, Inc. | Semiconductor device with modified current distribution |
| US9940419B1 (en) * | 2015-08-05 | 2018-04-10 | The United States Of America As Represented By The Secretary Of The Army | Post design integrated circuit manufacturing obfuscation |
| CN115411005A (en) | 2021-05-26 | 2022-11-29 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method of semiconductor structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1467835A (en) * | 2002-07-10 | 2004-01-14 | 矽品精密工业股份有限公司 | Lead frame adapting to integrate circuit miniaturization trend |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5581122A (en) * | 1994-10-25 | 1996-12-03 | Industrial Technology Research Institute | Packaging assembly with consolidated common voltage connections for integrated circuits |
| KR20090011769A (en) | 2007-07-27 | 2009-02-02 | 삼성전자주식회사 | Semiconductor package having heat radiation capacitor |
| US8304863B2 (en) * | 2010-02-09 | 2012-11-06 | International Business Machines Corporation | Electromigration immune through-substrate vias |
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2011
- 2011-04-21 KR KR1020110037482A patent/KR101211046B1/en active IP Right Grant
- 2011-08-02 US US13/196,320 patent/US8564138B2/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1467835A (en) * | 2002-07-10 | 2004-01-14 | 矽品精密工业股份有限公司 | Lead frame adapting to integrate circuit miniaturization trend |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101211046B1 (en) | 2012-12-12 |
| KR20120119512A (en) | 2012-10-31 |
| US8564138B2 (en) | 2013-10-22 |
| US20120267790A1 (en) | 2012-10-25 |
| CN102751258A (en) | 2012-10-24 |
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