CN102741992A - Apparatus and method for measuring withstand voltage of semiconductor element - Google Patents
Apparatus and method for measuring withstand voltage of semiconductor element Download PDFInfo
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- CN102741992A CN102741992A CN2009801007518A CN200980100751A CN102741992A CN 102741992 A CN102741992 A CN 102741992A CN 2009801007518 A CN2009801007518 A CN 2009801007518A CN 200980100751 A CN200980100751 A CN 200980100751A CN 102741992 A CN102741992 A CN 102741992A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
- G01R31/2623—Circuits therefor for testing field effect transistors, i.e. FET's for measuring break-down voltage therefor
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
- G01R31/20—Preparation of articles or specimens to facilitate testing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
Provided is a withstand voltage measuring method for measuring withstand voltages of a plurality of semiconductor elements formed on a wafer surface. The method includes a step (A) of fixing the wafer on a stage; a step (B) of covering, with an insulating solution, only a part of the wafer surface, i.e., one or more electrodes, which are arranged on one semiconductor element selected from among at least the semiconductor elements and exposed to atmosphere, and are electrodes wherein withstand voltages are to be measured, and bringing a probe into contact with at least one of the electrodes; and a step (C) of measuring a withstand voltage between at least one of the electrodes and a point selected from the surface of the stage.
Description
Technical field
The present invention relates to withstand voltage withstand voltage determinator of measuring and withstand voltage assay method to semiconductor element; Relate in particular under a kind of wafer state before in being installed to encapsulation, can be to having the withstand voltage withstand voltage determinator of measuring and the withstand voltage assay method of high withstand voltage silicon carbide semiconductor device constant power device.
Background technology
Semiconductor element is formed with a plurality of usually on wafer, after separating into independently element, is sealing in resinous encapsulation etc.Use determinator whether each semiconductor element is had the regulation performance and estimate, only will satisfy the semiconductor element of evaluation criterion and peddle as goods.
After encapsulation, carry out under the situation of such evaluation, need to implement the general independently semiconductor element be inserted into the operation of (test head) in the measuring head of determinator one by one, the processing (handling) of element is needed labour and time.In order efficiently to carry out this operation, need to adopt the large-scale transport mechanism that is called as processor (handler).
Relative with it, if under the wafer state before element is separated semiconductor element is estimated, then owing to can estimate majority element effectively, so be the practice easily.Its reason is and since on wafer element each other near and periodic arrangement regularly, so; As long as the probe through making inspection usefulness contacts the mensuration of carrying out characteristic with each element; And after measuring, probe and adjacent element are relatively moved, just can estimate majority element effectively.
Fig. 8 has schematically represented existing common determinator 200 that the property of semiconductor element of wafer state is measured.Determinator 200 possesses: carry platform (stage) 201, probe 202 and 203, voltage application portion 204 and the current measurement portion 205 of putting.Fig. 9 is that expression has been used the property of semiconductor element of determinator 200, especially represented the flow chart of withstand voltage mensuration order.
At first, from the box (cassette) of putting into a plurality of wafers 1 wafer 1 is loaded into to carry and puts (step S201) on the platform 201.Then, carry out the calibration (S211) of wafer.For example; Utilize not shown CCD camera to wait to detect a plurality of collimating marks (specific pattern on the normally predefined wafer of this collimating marks), make according to the consistent mode of orientation of carrying a plurality of semiconductor elements in the moving direction (for example X, Y direction) of putting platform 201 and the wafer 1 and year put platform 201 and rotate (θ direction) in separated setting on the wafer 1.
Then, make to carry according to predefined wafer map (wafer map) and put platform and move, so that probe 202 and 203 is positioned on the semiconductor element of initial determination object (S212).Then, for example make to carry and put platform 201 risings, let the front end of probe 202 and 203 contact (S213) with the electrode pad of semiconductor element.
Subsequently, utilize 204 pairs of voltage application portion probe 202 and 203 or carry and put platform 201 and apply voltage.When voltage is increased, utilize current measurement portion 205 to measure the electric current that flows through, the voltage in the time of will becoming desirable current value is recorded as withstand voltage (S214).
After withstand voltage mensuration finishes, make to carry and put platform 201 and descend (S215), the next element on the wafer 1 is measured (S216, S212～S215).
After last element having been carried out mensuration (S216), unload lower wafer 1 (S217), from box, load next wafer 1 (S210).(S212～S216) carries out withstand voltage mensuration to the semiconductor element of all wafers in the box 1 through carrying out these actions repeatedly.
In recent years, climate warming becomes the problem of attracting attention, and in order to reduce carbon dioxide, needs to adopt the technology of saving the energy.Therefore, the exploitation that is used for employed motors such as hybrid vehicle, electric motor car are carried out the high MOSFET of inversion control and operation voltage and operating current, IGBT, diode, bipolar transistor, JFET, SIT constant power device is in vogue.
For these power devices, withstand voltage is one of important performance, is the project that must estimate.But; Because power device is to have a device withstand voltage more than the hundreds of V mostly, so, if in order to measure withstand voltage between probe or apply high voltage between probe and framework; Then between these parts, will cause atmospheric discharge, and exist the power supply of determinator problem such as to be destroyed.And, exist withstand voltage mensuration by creepage distance, space length and humidity etc. about, be difficult to measure exactly withstand voltage problem.Therefore,, after it being received into encapsulation, then can not estimate, also become the reason that checking efficiency reduces carrying out element to separate even if can not on wafer, check the element that the withstand voltage and voltage endurance of semiconductor element is not enough.
In order to solve such problem, patent documentation 1 discloses the pressure-proof inspection device shown in a kind of Figure 10 (a) and Figure 10 (b).Testing fixture shown in Figure 10 (a) possesses to carry puts platform 302, probe 311P and 312P, and wafer 301 is supported in to carry and puts on the platform 302.The integral body of wafer 301 is insulated solution 351 and covers.Carry put platform 302 and probe 311P and 312P respectively with wafer 351 on collector electrode 313C and grid 311G and the emitter 312E of semiconductor element be electrically connected.Thus, disclose, can measure withstand voltage technology through between them, applying voltage.In addition, the testing fixture shown in Figure 10 (b) possesses the groove 321 that has been full of dielectric 322, is supported in to carry the wafer 301 put on the platform 302 and measure with the state of mass-impregnation in insulating solution 322 that it is withstand voltage.
According to patent documentation 1, through using the pressure-proof inspection device shown in Figure 10 (a) and Figure 10 (b), can be rising to about 10kV about 2000V with the mensuration of pressure-proof inspection device self is withstand voltage in the past.
Patent documentation 1: TOHKEMY 2003-100819 communique
In recent years, the carborundum of continually developing (SiC), gallium nitride broad-band gap (wideband-gap) semi-conducting materials such as (GaN) are compared with silicon, have than its insulation breakdown electric field more than big one magnitude.Therefore, consider that the power device that has used wide bandgap semiconductor materials compares with the power device that has used silicon, the high situation of insulation breakdown electric field of semi-conducting material self is come the withstand voltage structure of design element.
Inventor of the present invention has studied the situation of on wafer, carrying out withstand voltage mensuration to as MOSFET one of power device that uses wide bandgap semiconductor materials, that adopted carborundum, has implemented various experiments.The result finds that in the MOSFET that has adopted carborundum, MOSFET is destroyed under than the withstand voltage low voltage of design.Can think that this is relevant with atmospheric discharge.
In order to prevent atmospheric discharge, to measure withstand voltagely exactly, can consider to use disclosed device in the patent documentation 1, measure withstand voltage scheme.But, in the device shown in Figure 10 of patent documentation 1 (a) and Figure 10 (b),, wafer surface integral body covers because being insulated liquid, so, might be difficult to detect exactly the collimating marks that is arranged on the wafer 301.Therefore, under the situation of the calibration that can not carry out wafer 301 exactly, can't check this wafer 301.
In addition, as such dielectric, patent documentation 1 illustration fluorine class inert liquid.But in fluorine class inert liquid, for example hydrogen fluorine ether that kind is understood (several seconds) generating gasification in the relatively shorter time.Therefore, when whole, also to consider that in the process that the element on the wafer 301 is measured, insulating solution 351 evaporate gradually by insulating solution 351 cover wafers 301 when such shown in Figure 10 (a), in mensuration midway, the situation of insulating solution 351 complete obiterations.
And, withstand voltage for all elements of wafer 301 are measured, need to move to carry and put platform 302.Generally, in order to carry out the mensuration of a plurality of elements at short notice, such determinator can carry with high-speed mobile puts platform.Therefore, when to carry at a high speed when putting platform mobile, in the device shown in Figure 10 (a), insulating solution 351 might be spilt because of year putting the mobile of platform 302.In addition, reducing for insulating solution 351 is not spilt under the situation of carrying the translational speed of putting platform 302, the needed times of element of having measured wafer 301 integral body increase, and that kind can cause insulating solution 351 evaporations as stated.
In addition, under the situation that adopts the device shown in Figure 10 (b), owing to need to carry to put platform 302 mass-impregnations in insulating solution 322, so, cause the determinator scale big, and the device price also increase.
Summary of the invention
The objective of the invention is to, in order to solve at least one problem of such prior art, and the withstand voltage determinator and the withstand voltage assay method that can carry out withstand voltage mensuration to the withstand voltage semiconductor element of height is provided.
Withstand voltage assay method of the present invention is used for the withstand voltage of a plurality of semiconductor elements that is formed on wafer surface measured, comprising: said wafer is fixed to carries the step (A) put platform; Utilize dielectric only cover the part of said wafer surface, promptly cover at least mensuration that a semiconductor element selecting from said a plurality of semiconductor elements is provided with withstand voltage be exposed to the electrode of atmosphere more than one, and make a probe and a said step that contacts with top electrode (B); And to from said one with top electrode and put the withstand voltage step of measuring (C) between two that platform surface selects in said year.
A certain preferred embodiment in, in said step (B), utilize said dielectric to cover a said semiconductor element and surround a said semiconductor element and be exposed to the position line of atmosphere.
A certain preferred embodiment in, said dielectric has the insulating properties higher than atmosphere.
A certain preferred embodiment in, from said a plurality of semiconductor elements, select different semiconductor elements repeatedly, to selected semiconductor element, carry out said step (B) and (C).
A certain preferred embodiment in; Withstand voltage assay method also be included in said step (A) and (B) between; Use is arranged on two above collimating marks of said wafer surface; According to the orientation of the said a plurality of semiconductor elements that the are arranged at said wafer mode consistent, make the step of putting the platform rotation in said year with the movable direction of putting platform in said year.
A certain preferred embodiment in, said step (B) comprising: make the probe and the said step that contacts with top electrode (B1) of a said semiconductor element; With afterwards in said step (B1), utilize dielectric only cover the part of said wafer surface, promptly cover at least be arranged at a said semiconductor element to the withstand voltage step of measuring (B2) that is exposed to the electrode of atmosphere more than.
A certain preferred embodiment in, said step (B) comprising: utilize dielectric only cover the part of said wafer surface, promptly cover at least be arranged at a said semiconductor element to the withstand voltage step of measuring (B3) that is exposed to the electrode of atmosphere more than; With afterwards, make a said step that contacts with top electrode (B4) of popping one's head in a said semiconductor element in said step (B3).
A certain preferred embodiment in, said step (B3) comprising:, make said year and put the step that platform moves near the mode of said probe according to said wafer; With said dielectric is ejected into the step on the wafer.
A certain preferred embodiment in, said semiconductor element is the manufacturing silicon carbide semiconductor power component.
Withstand voltage determinator of the present invention is used for the withstand voltage of a plurality of semiconductor elements that is formed on wafer surface measured, and it possesses: control part; At least one probe; The wafer position control part; It contains carrying of fixing said wafer puts platform; According to instruction from said control part; Make said year and put platform and move,, can contact with said at least one probe so that at the withstand voltage electrode that is exposed to atmosphere more than of the mensuration of a semiconductor element setting of from a plurality of semiconductor elements that are fixed in the wafer of putting platform in said year, selecting; Dielectric ejection portion, it is according to from the instruction of said control part, utilizes dielectric only to cover the part of said wafer surface, promptly cover the said electrode of the semiconductor element of said selection at least; And voltage application portion, it is according to from the instruction of said control part, to from said at least one probe and put withstand voltage mensuration the between two that the platform surface selects in said year.
A certain preferred embodiment in, said dielectric ejection portion comprises the nozzle that has with the approaching ejiction opening of at least one probe.
A certain preferred embodiment in, said dielectric ejection portion according to the semiconductor element that covers said selection with surround a said semiconductor element and be exposed to the mode of the position line of atmosphere, spray said dielectric.
A certain preferred embodiment in, said dielectric has the insulating properties higher than atmosphere.
According to the present invention; Owing to a plurality of semiconductor elements that are formed at wafer being measured when withstand voltage, utilize dielectric to cover the withstand voltage electrode of measuring, and cover wafers is whole to the semiconductor element that becomes determination object; So; Device is changed on a large scale, can prevent atmospheric discharge, thereby it is withstand voltage accurately to measure semiconductor element.
And, owing to need not utilize dielectric cover wafers surface whole, so collimating marks can not be insulated liquid and block and be difficult to and observe.And, because can be before measuring, semiconductor element ejection dielectric only to measuring, so, even under the situation that the mensuration of a wafer takes a long time, also can not make the dielectric evaporation, can prevent atmospheric discharge.
In addition, can also prevent that dielectric carries the mobile vibration that causes put platform and spills because of being accompanied by.
Especially in the withstand voltage mensuration of the power device that constitutes by wide band gap semiconducter, be effective.
Description of drawings
Fig. 1 is the figure of first execution mode of the withstand voltage determinator that the present invention relates to of expression, is the concept nature figure of the structure of expression major part.
Fig. 2 is the module map of bright first execution mode of withstand voltage determinator that the present invention relates to of expression.
Fig. 3 is the vertical view that is illustrated in the state of MOSFET when mensuration is withstand voltage in the withstand voltage determinator shown in Figure 1.
Fig. 4 is the B-B ' profile among Fig. 3.
Fig. 5 is the flow chart of first execution mode of the withstand voltage assay method that the present invention relates to of expression.
Fig. 6 is the IV performance plot of silicon carbide power MOSFET when withstand voltage mensuration that the withstand voltage assay method through first execution mode determines.
Fig. 7 is the vertical view that is illustrated in the state of MOSFET when mensuration is withstand voltage in second execution mode.
Fig. 8 is a sketch map of representing the formation of withstand voltage determinator in the past.
Fig. 9 is a flow chart of representing withstand voltage assay method in the past.
It is respectively the sketch map of representing other formations of withstand voltage determinator in the past that Figure 10 (a) reaches (b).
Figure 11 is a vertical view of measuring the semiconductor element of state in the withstand voltage assay method of representing in the past.
Figure 12 is a profile of representing the structure of semiconductor element in the past.
Figure 13 is the IV performance plot of semiconductor element when withstand voltage mensuration in the past.
Among the figure: 1-wafer, 2-semiconductor element, 9-source electrode pad, 10-gate electrode pad, the 11-position line (scribe line); The 12-interlayer dielectric, 13-diaphragm, 13a-open end, 14-substrate, 15-n N-type semiconductor N drift layer; The 16-p semiconductor regions, 17-depletion layer, 18-source electrode, 19-gate electrode, 21-gate insulating film; The withstand voltage determinator of 50-, 51-wafer position control part, 52-dielectric ejection portion, 53-voltage application portion, 54-amperometric determination portion; 55-control part, 56-nozzle, 57-carry puts platform, and 58,59-probe, the 60-dielectric.
Embodiment
The application's inventor is in the MOSFET that has used carborundum, and MOSFET at length studies in the reason that destruction is taken place than the withstand voltage low voltage of design down.
Figure 11 is the vertical view of wafer state of silicon carbide MOSFET 2 of the application's inventor trial-production.On wafer, dispose a plurality of MOSFET2.Each MOSFET2 possesses source electrode pad 9 and gate electrode pad 10, and the back side of wafer becomes and the public drain electrodes that are connected of a plurality of MOSFET2 (not shown).Each MOSFET2 is separated by the position line 11 with adjacent MOSFET2.Here, the position line is the zone of having removed the interlayer dielectric and the diaphragm of semiconductor surface in order to cut (cutting) element, and therefore, at position line place, semiconductor surface exposes in atmosphere.
MOSFET2 is integrated a plurality of small unit (unit cell), and each unit has constituted MOSFET respectively.In MOSFET2, the grid of each unit, source electrode and drain electrode are connected with the drain electrode of gate electrode pad 10, source electrode pad 9, chip back surface, and the MOSFET that is made up of the unit has constituted the power transistor that is connected in parallel.And, possess at the drain electrode that is arranged at chip back surface and be arranged at the longitudinal type structure of streaming current between the source electrode pad 9 of wafer surface.
Use withstand voltage in the past determinator 200 shown in Figure 8, measured withstand voltage under the MOSFET2 cut-off state of wafer state.Measuring when withstand voltage, the wafer 1 that will be formed with MOSFET2 through vacuum suction etc. is fixed to carry to be put on the platform 201, and probe 202 and 203 is contacted with gate electrode pad 10 and source electrode pad 9.MOSFET2 is for strengthening (enhancement) type, and through grid and source electrode are made as earthing potential, MOSFET2 becomes cut-off state.Therefore, will pop one's head in and 202 and 203 be set at earthing potential.The drain electrode of not shown chip back surface is put platform 201 by being used for fixing carrying of wafer 1, is electrically connected with the voltage application portion 204 and the amperometric determination portion 205 of determinator 200.
When utilizing amperometric determination portion 205 to measure drain current, through voltage application portion 204 the drain voltage gradual slow is increased, the drain voltage when drain current has been surpassed the threshold current of stipulating is defined as withstand voltage.Perhaps, also can replace amperometric determination portion 205, voltage application portion 204 and connect constant-current source, voltage application portion, the drain voltage in the time of will flowing through the drain current of regulation is defined as withstand voltage.
Figure 13 be expression MOSFET2 by the time (grid voltage Vg=0) the figure of IV characteristic of drain current and drain voltage.Designing withstand voltage is 1400V.
Can know that by Figure 13 before drain voltage reached 1100V, drain current hardly flowed.But when drain voltage had reached about 1100V, electric current flowed sharp and has reached 1 μ A.At this moment, the work of the electrical power limit device of IV analyzer makes that applying voltage drop is low to moderate 600V.The rapid increase of electric current is because semiconductor element is destroyed because of atmospheric discharge.When again the IV characteristic of this MOSFET2 having been carried out mensuration, in secondary IV measures, flow through greatly the leakage current (not shown) of several V.Can think that its reason is,, cause temperature to rise with it together, in semiconductor element, form leakage paths thus because the destruction that atmospheric discharge causes is flow through big electric current in carborundum.
When utilizing the ruined MOSFET2 of observation by light microscope, confirmed the destruction at the periphery place of element.Particularly, can observe the sealing ring variable color of diaphragm openend 13a with the periphery of source electrode pad 9 shown in Figure 11, and see that the vestige of fusion has taken place in the AL wiring.
The result of research is that the present inventor is following with the reason inference of atmospheric discharge.Figure 12 is the figure that observes the A-A ' section of MOSFET2 shown in Figure 11 along the direction of arrow.On low-resistance n N-type semiconductor N substrate 14, be formed with high-resistance n N-type semiconductor N drift layer 15, optionally be formed with p semiconductor regions 16 in the inside of drift layer 15.The surface of the p semiconductor regions 16 in the unit forms active electrode 18, and the source electrode 18 of each unit interconnects through the source electrode pad 9 of thick film.Source electrode pad 9 contacts with probe 203 as above-mentioned, and all source electrodes 18 are fixed to earthing potential.
N type semiconductor substrate 14 is fixed to drain potential as drain electrode performance function by the drain electrode that is formed on this back side (backplate) 20.Because generally drain potential is positive voltage, so, the interface of p semiconductor regions 16 and n N-type semiconductor N drift layer 15, be that the pn knot is applied in contrary bias voltage.Therefore, depletion layer 17 spreads expansion in drift layer 15.
There is electric field in depletion layer 17 inside in drift layer 15, produce Potential distribution thus, but do not produce electric field in the zone beyond depletion layer 17, and current potential is identical.That is, the zone beyond the depletion layer 17 of drift layer 15 becomes drain potential.
Surface at drift layer 15 is formed with gate electrode 19 across gate insulating film 21.And, be provided with interlayer dielectric 12 according to the mode of covering grid electrode 19.Source electrode pad 9 is positioned on the interlayer dielectric 12, and via the opening that is arranged at interlayer dielectric 12, source electrode pad 9 is connected with source electrode 18.
On source electrode pad 9, be formed with the diaphragm 13 that mainly constitutes by silicon nitride film or polyimides.For source electrode pad 9 is exposed, diaphragm 13 is provided with the opening by openend 13a regulation.
The position line 11 is the zones that are used for being arranged on a plurality of MOSFET2 cut-outs on the wafer.Gate insulating film 21, interlayer dielectric 12 and diaphragm 13 are not set on the position line 11, and expose in atmosphere on the surface of drift semiconductor layer 15.As stated, because drift layer 15 except depletion layer 17, is identical current potential, so in withstand voltage mensuration process, the surface of the position line 11 also is a drain potential.Source electrode pad 9 is an earthing potential, and the position line 11 is a drain potential, exposes in atmosphere.The electric field that is produced by these potential difference also applies to atmosphere except applying to semiconductor inside.
Therefore; If in withstand voltage mensuration; The insulation breakdown electric field of atmosphere is littler than the insulation breakdown electric field of drift layer 15 and n N-type semiconductor N substrate 14 the distance L till from the openend 13a of diaphragm 13 to the end of the position line 11, then based on the rising of drain potential; Till from the openend 13a of source electrode pad 9 to the end of the position line 11, electric current is by Atmospheric Flow.When flowing this electric current, sharply rise to the temperature on diaphragm 13 surfaces that the atmosphere between the end of the position line 11 contacts with openend 13a.Thus, the component construction between them of drift layer 15 near surfaces forms low-resistance conductivity path because of heat is destroyed, and causes and can not accurately bring into play function as MOSFET2.
Like this, between to source electrode pad 9 and drain electrode pad 20, having applied the discharge that has produced under the high-tension situation by atmosphere, is because under wafer state, the withstand voltage of MOSFET2 measured.Generally, because each MOSFET2 is incorporated in the encapsulation, the surperficial packed resin of MOSFET2 covers, so electric current can not flow through atmosphere like this.
Table 1 has been represented the insulation breakdown electric field of silicon, carborundum, atmosphere and potting resin.
[table 1]
| Material | Silicon | Carborundum | Atmosphere | Potting resin (cresols novolaks based material) |
| Insulation breakdown electric field (MV/cm) | ～0.3 | ～3 | 0.06 | 0.01～0.14 |
As shown in table 1, the insulation breakdown electric field of carborundum than the big one magnitude of silicon about.Though not expression in table 1, the insulation breakdown electric field of known gallium nitride is also than about the big one magnitude of silicon.Like this, because wide band gap semiconducter is compared with silicon, the insulation breakdown electric field is big about 10 times, so, also can guarantee the withstand voltage of element even reduce size of component in theory.
But, the insulation breakdown electric field of atmosphere than the little one magnitude of silicon about.Therefore; Through semi-conducting material is changed to carborundum from silicon; Can realize more small-sized, withstand voltage higher semiconductor element; But under element surface and situation that atmosphere contacts,, become the problem in the withstand voltage mensuration of semiconductor element under the wafer state by the discharge that the withstand voltage mensuration of semiconductor element causes by atmosphere.
Especially under wafer state, the position line that exists the surface of semiconductor substrate to expose.Therefore, as Figure 11 and shown in Figure 12 use the wide band gap semiconducter manufacturing semiconductor element, reduce component size more, the distance L of the open end 13a of the end of the position line 11 and source electrode pad 9 is short more, and the atmospheric discharge in the withstand voltage mensuration takes place easily.
Therefore, under the position line 11 situation relevant, cover the position line 11, can think that the position line 11 can not be exposed in the atmosphere, can prevent above-mentioned atmospheric discharge through in withstand voltage mensuration, utilizing dielectric with atmospheric discharge.
Among the MOSFET2 shown in Figure 11, gate electrode pad 10 is set to idiostatic with source electrode pad 9 in withstand voltage mensuration process.Therefore, between these electrode pads, do not produce high potential difference, atmospheric discharge can not take place yet.But, for semiconductor element (the for example power MOSFET of horizontal type), can also think in withstand voltage mensuration, withstand voltage through 2 determination of electrode that are formed on wafer surface.Under this situation, might be via the air flow overcurrent between two electrodes refer to.In this case, be insulated liquid and cover if be exposed in 2 electrodes of atmosphere at least one electrode, then since at least one in 2 electrodes be not exposed in the atmosphere, so, can prevent atmospheric discharge.
That is, under wafer state, measure under the withstand voltage situation of semiconductor element,, can suppress the generation of above-mentioned atmospheric discharge through utilizing dielectric withstand voltage being exposed to the electrode in the atmosphere more than one or being exposed to the position line 11 in the atmosphere of overlay measurement at least.Do not need as patent documentation 1 is disclosed, to utilize the whole surface of dielectric cover wafers.And dielectric is therefore as long as dropped onto determined element before measuring.
The problem, dielectric that thus, can also solve the calibration difficulties of wafer puts because of carrying that moving of platform spilt or dielectric evaporates caused problem in mensuration.According to such thinking, the present inventor has invented the withstand voltage determinator and the withstand voltage assay method of following detailed description.
(first execution mode)
Below, with reference to accompanying drawing, the withstand voltage determinator that the present invention relates to and the execution mode of withstand voltage assay method are described.
Fig. 1 has schematically represented the major part of first execution mode of withstand voltage determinator of the present invention.And Fig. 2 is the block diagram of the formation of expression first execution mode.The withstand voltage determinator 50 of this execution mode possesses: wafer position control part 51, dielectric ejection portion 52, voltage application portion 53, amperometric determination portion 54, control part 55, probe 58 and 59.54 pairs of wafer position control parts 51 of control part, dielectric ejection portion 52, voltage application portion 53 and amperometric determination portion 54 control.
In this execution mode,, measure withstand voltage to a plurality of vertical formula power MOSFET 2 that is produced on the wafer 1 as semiconductor element.Usually, the device that the semiconductor device of wafer state is checked is called as probe, according to the semiconductor element of checking, except withstand voltage, can also check various element characteristics such as threshold voltage, conducting resistance, positive direction and opposite direction I-V characteristic.Withstand voltage determinator of the present invention can be assembled in such probe rightly.
Wafer position control part 51 comprises carrying puts platform 57.Wafer position control part 51 for example is fixed to wafer 1 to carry through absorption and puts on the platform 57 according to the instruction from control part 55.Carry put platform 57 can according to from the instruction of control part 55, be control signal, that kind for example as shown in Figure 1 moves axially to X, Y, Z three.And, carry and to put platform 57 and can in X-Y plane, rotate along the θ direction.
Fig. 3 is formed in the vertical view of a plurality of MOSFET2 on the wafer 1.As illustrated with reference to Figure 11, each MOSFET2 possesses source electrode pad 9 and gate electrode pad 10, and the back side of wafer becomes and the public drain electrodes that are connected of a plurality of MOSFET2 (not shown).Each MOSFET2 is separated by the position line 11 with adjacent MOSFET2.
MOSFET2 comprises a plurality of unit, and each unit has constituted MOSFET respectively.In MOSFET2, the grid of each unit, source electrode and drain electrode are connected with gate electrode pad 10, source electrode pad 9, drain electrode, and the MOSFET that is made up of the unit has constituted the power transistor that is connected in parallel.And MOSFET2 possesses at the drain electrode that is arranged at chip back surface and is arranged at the longitudinal type structure of streaming current between the source electrode pad 9 of wafer surface.
The front end that probe 58 and 59 is configured to separately contacts with gate electrode pad 10 and source electrode pad 9.Carry the surface of putting platform 57 and for example be covered, be electrically connected with the drain electrode that is arranged at chip back surface by conductors such as gold.Probe 58 and 59 and carry the surface put platform 57 and be connected with the withstand voltage determination part that comprises voltage application portion 53 and amperometric determination portion 54.Based on the instruction of control part 55, probe 58 and 59 is fixed to earthing potential, carries the surface of putting platform 57 and is applied in drain voltage.
Fig. 4 has represented the B-B ' section of MOSFET2 shown in Figure 3.If as Fig. 3 and shown in Figure 4 concise and to the point describing; Then for the dielectric that is sprayed 60; According among a plurality of MOSFET2 on being formed at wafer 1 from now in the mensuration with determined MOSFET2; The mode of atmospheric discharge does not take place, and only covers the MOSFET2 as the part on the surface of wafer 1 by dielectric 60.Particularly, by dielectric 60 covered at least be arranged at the MOSFET2 that will measure from now on to the withstand voltage electrode of measuring that is exposed to atmosphere more than.Under the situation of this execution mode, by dielectric 60 covering source electrode pad 9 and gate electrode pads 10.More preferably; According to electrode pad 9 and gate electrode pad 10 and locate in the source; With the mode that the position line that is exposed to atmosphere 11 that surrounds the MOSFET2 (with dashed lines 24 expressions) that will measure is from now on covered by dielectric 60 fully, adjust the amount of dielectric 60.For example, be under the situation about 3mm * 3mm in the size of the periphery of the position line 11, the amount of dielectric 60 is about 1～2ml.The more preferably end setover line 11 of dielectric 60 and arrive adjacent element.Thus, can be insulated liquid 60 reliably fully as the MOSFET2 of determination object and the position line 11 that surrounds it covers.As long as satisfied such condition, then dielectric 60 can also cover and be positioned at the adjacent MOSFET2 of MOSFET2 that locates.
Can also use the index of insulation resistance as the insulating properties of expression dielectric.The insulation resistance is defined by the voltage that can between the electrode in the gap that is provided with 2.54mm, apply.The insulation resistance of the 0.18MV/cm of above-mentioned Off ロ リ Na one ト FC40 is 46kV/2.54mm.And also has about 6 times insulation resistance of this atmosphere of 40kV/2.54mm as the ガ Le デ Application (registered trade mark) of the ソ Le ベ イ ソ レ Network シ ス カ manufactured of PFPE.
Using under the situation of fluorine class inert fluid as dielectric 60, because viscosity is low, so be difficult to generally that adopting exerts pressure and adjust the distributor of the type of spray volume.Under this situation, the preferred allocation device possesses air valve, controls ejection through the switching of valve.Air valve opens and closes needle valve through the pressure of air, sprays quantitative liquid.Air is supplied with from dispenser controller.Dispenser controller is according to from the triggering signal of control part 55, with predefined pressure and time to the needle valve air supply.Through adjusting this pressure and time, can adjust spray volume.Low viscous liquid is difficult to long propagation, preferably makes its whereabouts naturally directly over the MOSFET2 that should measure.Therefore, preferred nozzle 56 be positioned at the MOSFET2 that measure roughly directly over.More specifically, in order to make from the quantitative dielectrics 60 of the ejection integral body that can cover the MOSFET2 that measure naturally and surround its position line 11 of nozzle 56, preferred nozzle 56 roughly is arranged in the MOSFET2 that measure in the heart.
Then, with reference to Fig. 1～Fig. 4 and Fig. 5, the withstand voltage assay method that this execution mode is related to describes.
At first, from Fig. 1, take out wafer 1 in the not shown wafer case, it is loaded into to carry puts (S101) on the platform 57.
Then, carry out the calibration of wafer 1.Use not shown CCD camera, read on the wafer 1 more than two away from collimating marks, confirm the orientation of wafer 1 in X-Y plane that is loaded.According to the orientation of confirming, according to the direction of the arrangement of a plurality of MOSFET2 that are formed at wafer 1, with carry the consistent mode of moving direction of putting platform 57, make and year put platform 57 and rotate (S102) to the θ direction.
And; According to coordinate and the mensuration order of each MOSFET2 that is stored in control part 55 in advance on wafer 1; And according to control signal from control part 55; Make to carry by wafer position control part 51 and put platform 57 and move, make MOSFET2 move to locate (S103) that probe 58 and 59 can contact by the appointment of mensuration order.
Then, according to the instruction of control part 55, dielectric ejection portion 52 is ejected into dielectric 60 on the MOSFET2 that locates that is positioned at wafer 1.As stated, covered the withstand voltage electrode that is exposed to atmosphere more than of mensuration that is arranged in the MOSFET2 that locates at least by dielectric 60.Preferably covered fully and be positioned at the MOSFET2 that locates and surround it and be exposed to the position line 11 (S104) of atmosphere by dielectric 60.
Then, put platform 57 along the rising of Z direction, let the front end of probe 58 and 59 contact (S105) with gate electrode pad 10 and the source electrode pad 9 of the MOSFET2 that is insulated liquid 60 coverings respectively through making to carry.Gate electrode pad 10 and source electrode pad 9 are fixed to earthing potential by probe 58 and 59 respectively.Also can be as stated, at ejection dielectric 60 (S104) before, make probe 58 and 59 contact (S105) with gate electrode pad 10 and source electrode pad 9.
Then, carry out withstand voltage mensuration (S106).Control part 23 sends to amperometric determination portion 54 and voltage determination 53 as withstand voltage determination part with control signal; Measure by amperometric determination portion 54 carry put the electric current (it becomes the drain current of MOSFET2) that flows through in the platform 57 in, make by voltage application portion 53 and to carry the drain potential of putting platform 57 and slowly increase.Drain voltage when drain current is surpassed threshold value (for example 1mA) is as withstand voltage, and the voltage that the voltage application portion 53 of 23 pairs of this moments of control part is applied is stored.For example drain voltage applies as long as rise with the speed about 50V/s.
After withstand voltage mensuration finished, wafer position control part 51 made to carry and puts platform 57 and descend, and made probe 58 and 59 leave (S107) from gate electrode pad 10 and source electrode pad 9 thus.
If the MOSFET2 that measured just now is not the last MOSFET2 (S108) that should measure on the wafer 1; Then according to the instruction of control part 23; Make to carry by wafer position control part 51 and put platform 57 and move, so that next MOSFET2 by the appointment of mensuration order comes locate (S103).Subsequently, carry out the leaving of ejection (S104), probe 58 and 59 contact (S105), withstand voltage mensuration (S106), probe 58 and 59 (S107) of dielectric 60 repeatedly.
When the MOSFET2 that is measured is the last MOSFET2 with the appointment of mensuration order (S109), finish the mensuration of this wafer 1, wafer is unloaded.Load ensuing other wafers 1 then, this wafer 1 is carried out above-mentioned step (S101～S109) repeatedly.The last wafer of in box, taking in 1 mensuration that is through with then finishes whole steps.Wherein,, for example can brush nitrogen, dielectric 60 is removed from the surface of wafer 1 when measuring the back when the remained on surface of wafer 1 has dielectric 60.
Fig. 6 has represented to use Fig. 1 and withstand voltage determinator shown in Figure 2, through the withstand voltage assay method of above-mentioned execution mode, to the withstand voltage result who measures that carried out of silicon carbide power MOSFET.The IV characteristic (relation of drain current and drain voltage) of having represented 12 silicon carbide power MOSFET among Fig. 6.Under situation in the past, shown in figure 13, because atmospheric discharge takes place, because of the resistance of the ruined element of discharge sharply reduces, so, show the IV characteristic that voltage sharply reduces.And, if measure once more, then can not reproduce identical IV characteristic, cause in the dirty overcurrent of low voltage.
Withstand voltage assay method according to this execution mode can know that even electric current begins to flow, voltage does not descend yet, and the inner so-called avalanche current of semiconductor is flowing.And, even measure once more, also can reproducibility obtain identical IV characteristic well.Therefore, atmospheric discharge ground can not take place measure the withstand voltage of original semiconductor element.Wherein, in this is measured, the threshold value of drain current is made as 1 μ A.
Like this, according to the present invention, owing to covered the withstand voltage electrode of measuring by dielectric at least to determined semiconductor element, so, in withstand voltage mensuration atmospheric discharge can not take place, can under wafer state, measure the withstand voltage of each semiconductor element.And, because cutting and separating does not become chip status and measures with regularly arranged state on wafer, so can realize measuring efficiently.
And, since in the present invention not with the wafer mass-impregnation in dielectric, so, do not need to carry the large-scale groove of putting the platform mass-impregnation, as long as append small-sized dielectric ejection portion such as distributor.
In addition, because not by the whole surface of dielectric cover wafers, and needed zone when only having covered each measuring element by dielectric, so, can not put platform and move dielectric is spilt because of carrying.And, owing to before withstand voltage mensuration, dielectric is supplied on the wafer, so dielectric can not evaporate when withstand voltage mensuration.
And, because being insulated liquid, the collimating marks of wafer do not cover, so, can carry out the contraposition of wafer in the withstand voltage determinator reliably.
In addition, in this execution mode, Yi Bian withstand voltage determination part 55 utilizes voltage application portion 53 to apply drain voltage, Yi Bian measure drain current through amperometric determination portion 54.But withstand voltage determination part 55 also can possess electric current and apply portion's (for example constant-current source) and voltage determination portion, and the portion of applying at constant current through electric current, and measures the drain voltage of this moment, with it as withstand voltage.Withstand voltage determination part 55 can also possess electric current and apply portion and voltage application portion.
And, in this execution mode, make to carry through wafer position control part 51 and put platform 57 and move, make the electrode pad that is formed on the semiconductor element on the wafer 1 contact with probe 58 and 59, and the approaching nozzle 56 that sprays dielectric 60.But, also can make probe 58 and 59 and nozzle 56 move to the position of semiconductor element that should be determined, let probe 58 and 59 contact with the electrode pad of semiconductor element.
(second execution mode)
Below, with reference to accompanying drawing, the withstand voltage determinator that the present invention relates to and other execution modes of withstand voltage assay method are described.
This execution mode is that with the difference of first execution mode measure withstand voltage semiconductor element is the horizontal type power MOSFET.In the horizontal type power MOSFET, be formed with gate electrode pad, drain electrode pad and source electrode pad on the surface of wafer.Therefore, under the withstand voltage situation about measuring to the horizontal type power MOSFET, withstand voltage determinator possesses 3 probes.
Fig. 7 is being fixed in the vertical view that carries a plurality of horizontal type power MOSFETs 2 ' that form on the wafer 1 of putting platform of withstand voltage determinator.Each horizontal type power MOSFET 2 ' possesses: gate electrode pad 42, source electrode pad 44 and drain electrode pad 46.The withstand voltage determinator of this execution mode possesses probe 58 and 59,62, and probe 58 and 59,62 contacts with gate electrode pad 42, source electrode pad 44, drain electrode pad 46 respectively.Dielectric 60 has covered the withstand voltage electrode of measuring that is exposed to atmosphere more than to the MOSFET2 ' that should measure.
To pop one's head on one side and 58 and 59 be fixed as earthing potential; The electric current (source current) that flows in 59 to popping one's head in or the electric current (drain current) that flows in 62 of popping one's head in are measured; On one side 62 apply voltage (drain voltage) to popping one's head in, probe 59 and the voltage (drain electrode-source voltage) between 62 of popping one's head in were as withstand voltage when drain current or source current had been reached a certain setting.The formation of other withstand voltage determinator and withstand voltage determination step are identical with first execution mode.
According to this execution mode, same with first execution mode, can measure the withstand voltage of horizontal type power MOSFET exactly with wafer state.Therefore, can obtain the effect same with first execution mode.
More than, in first execution mode and second execution mode, the withstand voltage example that is determined as with vertical formula MOSFET and horizontal type MOSFET describes the present invention.But the invention is not restricted to these semiconductor elements, can also measure various semiconductor elements with wafer state.For example, under withstand voltage situation about measuring, use a probe, for example apply voltage between the platform with year putting at probe to a plurality of Schottky diodes of being formed at wafer.Under this situation, dielectric ejection portion has only covered the Schottky diode measured, has been the part of wafer surface through dielectric.Therefore, dielectric can not evaporate during withstand voltage mensuration, and dielectric can not put the mobile vibration that causes of platform and spills the atmospheric discharge in the time of can preventing withstand voltage mensuration because of being accompanied by to carry.Thereby, can measure Schottky diode withstand voltage of wafer state exactly.Equally, also can suitably adopt the present invention to IGBT, bipolar transistor, JFET, SIT constant power device.
In addition, in first execution mode and second execution mode, be that example describes the present invention with the silicon carbide semiconductor device.Because as stated; In the power semiconductor that constitutes by other wide band gap semiconducter such as GaN; Also produce same problem, so the present invention can also be preferably uses in the power semiconductor that is made up of other wide band gap semiconducter such as GaN along with reducing of chip size.
Utilizability in the industry
According to the present invention, atmospheric discharge ground can not take place the various power devices that are in wafer state are efficiently carried out withstand voltage mensuration.Therefore, the present invention preferably uses in the inspection operation with the withstand voltage power device of height.
Claims (13)
1. a withstand voltage assay method is used for the withstand voltage of a plurality of semiconductor elements that is formed on wafer surface measured, comprising:
Said wafer is fixed to carries the step (A) put platform;
Utilize dielectric only cover the part of said wafer surface, promptly cover at least mensuration that a semiconductor element selecting from said a plurality of semiconductor elements is provided with withstand voltage be exposed to the electrode of atmosphere more than one, and make a probe and a said step that contacts with top electrode (B); With
To from said one with top electrode and put the withstand voltage step of measuring (C) between two that platform surface selects in said year.
2. withstand voltage assay method according to claim 1 is characterized in that,
In said step (B), utilize said dielectric to cover a said semiconductor element and surround a said semiconductor element and be exposed to the position line of atmosphere.
3. withstand voltage assay method according to claim 1 and 2 is characterized in that,
Said dielectric has the insulating properties higher than atmosphere.
4. according to any described withstand voltage assay method in the claim 1～3, it is characterized in that,
From said a plurality of semiconductor elements, select different semiconductor elements repeatedly,, carry out said step (B) and reach (C) selected semiconductor element.
5. according to any described withstand voltage assay method in the claim 1～4, it is characterized in that,
Also be included in said step (A) and (B) between; Use is arranged on two above collimating marks of said wafer surface; According to the orientation of the said a plurality of semiconductor elements that the are arranged at said wafer mode consistent, make the step of putting the platform rotation in said year with the movable direction of putting platform in said year.
6. withstand voltage assay method according to claim 5 is characterized in that,
Said step (B) comprising: make a said step that contacts with top electrode (B1) of popping one's head in a said semiconductor element; With
In said step (B1) afterwards, utilize dielectric only cover the part of said wafer surface, promptly cover at least be arranged at a said semiconductor element to the withstand voltage step of measuring (B2) that is exposed to the electrode of atmosphere more than.
7. withstand voltage assay method according to claim 5 is characterized in that,
Said step (B) comprising: utilize dielectric only cover the part of said wafer surface, promptly cover at least be arranged at a said semiconductor element to the withstand voltage step of measuring (B3) that is exposed to the electrode of atmosphere more than; With
In said step (B3) afterwards, make a said step that contacts with top electrode (B4) of popping one's head in a said semiconductor element.
8. withstand voltage assay method according to claim 7 is characterized in that,
Said step (B3) comprising: according to the mode of said wafer near said probe, make said year and put the step that platform moves; With
Said dielectric is ejected into the step on the wafer.
9. according to any described withstand voltage assay method in the claim 1～8, it is characterized in that,
Said semiconductor element is the manufacturing silicon carbide semiconductor power component.
10. a withstand voltage determinator is used for the withstand voltage of a plurality of semiconductor elements that is formed on wafer surface measured, and it possesses:
Control part;
At least one probe;
The wafer position control part; It contains carrying of fixing said wafer puts platform; According to instruction from said control part; Make said year and put platform and move,, can contact with said at least one probe so that at the withstand voltage electrode that is exposed to atmosphere more than of the mensuration of a semiconductor element setting of from a plurality of semiconductor elements that are fixed in the wafer of putting platform in said year, selecting;
Dielectric ejection portion, it is according to from the instruction of said control part, utilizes dielectric only to cover the part of said wafer surface, promptly cover the said electrode of the semiconductor element of said selection at least; With
Voltage application portion, it is according to from the instruction of said control part, to from said at least one probe and put withstand voltage mensuration the between two that the platform surface selects in said year.
11. withstand voltage determinator according to claim 10 is characterized in that,
Said dielectric ejection portion comprises the nozzle that has with the approaching ejiction opening of at least one probe.
12. withstand voltage determinator according to claim 11 is characterized in that,
Said dielectric ejection portion is according to a semiconductor element that covers said selection and surround a said semiconductor element and be exposed to the mode of the position line of atmosphere, sprays said dielectric.
13., it is characterized in that said dielectric has the insulating properties higher than atmosphere according to any described withstand voltage determinator in the claim 10～12.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
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| JP2008210412 | 2008-08-19 | ||
| JP2008-210412 | 2008-08-19 | ||
| PCT/JP2009/002088 WO2010021070A1 (en) | 2008-08-19 | 2009-05-13 | Apparatus and method for measuring withstand voltage of semiconductor element |
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| CN102741992A true CN102741992A (en) | 2012-10-17 |
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| JP (1) | JP4482061B2 (en) |
| CN (1) | CN102741992A (en) |
| WO (1) | WO2010021070A1 (en) |
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| JPS6233433A (en) * | 1985-08-07 | 1987-02-13 | Toshiba Corp | Manufacture of high withstand voltage semiconductor element |
| JP2000206149A (en) * | 1999-01-14 | 2000-07-28 | Sony Corp | Probe card and method for testing electric characteristic of body to be tested |
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| JP2003130889A (en) * | 2001-10-29 | 2003-05-08 | Vector Semicon Kk | Semiconductor device inspection device and method |
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2009
- 2009-05-13 CN CN2009801007518A patent/CN102741992A/en active Pending
- 2009-05-13 JP JP2009541665A patent/JP4482061B2/en not_active Expired - Fee Related
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Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2010021070A1 (en) | 2012-01-26 |
| WO2010021070A1 (en) | 2010-02-25 |
| JP4482061B2 (en) | 2010-06-16 |
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