CN102739385A - Method and system for logic signal synchronization and synthesis - Google Patents
Method and system for logic signal synchronization and synthesis Download PDFInfo
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- CN102739385A CN102739385A CN201110082083XA CN201110082083A CN102739385A CN 102739385 A CN102739385 A CN 102739385A CN 201110082083X A CN201110082083X A CN 201110082083XA CN 201110082083 A CN201110082083 A CN 201110082083A CN 102739385 A CN102739385 A CN 102739385A
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Abstract
The invention provides a method and a system for logic signal synchronization and synthesis. The method comprises the steps: firstly, interrupt signals of all members in a parallel system are synchronized by using periodic interrupt signals of a host; and then, logical serial signals are transmitted to all slaves by using the host and frame headers of all the members are synchronized under interrupt signal synchronization; and finally, all the members receive and transmit logic signals synchronously under the premise of interrupt signal and frame header synchronization, thus realizing synchronization of logic signals in the parallel system. Instead of using either a CAN bus or a complex hardware programmable logic gate array, the method for logic signal synchronization provided by the invention uses resource of the parallel system itself as well as simple wires and/or chips to realize synchronization of logic signals in the whole system, and thus instantaneity of the system can be guaranteed and cost can be reduced.
Description
Technical field
The present invention relates to the adverser control technology field, particularly a kind of logical signal reaches synthetic method synchronously and reaches synthetic method and system synchronously.
Background technology
It is that system provides continual power supply that uninterrupted power supply (UPS, uninterruptible power system) is used for when system cut-off.UPS mainly is made up of several parts such as rectifier, storage battery, inverter and static switches.
In order to increase the carrying load ability of UPS, normal ac output end with a plurality of inverters is connected in parallel and is electric.If when one of them inverter or other module failures, other normal modules of parallel connection can work on, thereby are electric.
Because inverter is connected in parallel and is electric, therefore need the behavior of each inverter of parallel connection to be consistent.This behavior consistent is mainly two aspects: the first, and logic behavior is consistent; The second, performance is consistent.
Logic behavior is meant each module under specific operation or initial conditions, the output mode of its arbitration or decision, and for example, the arbitration output mode is that inverter power supply or bypass power supply or inverter and bypass are not all supplied power.If it is inverter side power supply that the logic behavior of a module is arranged, and the logic behavior of module is a bypass power supply in addition, if this inconsistent logic behavior is not coordinated, the situation that inverter and bypass (possibly be electrical network) directly link to each other will appear.If the information of voltage of inverter and bypass is different, then can damages the device in inverter or the bypass, even cause system crash or paralysis.
Therefore, need manage, and then produce the logical signal of parallel system the logic behavior of each module in the parallel operation system.
Can come pass logic signals through the CAN bus in the prior art, but CAN bus transfer logical signal receives the quantitative limitation of parallel operation number of members.Because each member's of parallel system logical signal all need upgrade on the CAN bus, like this when the number of members of parallel system more for a long time, it is also longer to upgrade the time that once needs, therefore, the many needs in time state of response can't be realized switching.
Can also pass through the hardware pass logic signals in the prior art, it is reliable to bring into play the logical signal transmission like this, the advantage that the response time is short.But the hardware of logical signal relates to the signal Synchronization problem, needs complicated logic programmable gate array (CPLD or FPGA) to realize usually.The complicated hardware system causes cost too high.
Summary of the invention
The technical problem that the present invention will solve provides a kind of logical signal and reaches synthetic method method and system synchronously, both can guarantee the real-time of logical signal, can reduce hardware cost again.
The present invention provides a kind of logical signal to reach synthetic method synchronously, may further comprise the steps:
Main frame in the parallel system sends the cycle interruption signal and gives all slaves, so that the cycle interruption signal Synchronization of the cycle interruption signal of main frame and all slaves;
When the cycle interruption signal Synchronization of the cycle interruption signal of main frame in the parallel system and all slaves, main frame sends the logical synchronization signal to all slaves, so that the frame head of main frame and slave is synchronous;
After the frame head of main frame and slave was synchronous, main frame all sent the logic serial signal with all slaves and carries out logical AND;
Said main frame and slave receive the result of the logical AND of said logic serial signal, and said result is carried out logic analysis, obtain the integrated logic signal of parallel system and carry out synchronous.
Preferably, main frame sends the logical synchronization signal to all slaves, so that the frame head of main frame and slave is synchronous, is specially:
Main frame sends the logical synchronization signal of predetermined interrupt cycle to all slaves; In the next interrupt cycle that the transmission of logical synchronization signal finishes, main frame detects the logical synchronization signal with all slaves and sends the sign that finishes; Detect in the next interrupt cycle of sending the sign that finishes, the frame head of main frame and slave is synchronous.
Preferably, said main frame all sends the logic serial signal with all slaves and carries out logical AND, is specially:
Said main frame and all slaves all send logic serial signal to self corresponding line and chip perhaps to self corresponding line or chip;
Said line and chip or line or chip to all logic serial signals carry out output logic behind the logical AND and the result.
Preferably; When the main frame in the parallel system and slave include primary processor and coprocessor; The transmission of main frame primary processor is given main frame coprocessor and all slave coprocessors with the square-wave signal of the cycle interruption signal Synchronization of said main frame primary processor, so that the cycle interruption signal of all coprocessors is consistent with the cycle interruption signal of main frame primary processor;
When the cycle interruption signal of all coprocessors was consistent with the cycle interruption signal of main frame primary processor, the main frame coprocessor sent the logical synchronization signal to all slave coprocessors, so that the frame head of main frame coprocessor and slave coprocessor is synchronous;
When main frame coprocessor and slave coprocessor frame head synchronously after, the main frame coprocessor all sends the logic serial signal with all slave coprocessors and carries out logical AND;
Said main frame coprocessor and slave coprocessor are accepted the result of the logical AND of said logic serial signal, and said result is carried out logic analysis, and the integrated logic signal that obtains parallel system carries out synchronously.
Preferably, the cycle interruption signal of said primary processor is PWM interrupt signal or timer interrupt signal.
The present invention also provides a kind of logical signal to reach synthetic system synchronously, is applied to comprise the parallel system of main frame, the first logical AND device and at least one slave;
Said main frame is used for sending the cycle interruption signal to all slaves; After the cycle interruption signal Synchronization of main frame and slave, also be used for sending the logical synchronization signal to all slaves; After the frame head of main frame and slave was synchronous, said main frame was used to send logic serial signal to said logical AND device;
Said slave is used for making according to the cycle interruption signal that said main frame sends the cycle interruption signal Synchronization of self cycle interruption signal and main frame; The logical synchronization signal that sends according to said main frame makes the frame head of frame head and main frame of self synchronous; After the frame head of main frame and slave was synchronous, said slave sent logic serial signal to the said first logical AND device;
The said first logical AND device is used for all logic serial signals that receive are carried out logical AND, and the result of logical AND is sent to said main frame and all slaves;
Said main frame all carries out logic analysis to the result of said logical AND with all slaves, obtains the integrated logic signal of parallel system and carries out synchronous.
Preferably, said main frame comprises the logical synchronization signal transmitting unit, is used for sending to all slaves the said logical synchronization signal of predetermined interrupt cycle.
Preferably, each slave comprises logical synchronization signal receiving unit, detecting unit and frame head lock unit;
Said logical synchronization signal receiving unit is used to receive the logical synchronization signal that main frame sends;
Said detecting unit is used for sending the next interrupt cycle that finishes when said logical synchronization signal, is used to detect the logical synchronization signal and sends the sign that finishes;
Said frame head lock unit when said detection is sent the sign that finishes to the logical synchronization signal after, is used for the frame head of the frame head of slave and main frame synchronous.
Preferably, said logical AND device is line and chip, perhaps, and line or chip.
Preferably, also comprise the second logical AND device; Said main frame includes primary processor and coprocessor with all slaves;
Said main frame primary processor; Be used for to main frame coprocessor and the square-wave signal of all slave coprocessors transmissions, so that the cycle interruption signal of all coprocessors is consistent with the cycle interruption signal of main frame primary processor with the cycle interruption signal Synchronization of main frame primary processor;
Said main frame coprocessor, when all coprocessor cycle interruption signals with after the cycle interruption signal of main frame primary processor is consistent, be used for sending the logical synchronization signal to all slave coprocessors; After frame head is synchronous, be used for sending the logic serial signal to the second logical AND device;
Said slave coprocessor after frame head is synchronous, is used for sending the logic serial signal to the second logical AND device;
The said second logical AND device is used for the logic serial signal of main frame coprocessor transmission and the logic serial signal of slave coprocessor transmission are carried out logical AND, and the result of logical AND is sent to main frame coprocessor and slave coprocessor;
Said main frame coprocessor and slave coprocessor carry out logic analysis to the result of said logical AND, obtain the integrated logic signal of parallel system and carry out synchronous.
Preferably, the cycle interruption signal of said primary processor is PWM interrupt signal or timer interrupt signal.
Compared with prior art, the present invention has the following advantages:
The logical signal that present embodiment provides reaches synthetic method and system synchronously; At first utilize the cycle interruption signal of main frame, all members' in the parallel system interrupt signal is synchronous, in interrupt signal synchronously down; It is synchronous to the frame head that all slaves carry out all members to utilize main frame to send the logic serial signal; Under the synchronous prerequisite of interrupt signal and frame head, all members just can carry out the synchronous transmitting-receiving of logical signal like this, realize parallel system logical signal synchronously.Because logical signal method for synchronous provided by the invention had not both utilized the CAN bus; Do not utilize the complicated hardware programmable gate array again; But utilized parallel system its other resources and simple line and chip or line or chip to realize logical signal synchronous of whole system, can guarantee that the real-time of system can reduce cost again.
Description of drawings
Fig. 1 is that logical signal reaches synthetic method embodiment one flow chart synchronously in the uninterrupted power supply provided by the invention;
Fig. 2 is the sketch map of parallel system provided by the invention;
Fig. 3 is the oscillogram of the main signal that provides of the embodiment of the invention one;
Fig. 4 is the sketch map of the synchronous parallel system of the logical signal that has a redundancy feature provided by the invention;
Fig. 5 is the oscillogram of each corresponding signal of Fig. 4;
Fig. 6 is that logical signal provided by the invention reaches synthetic system embodiment one sketch map synchronously;
Fig. 7 is the sketch map of main frame provided by the invention;
Fig. 8 is the sketch map of slave provided by the invention;
Fig. 9 is system embodiment two sketch mapes provided by the invention.
Embodiment
For those skilled in the art can be understood and embodiment of the present invention better, at first introduce several technical terms below.
Parallel system is meant the system that a plurality of members are connected in parallel, and wherein has a member to be main frame, and other members are slave.
The redundancy of logical signal is meant that the transmission of logical signal has two-way in the parallel system, and two-way backups each other, and when wherein one the road when going wrong, other one the tunnel carries out work as usual.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Referring to Fig. 1, this figure is that logical signal reaches synthetic method embodiment one flow chart synchronously in the uninterrupted power supply provided by the invention.
Logical signal reaches synthetic method synchronously in the uninterrupted power supply that present embodiment provides, and may further comprise the steps:
S101: the main frame in the parallel system sends the cycle interruption signal and gives all slaves, so that the cycle interruption signal Synchronization of the cycle interruption signal of main frame and all slaves;
Have only one tunnel high frequency synchronization signal in the parallel system, this high frequency synchronization signal is produced by main frame.The high frequency synchronization signal of main frame is carried out cycle interruption signals all in the parallel system synchronously, and the moment that the cycle interruption in the whole like this ups system produces just can be consistent.
S102: when the cycle interruption signal Synchronization of the cycle interruption signal of main frame in the parallel system and all slaves, main frame sends the logical synchronization signal to all slaves, so that the frame head of main frame and slave is synchronous;
In the cycle interruption of unanimity, main frame is consistent the frame head of all slaves and the frame head of oneself through sending the logical synchronization signal.For the line of subsequent logic serial signal with or line or prepare.
S103: after the frame head of main frame and slave was synchronous, after the frame head of main frame and slave was synchronous, main frame all sent the logic serial signal with all slaves and carries out logical AND;
S104: said main frame and slave receive the result of the logical AND of said logic serial signal, and said result is carried out logic analysis, obtain the integrated logic signal of parallel system.
Logic serial signal to all members in the parallel system (main frame and slave) carries out logical, and the result of logical is sent to each member.
The logical signal that present embodiment provides reaches synthetic method synchronously; At first utilize the cycle interruption signal of main frame, all members' in the parallel system interrupt signal is synchronous, in interrupt signal synchronously down; It is synchronous to the frame head that all slaves carry out all members to utilize main frame to send the logic serial signal; Under the synchronous prerequisite of interrupt signal and frame head, all members just can carry out the synchronous transmitting-receiving of logical signal like this, realize parallel system logical signal synchronously.Because logical signal method for synchronous provided by the invention had not both utilized the CAN bus; Do not utilize the complicated hardware programmable gate array again; But utilized parallel system its other resources and simple line and chip or line or chip to realize logical signal synchronous of whole system, can guarantee that the real-time of system can reduce cost again.
Below in conjunction with Fig. 2 and Fig. 3 logical signal of the present invention is reached synthetic method synchronously and carry out detailed introduction.
Referring to Fig. 2, this figure is the sketch map of parallel system provided by the invention.
To comprise three members in the parallel system, being respectively host A, the first slave B and the second slave C is that example is introduced among Fig. 2.
It is understandable that, can comprise a main frame and at least one slave in the parallel system, specifically do not limit the member's number in the parallel system in the present invention, other a plurality of slaves are identical with the operation principle of a slave with operation principle, do not enumerate one by one at this.
The corresponding controller of each member, be respectively console controller A1, first from machine controller B1 and second from machine controller B2.
Use three IO mouths of each member in the present embodiment, wherein the SYN-M-1 of host A is used to send the logical synchronization signal, and the SYN-S2-1 mouth of the SYN-S1-1 of the first slave B and the second slave C is used to receive the logical synchronization signal that the SYN-M-1 of host A sends.
Wherein, the OUT-S2-1 of the OUT-S1-1 of the OUT-M-1 of host A, the first slave B, the second slave C all is used to send the logic serial signal.
In the present embodiment, said main frame all sends the logic serial signal with all slaves and carries out logical AND, is specially:
Said main frame and all slaves all send logic serial signal to self corresponding line and chip perhaps to self corresponding line or chip;
Said line and chip or line or chip to said logic serial signal carry out output logic behind the logical AND and the result.
As shown in Figure 2, corresponding line of each member and chip.Wired and S_H chip link together, wired and S_L chip of institute links together.
Wired and the chip signal that can the TX of each line and chip be received carry out logical AND, then the result of the logical AND RX through is separately exported.
Main frame line and the TX of chip A2, OUT-M-1, the IN-M-1 that RX is connected host A respectively;
The first slave line and the TX of chip B2, OUT-S1-1, the IN-S1-1 that RX is connected the first slave B respectively;
The second slave line and the TX of chip C2, OUT-S2-1, the IN-S2-1 that RX is connected the second slave C respectively;
The SYN-S1-1 of the first slave B and the SYN-S2-1 of the second slave C all are connected the SYN-M-1 of host A.
It is understandable that the result of logical AND also can realize through line or chip.
Analyzing the present invention below in conjunction with the oscillogram of main signal is how to realize logical signal synchronous.
Referring to Fig. 3, this figure is the oscillogram of the main signal that provides of the embodiment of the invention one.
Main frame sends the logical synchronization signal to all slaves in the present embodiment, so that the frame head of main frame and slave is synchronous, is specially:
Main frame sends the logical synchronization signal of predetermined interrupt cycle to all slaves; Can set as required wherein predetermined interrupt cycle, is four or five and all can for example predetermined interrupt cycle.
In the next interrupt cycle that the transmission of logical synchronization signal finishes, main frame detects the logical synchronization signal with all slaves and sends the sign that finishes; Detect in the next interrupt cycle of sending the sign that finishes, the frame head of main frame and slave is synchronous.
Wherein, main frame and all slaves detect the logical synchronization signal and send the sign that finishes and realize through software program.
Come specifically to introduce the synchronous of logical signal below in conjunction with Fig. 3.
Only introduce among Fig. 3 with the main frame and first slave.
Wherein EPWM is the high frequency synchronization signal that main frame sends, and EPWM gives all slaves as the cycle interruption signal, so that the cycle interruption signal Synchronization of the cycle interruption signal of main frame and all slaves.
EPWM is the triangular pulse signal in the present embodiment, also can be other pulse signals, and for example square-wave signal is used for producing regularly and interrupts.
At first, logical synchronization signal SYN-M that main frame sends to slave is the high level of two interrupt cycles (t1 and t2), is the low level of two interrupt cycles (t3 and t4) then.
The SYN-M that it is understandable that main frame specifically sends high level or low level, and high level and low level interrupt cycle number can set as required, only illustrate at this, do not do concrete qualification.
Then, the SYN-M of main frame keeps the low level of an interrupt cycle (t5) constant, and this low level presentation logic synchronizing signal is sent the sign that finishes.At this moment, it is synchronous that main frame and slave keep frame head.
From confirm frame head synchronous next interrupt cycle (t6) the beginning main frame and slave begin to send the logic serial signal.
As shown in Figure 3, in the t6, OUT-S1-1 and OUT-M-1 all are low levels, and therefore, IN-M-1 and IN-S1-1 also are low levels.In the t7, OUT-S1-1 and OUT-M-1 all are high level, and therefore, IN-M-1 and IN-S1-1 all are high level.In the t8, OUT-S1-1 and OUT-M-1 all are low levels, and therefore, IN-M-1 and IN-S1-1 all are low levels.
Need to prove that above embodiment provides in parallel system main frame and slave and carries out logical signal synchronously and synthetic method, in addition, this method can also be carried out the synchronous redundancy of logical signal.Promptly on the basis of Fig. 2, have a cover to get final product with the identical structure of Fig. 2 in addition again, utilized three IO mouths of main frame, three IO mouths of slave among Fig. 2 at present, the IO mouth that in like manner can double is realized redundant.When this synchronous cover system of logical signal breaks down, can utilize the redundant another set of logical signal that carries out synchronous, identical among its operation principle and Fig. 3 repeated no more at this.
Introduce below when main frame in the parallel system and slave all have coprocessor, utilize primary processor and coprocessor to realize that respectively two of redundancy overlaps the method for controlling.When the main frame in the parallel system and slave include primary processor and coprocessor; The transmission of main frame primary processor is given main frame coprocessor and all slave coprocessors with the square-wave signal of the cycle interruption signal Synchronization of said main frame primary processor, so that the cycle interruption signal of all slave coprocessors is consistent with the cycle interruption signal of main frame primary processor;
When the main frame primary processor sends square-wave signal to all slave coprocessors; Send to the main frame coprocessor, can guarantee that so just the cycle interruption signal of all coprocessors (comprising main frame coprocessor and slave coprocessor) and the cycle interruption signal of main frame primary processor all keep synchronous.
When the cycle interruption signal of all coprocessors was consistent with the cycle interruption signal of main frame primary processor, the main frame coprocessor sent the logical synchronization signal to all slave coprocessors, so that the frame head of main frame coprocessor and slave coprocessor is synchronous;
When main frame coprocessor and slave coprocessor frame head synchronously after, the main frame coprocessor all sends the logic serial signal with all slave coprocessors and carries out logical AND;
Said main frame coprocessor and slave coprocessor are accepted the result of the logical AND of said logic serial signal, and said result is carried out logic analysis, obtain the integrated logic signal of parallel system.
Need to prove that it is to carry out work in order to start coprocessor that the square-wave signal that the main frame primary processor sends to all coprocessors also has an effect, for example the frame head of coprocessor synchronously, send the logical synchronization signal, send logic serial signal etc.The cycle interruption signal of all coprocessors is presented as that all coprocessors carry out the sequential of these concrete work, is the virtual for convenience clock signal that comes out.
Specifically can be referring to Fig. 4, this figure is the sketch map of the synchronous parallel system of the logical signal that has a redundancy feature provided by the invention.
Because Fig. 3 has introduced the synchronous operation principle of a cover logical signal in detail, only introduce the synchronous part of logical signal of the coprocessor completion that utilizes each member in the parallel system below.
Continuing with a main frame and two slaves below is that example is introduced.
Because this redundancy approach requires main frame and slave all to have primary processor and coprocessor, therefore, in order to distinguish, is called main frame primary processor and main frame coprocessor, slave primary processor and slave coprocessor respectively.Because main frame primary processor and slave primary processor are realized the synchronous process of logical signal and are combined Fig. 3 to carry out detailed introduction, repeat no more at this, only introduce coprocessor and carry out the redundant part of logical signal.
The primary processor of host A sends coprocessor and the coprocessor of the first slave B and the coprocessor of the second slave C of giving host A with the square-wave signal CLA-SYN-M of the cycle interruption signal Synchronization of the primary processor of said host A, so that the cycle interruption signal of the coprocessor of the coprocessor of host A, the first slave B and the coprocessor of the second slave C is all consistent with the cycle interruption signal of the primary processor of host A;
When the cycle interruption signal of cycle interruption signal, the first slave B and the coprocessor of the second slave C of the coprocessor of host A is all consistent with the cycle interruption signal of the primary processor of host A; The coprocessor of host A sends logical synchronization signal SYN-M-2 respectively to the coprocessor of the first slave B and the second slave C, so that the frame head of the coprocessor of the coprocessor of host A and the first slave B and the second slave C is synchronous;
After the coprocessor frame head of the first slave B and the second slave C coprocessor and host A was synchronous, the coprocessor of host A sent logic serial signal OUT-M-2 to main frame first line and chip A3; The coprocessor of the first slave B sends logic serial signal OUT-S1-2 to first slave, first line and chip B3; The coprocessor of the second slave C sends logic serial signal OUT-S2-2 to second slave, first line and chip C3.
A3, B3 and C3 carry out logical AND with OUT-M-2, OUT-S1-2 and OUT-S2-2, and A3 sends to the result of logical AND the IN-M-2 of A; B3 sends to the result of logical AND the IN-S1-2 of B; C3 sends to the result of logical AND the IN-S2-2 of C.
The coprocessor of the coprocessor of A and B, C carries out logic analysis to the result of logical AND, and the integrated logic signal that obtains parallel system carries out synchronously.
In the present embodiment; Logical signal between each member in the parallel system is to carry out a cover synchronously through primary processor synchronously, and coprocessor carries out a cover synchronously simultaneously, and such two covers constitute redundant synchronously; When wherein fault appears in a cover, use another set of realization synchronous.
Referring to Fig. 5, this figure is the oscillogram of each corresponding signal of Fig. 4.
Need to prove that the difference of Fig. 5 and Fig. 3 is to have increased square-wave signal CLA-SYN-M, the effect of the signal among other signals and Fig. 3 is identical, repeats no more at this.
The effect of square-wave signal CLA-SYN-M is to keep synchronously for the cycle interruption signal of the coprocessor of the coprocessor of the primary processor of the coprocessor of realizing A, A, B and C.
The logical signal method for synchronous that the embodiment of the invention provides; Not only to having carried out the synchronous of logical signal between each member in the parallel system; And, also the synchronous process of logical signal is carried out redundancy, can guarantee more effectively that like this logical signal between each member keeps synchronously.
Reach synthetic method synchronously based on above-mentioned logical signal, the present invention also provides logical signal to reach synthetic system synchronously, specifies its part below in conjunction with specific embodiment.
Referring to Fig. 6, this figure is that logical signal provided by the invention reaches synthetic system embodiment one sketch map synchronously.
Logical signal provided by the invention reaches synthetic system synchronously, is applied to comprise the parallel system of host A, the first logical AND device D and at least one slave;
Be that example is introduced with a host A, two slaves (the first slave B and the second slave C) in the present embodiment.
Said host A is used for sending the cycle interruption signal to all slaves (the first slave B and the second slave C); After the cycle interruption signal Synchronization of main frame and slave, also be used for sending the logical synchronization signal to all slaves; After the frame head of main frame and slave was synchronous, said main frame was used to send the logic serial signal to the said first logical AND device D;
Said slave (the first slave B and the second slave C) is used for making according to the cycle interruption signal that said main frame sends the cycle interruption signal Synchronization of self cycle interruption signal and main frame; The logical synchronization signal that sends according to said main frame makes the frame head of frame head and main frame of self synchronous; After the frame head of main frame and slave was synchronous, said slave sent the logic serial signal to the said first logical AND device D;
The said first logical AND device D is used for all logic serial signals that receive are carried out logical AND, and the result of logical AND is sent to said main frame and all slaves;
Need to prove that the said first logical AND device D can be by line and chip, perhaps, line or chip are realized.When the said first logical AND device D is line and chip; Be specially with parallel system in identical line and the chip of member's number; For example in parallel system shown in Figure 6; Comprise a main frame and two slaves (totally three members), the first then corresponding logical AND device is three lines and chip, is used for corresponding with each member respectively.
Said host A and all slaves (the first slave B and the second slave C) all result to said logical AND carry out logic analysis, and the integrated logic signal that obtains parallel system also carries out synchronously.
This parallel system can be the inverter of a plurality of parallel connections in the uninterrupted power supply.
The logical signal that present embodiment provides reaches synthetic system synchronously; At first utilize the cycle interruption signal of host A, all members' in the parallel system interrupt signal is synchronous, in interrupt signal synchronously down; It is synchronous to the frame head that all slaves carry out all members to utilize main frame to send the logic serial signal; Under the synchronous prerequisite of interrupt signal and frame head, all members just can carry out the synchronous transmitting-receiving of logical signal like this, realize parallel system logical signal synchronously.Because logical signal method for synchronous provided by the invention had not both utilized the CAN bus; Do not utilize the complicated hardware programmable gate array again; But utilized parallel system its other resources and simple line and chip or line or chip to realize logical signal synchronous of whole system, can guarantee that the real-time of system can reduce cost again.
Need to prove that the system that present embodiment provides can carry out the synchronous redundancy of logical signal, only need to add corresponding logical AND device again and get final product; Redundant realization can have two kinds, and a kind of is to serve as that the basis is added same signal again and got final product with the structure among Fig. 2, and another kind is when each member in the parallel system has primary processor and coprocessor; Accomplish a cover by primary processor; Accomplish a cover by coprocessor, two covers form redundant, as shown in Figure 4.
Referring to Fig. 7, this figure is the sketch map of main frame provided by the invention.
The main frame that present embodiment provides comprises cycle interruption signal transmitting unit 701, logical synchronization signal transmitting unit 702, logic serial signal transmitting unit 703, logical AND receiving element 704 as a result.
Logical synchronization signal transmitting unit 702 is used for sending the said logical synchronization signal of being scheduled to interrupt cycle to all slaves.
Logic serial signal transmitting unit 703 is used for sending the logic serial signal to the logical AND device.
Logical AND is receiving element 704 as a result, is used for RL and installs the logical AND result who sends.
Referring to Fig. 8, this figure is the sketch map of slave provided by the invention.
Each slave comprises logical synchronization signal receiving unit 801, detecting unit 802 and frame head lock unit 803;
Detecting unit 802 is used for sending the next interrupt cycle that finishes when said logical synchronization signal, is used to detect the logical synchronization signal and sends the sign that finishes;
Frame head lock unit 803 when said detection is sent the sign that finishes to the logical synchronization signal after, is used for the frame head of the frame head of slave and main frame synchronous.
Introduce below in this system and carry out redundant operation principle for the logical synchronization signal.
Need to prove, also can realize the redundancy of logical synchronization signal with system shown in Figure 6, just main frame all sends two covers with the present signal of slave and gets final product, and need increase a logical AND device again.This situation is no longer specifically given unnecessary details, and its operation principle is with shown in Figure 6 identical.Only introducing the primary processor utilize each member in the system and coprocessor below, to accomplish a cover logical signal respectively synchronous, when wherein one overlapping when fault occurring, switches to another set of work.
Referring to Fig. 9, this figure is system embodiment two sketch mapes provided by the invention.
Still be that example is introduced with a main frame and two slaves in the present embodiment.
Said main frame includes primary processor and coprocessor with all slaves;
The primary processor A11 of main frame; Be used for to main frame coprocessor A12 and the square-wave signal of all slave coprocessors (the first slave coprocessor B12 and the second slave coprocessor C12) transmission, so that the cycle interruption signal of all coprocessors is consistent with the cycle interruption signal of main frame primary processor A11 with the cycle interruption signal Synchronization of main frame primary processor A11;
Because when the square-wave signal that main frame primary processor A11 sends sends to all slave coprocessors; Send to the coprocessor of main frame oneself, can guarantee that so just the cycle interruption signal of all coprocessors and the cycle interruption signal of main frame primary processor all keep synchronous.
Therefore, the effect of square-wave signal is all to keep synchronous for the cycle interruption signal of realizing main frame coprocessor A12, main frame primary processor A11 and slave coprocessor.
Main frame coprocessor A12 sends the logical synchronization signal to all slave coprocessors (the first slave coprocessor B12 and the second slave coprocessor C12), so that the frame head of main frame coprocessor A12 and slave coprocessor (the first slave coprocessor B12 and the second slave coprocessor C12) is synchronous;
When main frame coprocessor A12 and slave coprocessor (the first slave coprocessor B12 and the second slave coprocessor C12) frame head synchronously after, main frame coprocessor A12 all sends logic serial signal to the second logical AND device E with all slave coprocessors (the first slave coprocessor B12 and the second slave coprocessor C12);
The said second logical AND device E; Be used for the logic serial signal of main frame coprocessor A12 transmission and the logic serial signal of slave coprocessor (the first slave coprocessor B12 and the second slave coprocessor C12) transmission are carried out logical AND, and the result of logical AND is sent to main frame coprocessor A12 and slave coprocessor (the first slave coprocessor B12 and the second slave coprocessor C12);
Said main frame coprocessor A12 and slave coprocessor (the first slave coprocessor B12 and the second slave coprocessor C12) are accepted the result of the logical AND of said logic serial signal; Said result is carried out logic analysis, obtain the integrated logic signal of parallel system and carry out synchronous.
Need to prove that the cycle interruption signal of said primary processor is PWM interrupt signal or timer interrupt signal.
In the present embodiment, it is synchronous that each coprocessor is accomplished a cover logical signal, and it is synchronous that each primary processor is accomplished a cover logical signal, and two covers constitute the synchronous redundancy of logical signal.Wherein main frame primary processor A11, the first slave primary processor B11 are identical with the operation principle of framework shown in Fig. 6 with the operation principle of the second slave primary processor C11, repeat no more at this.
Need to prove, the second logical AND device E also can for main frame and slave line and chip or line or chip one to one.
The system that present embodiment provides, not only can accomplish main frame and each slave in the parallel system logical signal synchronously, and redundancy that can the completion logic signal Synchronization.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (11)
1. a logical signal reaches synthetic method synchronously, it is characterized in that, may further comprise the steps:
Main frame in the parallel system sends the cycle interruption signal and gives all slaves, so that the cycle interruption signal Synchronization of the cycle interruption signal of main frame and all slaves;
When the cycle interruption signal Synchronization of the cycle interruption signal of main frame in the parallel system and all slaves, main frame sends the logical synchronization signal to all slaves, so that the frame head of main frame and slave is synchronous;
After the frame head of main frame and slave was synchronous, main frame all sent the logic serial signal with all slaves and carries out logical AND;
Said main frame and slave receive the result of the logical AND of said logic serial signal, and said result is carried out logic analysis, obtain the integrated logic signal of parallel system and carry out synchronous.
2. method according to claim 1 is characterized in that, main frame sends the logical synchronization signal to all slaves, so that the frame head of main frame and slave is synchronous, is specially:
Main frame sends the logical synchronization signal of predetermined interrupt cycle to all slaves; In the next interrupt cycle that the transmission of logical synchronization signal finishes, main frame detects the logical synchronization signal with all slaves and sends the sign that finishes; Detect in the next interrupt cycle of sending the sign that finishes, the frame head of main frame and slave is synchronous.
3. method according to claim 1 and 2 is characterized in that, said main frame all sends the logic serial signal with all slaves and carries out logical AND, is specially:
Said main frame and all slaves all send logic serial signal to self corresponding line and chip perhaps to self corresponding line or chip;
Said line and chip or line or chip to all logic serial signals carry out output logic behind the logical AND and the result.
4. method according to claim 1; It is characterized in that; When the main frame in the parallel system and slave include primary processor and coprocessor; The transmission of main frame primary processor is given main frame coprocessor and all slave coprocessors with the square-wave signal of the cycle interruption signal Synchronization of said main frame primary processor, so that the cycle interruption signal of all coprocessors is consistent with the cycle interruption signal of main frame primary processor;
When the cycle interruption signal of all coprocessors was consistent with the cycle interruption signal of main frame primary processor, the main frame coprocessor sent the logical synchronization signal to all slave coprocessors, so that the frame head of main frame coprocessor and slave coprocessor is synchronous;
When main frame coprocessor and slave coprocessor frame head synchronously after, the main frame coprocessor all sends the logic serial signal with all slave coprocessors and carries out logical AND;
Said main frame coprocessor and slave coprocessor are accepted the result of the logical AND of said logic serial signal, and said result is carried out logic analysis, and the integrated logic signal that obtains parallel system carries out synchronously.
5. method according to claim 4 is characterized in that, the cycle interruption signal of said primary processor is PWM interrupt signal or timer interrupt signal.
6. a logical signal reaches synthetic system synchronously, it is characterized in that, is applied to comprise the parallel system of main frame, the first logical AND device and at least one slave;
Said main frame is used for sending the cycle interruption signal to all slaves; After the cycle interruption signal Synchronization of main frame and slave, also be used for sending the logical synchronization signal to all slaves; After the frame head of main frame and slave was synchronous, said main frame was used to send logic serial signal to said logical AND device;
Said slave is used for making according to the cycle interruption signal that said main frame sends the cycle interruption signal Synchronization of self cycle interruption signal and main frame; The logical synchronization signal that sends according to said main frame makes the frame head of frame head and main frame of self synchronous; After the frame head of main frame and slave was synchronous, said slave sent logic serial signal to the said first logical AND device;
The said first logical AND device is used for all logic serial signals that receive are carried out logical AND, and the result of logical AND is sent to said main frame and all slaves;
Said main frame all carries out logic analysis to the result of said logical AND with all slaves, obtains the integrated logic signal of parallel system and carries out synchronous.
7. system according to claim 6 is characterized in that said main frame comprises the logical synchronization signal transmitting unit, is used for sending to all slaves the said logical synchronization signal of predetermined interrupt cycle.
8. system according to claim 7 is characterized in that, each slave comprises logical synchronization signal receiving unit, detecting unit and frame head lock unit;
Said logical synchronization signal receiving unit is used to receive the logical synchronization signal that main frame sends;
Said detecting unit is used for sending the next interrupt cycle that finishes when said logical synchronization signal, is used to detect the logical synchronization signal and sends the sign that finishes;
Said frame head lock unit when said detection is sent the sign that finishes to the logical synchronization signal after, is used for the frame head of the frame head of slave and main frame synchronous.
9. system according to claim 6 is characterized in that, said logical AND device is line and chip, perhaps, and line or chip.
10. system according to claim 6 is characterized in that, also comprises the second logical AND device; Said main frame includes primary processor and coprocessor with all slaves;
Said main frame primary processor; Be used for to main frame coprocessor and the square-wave signal of all slave coprocessors transmissions, so that the cycle interruption signal of all coprocessors is consistent with the cycle interruption signal of main frame primary processor with the cycle interruption signal Synchronization of main frame primary processor;
Said main frame coprocessor, when all coprocessor cycle interruption signals with after the cycle interruption signal of main frame primary processor is consistent, be used for sending the logical synchronization signal to all slave coprocessors; After frame head is synchronous, be used for sending the logic serial signal to the second logical AND device;
Said slave coprocessor after frame head is synchronous, is used for sending the logic serial signal to the second logical AND device;
The said second logical AND device is used for the logic serial signal of main frame coprocessor transmission and the logic serial signal of slave coprocessor transmission are carried out logical AND, and the result of logical AND is sent to main frame coprocessor and slave coprocessor;
Said main frame coprocessor and slave coprocessor carry out logic analysis to the result of said logical AND, obtain the integrated logic signal of parallel system and carry out synchronous.
11. system according to claim 10 is characterized in that, the cycle interruption signal of said primary processor is PWM interrupt signal or timer interrupt signal.
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| CN1423389A (en) * | 2001-12-07 | 2003-06-11 | 广东志成冠军电子实业有限公司 | Bus-controlled parallel uninterrupted power source (UPS) system |
| US20050041445A1 (en) * | 2001-12-31 | 2005-02-24 | Dangsheng Zhou | Method of establishing a master & minus; host in modules connecting in parallel |
| CN1592031A (en) * | 2003-09-05 | 2005-03-09 | 飞瑞股份有限公司 | Uninterruption power source module parallel system and by-pass switching method thereof |
| CN1713480A (en) * | 2004-06-22 | 2005-12-28 | 中兴通讯股份有限公司 | Synchronized switching controller and its control for parallel uninterrupted power supply |
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