CN102736863A - 支持失序主机命令组块介质访问的非易失性半导体存储器模块 - Google Patents

支持失序主机命令组块介质访问的非易失性半导体存储器模块 Download PDF

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CN102736863A
CN102736863A CN2012100998748A CN201210099874A CN102736863A CN 102736863 A CN102736863 A CN 102736863A CN 2012100998748 A CN2012100998748 A CN 2012100998748A CN 201210099874 A CN201210099874 A CN 201210099874A CN 102736863 A CN102736863 A CN 102736863A
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D·S·苏里亚布迪
M-M·L·苏
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Western Digital Technologies Inc
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Abstract

本发明涉及支持失序主机命令组块介质访问的非易失性半导体存储器模块。本发明公开一种非易失性半导体存储器模块，其包括存储器件和可操作耦合到存储器件的存储器控制器，其中存储器控制器可操作用于接收主机命令，将主机命令分离为包括含有至少一个逻辑块地址(LBA)的第一组块的一个或更多个组块，以及对照包括一个或更多个活动组块的活动组块一致性列表检查第一组块以确定第一组块是否是独立组块并准备被提交以访问存储器件，或者是否是依赖组块并且延迟访问存储器件直至相关联的依赖性被清除为止。

Description

支持失序主机命令组块介质访问的非易失性半导体存储器模块
技术领域
背景技术
可以采用非易失性半导体存储器(NVSM)模块作为计算机系统(例如，桌上型计算机、膝上型计算机、便携式计算机等)或者消费类装置(例如，音乐播放器、蜂窝电话、相机等)或者其它合适应用的大容量存储器。NVSM模块可以包括一个或更多个存储器件(诸如闪存存储器)和用于经包括I/O总线的通道访问每个存储器件的存储器控制器。存储器控制器可以接收命令，诸如来自主机的写命令或者读命令，并且向存储器件提交每个命令。当向存储器件提交写命令时，存储器控制器通过I/O总线传递地址和写数据。当提交读命令时，存储器控制器通过I/O总线传递地址，接着通过I/O总线接收读取的数据。
然而，主机可以通过相应的读命令和写命令对一个或更多个存储器件中的任意物理位置进行读取和写入。因此，存储器控制器负责确保全部命令按照主机指定的顺序在一个或更多个存储器件上执行。这通常通过使用基于命令的一致性方案来实现。然而，如果多个主机命令正在访问存储器件的公共物理区域，则基于命令的一致性方案要求按照命令被接收到的相同顺序逐个执行命令。
发明内容
附图说明
图1示出根据本发明实施例的非易失性半导体存储器模块，其包括可操作地耦合到多个存储器件的存储器控制器，其中所述存储器控制器包括一致性检查模块和缓冲器，该缓冲器包括活动组块一致性列表。
图2图解说明根据本发明实施例的活动组块一致性列表，其包括已经从先前接收的主机命令分离的活动组块。
图3是根据本发明实施例的流程图，其中主机命令被分离为一个或更多个组块，并且针对活动组块一致性列表中的先前接收的活动组块评估每个组块的依赖性。
图4是根据本发明实施例的流程图，其中检查存储器件中已经完成执行的每个活动组块的前向依赖性，并且如果检测到前向依赖性，则相关联的依赖活动组块被清除以提交用于存储器件访问。
具体实施方式
图1示出根据本发明实施例的非易失性存储器模块102，其包括N个存储器件1041-104N，每个存储器件包括存储器阵列106。在一个实施例中，每个存储器阵列106包括多个块，其中每个块包括被称为页的多个存储段。在读/写命令期间被访问的存储段可以包括任意适当大小，诸如一组页中的完整页或者部分页。
非易失性半导体存储器模块102还包括经相应通道1101-110N可操作地耦合到存储器件1041-104N中每个的存储器控制器108，其中每个通道包括用于在相关联的存储器件和存储器控制器108之间传递读/写数据的I/O总线。非易失性半导体存储器模块102可以包括存储器控制器108和存储器件1041-1041N的任意适当配置。在图1的实施例中，存储器件1041-104N中的每个包括适当的闪存(例如，NAND或者NOR闪存)，并且存储器控制器包括闪存控制器。在一个实施例中，每个存储器件1041-104N可以包括例如相位变化随机存取存储器(PRAM)、电阻变化RAM(ReRAM)、磁阻RAM(MRAM)或者其它适当类型的非易失性半导体存储器。
在一个实施例中，存储器控制器108通过仿真可被主机系统使用标准磁盘驱动通信协议(例如，ATA协议)访问的磁盘驱动器来实现固态驱动器(SSD)。该实施例中的主机112可以包括单独的微处理器(例如，在桌上型或者膝上型计算机中)，其通过适当接口(例如串行或者并行ATA)与SSD通信。在替代实施例中，非易失性半导体存储器模块2可以在消费类装置(例如相机或者蜂窝电话)中实现。
在一个实施例中，非易失性半导体存储器模块102是用混合驱动器中的硬盘驱动器(HDD)实现的，其中存储器控制器108使用一个接口(例如，嵌入式多媒体卡(eMMC)、通用闪存存储器(UFS)或者开放NAND闪存接口(ONFI)接口)经由桥与HDD通信。该实施例中的主机112可以使用另一个接口(例如串行ATA(SATA)或者串行附接SCSI(SAS)接口)与HDD通信。在一个实施例中，一个或更多个非易失性半导体存储器模块102被实现为具有存储装置中的桥，其中主机112经一个接口(例如SAS接口)与该桥通信，并且一个或更多个非易失性半导体存储器模块102中的每个经另一个接口(例如SATA接口)与该桥通信。
在图1的实施例中，存储器控制器108包括一致性检查模块114，该一致性检查模块可操作以将从主机112接收的每个命令分离为一个或更多个组块，其中每个组块具有与闪存的至少一个编程单元相对应的大小。在一个实施例中，该至少一个编程单元对应于闪存的页。在图1的实施例中，一致性检查模块114还可操作用于通过对照包括一个或更多个活动组块(即，已经从先前接收的主机命令分离但是未在存储器件1041-104N之一中完成执行的组块)的活动组块一致性表116检查每个块来确定当前主机命令中的每个组块是独立组块还是依赖组块。在图1的实施例中，活动组块一致性列表116被存储在缓冲器118中。在一个实施例中，活动组块一致性列表116被存储在一致性检查模块114中。在本发明的实施例中，一致性检查模块114还可操作用于从主机112接收命令(例如，读命令和写命令)。下面将结合图2的描述提供关于活动组块一致性列表的额外细节。
在本发明的实施例中，独立组块准备好被提交用于访问存储器件，而依赖组块被延迟访问存储器件直至相关联的依赖性被清除为止。在一个实施例中，当依赖组块所依赖的活动组块在存储器件中完成执行时，依赖组块的相关联的依赖性被清除。在一个实施例中，活动组块包括至少一个逻辑块地址(LBA)。在一个实施例中，活动组块包括八个LBA。
在图1的实施例中，存储器控制器108还包括可通信地耦合到一致性检查模块110的缓冲器118，其中缓冲器118存储已经在一致性检查模块110中从主机命令分离的组块。缓冲器118包括易失性存储器，诸如动态随机存取存储器(DRAM)或者静态随机存取存储器(SRAM)。在本发明的一个实施例中，缓冲器118从主机112接收命令(例如，读命令和写命令)。
在图1的实施例中，存储器控制器108还包括执行模块120，该执行模块可通信地耦合到缓冲器118并且可操作用于从缓冲器118接收组块并提交组块以访问适当的存储器件。在图1的实施例中，执行模块120包括执行队列122，该执行队列用于临时存储主机命令的组块，这些组块已经被清除以提交用于存储器件访问直至适当的存储器件变得可用为止。在图1的实施例中，执行模块120还包括状态块124，该状态块用于从存储器件1041-104N中的每个接收已经被提交用于存储器件访问的组块的状态(例如，组块完成指示)。在一个实施例中，执行队列122包括多个单独的执行队列，每个单独的执行队列经通道1101-110N之一可操作地耦合到存储器件1041-104N之一，其中每个单独的执行队列提供对仅仅一个存储器件的访问。在替代实施例中，执行队列122包括全局执行队列，用于为被清除以提交到存储器件1041-104N中任意一个的组块提供临时存储。
图2图解说明根据本发明实施例的活动组块一致性列表。在图2的活动组块一致性列表216中，活动组块0_0-0_5与命令A相关联，活动组块1_0-1_5与命令B相关联，活动组块2_0-2_2与命令C相关联，以及活动组块3_0-3_5与命令D相关联。在图2所示的示例中，用黑影标记独立组块，并且用缺少阴影标记依赖组块。在一个实施例中，当活动组块中的一个与另一个活动组块交叠时，在两个活动组块之间形成依赖性链路，其中当活动组块中一个的至少一个LBA与另一个活动组块中的至少一个LBA相同时两个活动组块之间发生交叠。在一个实施例中，活动组块是依赖的，因为它们与一个或更多个其它活动组块正在访问相同的逻辑组块号(LCN)。
在一个实施例中，用依赖性指针指示两个活动组块之间的依赖性，其中依赖性指针从交叠组块指到被交叠组块(即，依赖组块)。在一个实施例中，独立组块被清除以提交到存储器件之一，因为它(即独立组块)不具有与另一个活动组块的依赖性。相反地，依赖组块必须等待被提交以对存储器件访问直至其依赖的活动组块在存储器件中完成执行并且与完成的活动组块的依赖性链路被清除。
在图2的实施例中，依赖性指针218指示活动组块3_1依赖于活动组块0_0，依赖性指针220指示活动组块1_0依赖于活动组块0_3，并且依赖性指针222指示活动组块3_4依赖于活动组块1_0。在图2的活动组块一致性列表216中，形成例如在活动组块0_0和3_1之间，活动组块0_3和1_0之间，以及活动组块1_0和3_4之间的依赖性链路。在图2的实施例中，独立组块3_0、0_0-0_5、1_3-1_5和2_0-2_2被清除以提交用于访问存储器件，而依赖组块3_1-3_5和1_0-1_2必须各自等待提交用于存储器件访问直至与另一个活动组块的相关联的依赖性链路被清除为止。在图2的实施例中，在命令C之前从主机接收命令B。然而，来自命令C的独立组块2_0-2_2被清除用于存储器件访问，而来自命令B的依赖组块1_0-1_2必须等待被提交用于存储器件访问直至来自命令A的相应独立组块0_3-0_5在存储器件中完成执行为止。因而，本发明的实施方式使得独立组块能够被失序地提交用于存储器件访问。
在一个实施例中，每个活动组块具有包括依赖性指针条目和状态指示的结构。在一个实施例中，组块状态指示可以是例如活动的、不活动、等待、读取或者写入。在一个实施例中，当两个活动组块交叠时，在这些活动组块之间形成依赖性链路，并且在相对于另一个活动组块独立的活动组块中的依赖性指针条目中标记依赖性指针。当独立组块在存储器件中完成执行时，依赖性链路被清除，因而触发依赖组块被提交用于存储器件访问。例如，在图2的活动组块列表216中，由于活动组块0_0交叠活动组块3_1，所以在活动组块0_0和活动组块3_1之间形成依赖性链路，并且在活动组块0_0的结构中的依赖性指针条目中标记依赖性指针218。当活动组块0_0在存储器件中完成执行时，依赖性链路被清除，因而触发活动组块3_1被提交用于存储器件访问。
在一个实施例中，在与主机命令相关联的每个活动组块在存储器件中完成执行之后，与该主机命令相关联的全部活动组块被从活动组块列表中去除。例如，在图2中的活动组块列表216中，当与主机命令A相关联的活动组块0_0-0_5已经在存储器件中各自完成执行时，活动组块0_0-0_5全部被从活动组块列表216中去除。
在图2的活动组块一致性列表216中，活动组块根据增加的LCN被水平地排序，并且根据进入活动组块列表216的时间被竖直地排序。因而，与命令D相关联的活动组块3_0-3_5是活动组块一致性列表216中的最新活动组块，而与命令A相关联的活动组块0_0-0_5是活动组块列表216中的最老活动组块。在一个实施例中，当在一致性检查模块114(图1)中将新主机命令分离为一个或更多个组块时，对照活动组块列表中的每个活动组块从最近的到最老的活动组块检查每个组块的依赖性。当被交叠的活动组块被标识时或者当全部活动组块已经被检查而没有标识被交叠的组块时，针对新主机命令中每个组块的依赖性检查结束。例如，在图2的活动组块一致性列表216中，首先对照活动组块3_0-3_5检查来自新主机命令的组块的依赖性，接着对照活动组块2_0-2_2检查，依次类推，直至标识了交叠组块或者到达活动组块列表216的末端为止。
图3是根据本发明的实施例由图1中的存储器控制器108执行的流程图，其中存储器控制器108从主机接收命令(步骤302)，并且将主机命令(例如读命令或者写命令)分离为一个或更多个组块(步骤304)。在一个实施例中，每个组块具有与闪存的至少一个编程单元相对应的大小。在本发明的实施例中，该至少一个编程单元对应于闪存的页。对于每个组块，存储器控制器108对照活动组块一致性列表检查组块(步骤306)，并且确定该组块是否是依赖组块(步骤308)。在一个实施例中，活动组块一致性列表包括一个或更多个活动组块，其中每个活动组块与先前接收的主机命令(例如读命令或者写命令)相关联，并且其中“活动”组块是指在存储器件中未完成执行的组块。在一个实施例中，按照从最新到最老活动组块的顺序对照活动组块一致性列表中的每个活动组块检查当前主机命令的每个组块，直至被交叠的活动组块被标识或者已经检查了列表中的全部活动组块，其中当每个组块中至少一个LBA相同时两个组块交叠。如果在活动组块一致性列表中找到被交叠的活动组块，则正被检查的当前组块被标识为依赖组块。在一个实施例中，在交叠的活动组块和当前组块之间建立依赖性链路，并且在交叠的活动组块的结构中的条目中标记依赖性指针。
在图3所示的本发明的实施例中，如果正被检查依赖性的当前组块被确定为是依赖组块，则存储器控制器108存储该依赖组块并且延迟提交用于访问存储器件直至依赖性被清除为止(步骤310)。在一个实施例中，依赖组块被存储在缓冲器118中(图1)。在一个实施例中，在链接到依赖组块的活动组块已经在存储器件中完成执行并且先前在这两个组块之间形成的依赖性链路被清除之后，清除依赖性。如果正被检查依赖性的当前组块被确定为是独立组块，则存储器控制器108将该独立组块发送到执行队列120(图1)以提交到存储器件1041-104N之一(图1)(步骤312)。在图3的实施例中，当存储器件可用时，存储器控制器108将独立组块提交到存储器件(步骤314)。在图3的本发明的实施例中，步骤306、308、310、312和314被存储器控制器108针对当前主机命令中的每个组块适当地重复。
图4是根据本发明的实施例由图1中的存储器控制器108执行的流程图，其中当活动组块在图1的存储器件104中完成执行时(步骤402)，存储器控制器108在活动组块一致性列表中将该活动组块标记为已完成(步骤404)，并且检查已完成的活动组块的前向依赖性(步骤406)。在一个实施例中，前向依赖性由在完成的活动组块中的依赖性指针条目中标记的依赖性指针指示，其中依赖性指针指示依赖于完成的活动组块的活动组块。
在图4的实施例中，如果前向依赖性检查指示前向依赖性，则存储器控制器108清除相关联的依赖组块以提交到存储器件(步骤408)，将清除了依赖性的活动组块发送到执行队列(步骤410)，并且当存储器件可用时将清除了依赖性的活动组块提交到存储器件(步骤412)。在一个实施例中，通过清除先前在相关联的依赖活动组块和完成的活动组块之间形成的依赖性链路，相关联的依赖组块被清除以提交到存储器件。在一个实施例中，完成的活动组块中的依赖性指针指示相关联的依赖组块将被清除用于存储器件提交。
在图4的实施例中，如果在完成的活动组块中不指示前向依赖性(步骤406)，或者指示前向依赖性并且相关联的依赖组块被提交到存储器件用于执行(步骤412)，则存储器控制器108确定完成的活动组块是否是相关联的主机命令中要完成的最后活动组块(步骤414)。如果完成的活动组块被确定为相关联的主机命令中要完成的最后活动组块，则存储器控制器108从活动组块一致性列表中去除相关联的主机命令中的全部活动组块(步骤416)。然而，如果完成的活动组块不是相关联的主机命令中要完成的最后活动组块，则存储器控制器108在活动组块一致性列表中保留完成的活动组块直至相关联的主机命令中的全部剩余的(若干)活动组块在存储器件中完成执行为止。
应注意的是在图3和图4的流程图中示出步骤的具体顺序以图解说明本发明的各个方面。在其它实施例中，可以按照不同顺序执行图3和图4中的流程图中的步骤。
非易失性半导体存储器模块102(图1)中的存储器控制器108可以包括任意适当电路，诸如一个或更多个集成电路。在一个实施例中，存储器控制器108包括微处理器，该微处理器执行控制程序的代码片段以便实现上述流程图。替代地，或者除了微处理器之外，存储器控制器108可以包括用专用集成电路实现的状态机电路。

Claims (26)

1.一种非易失性半导体存储器模块，其包括：
存储器件；
可操作地耦合到所述存储器件的存储器控制器，所述存储器控制器可操作用于：
从主机接收命令；
将所述命令分离为一个或更多个组块，所述一个或更多个组块包括第一组块，所述第一组块包括至少一个逻辑块地址LBA；以及
对照包括一个或更多个活动组块的活动组块一致性列表检查所述第一组块以确定所述第一组块是否是独立组块并且准备提交用于访问所述存储器件，或者是否是依赖组块并且延迟访问所述存储器件直至相关联的依赖性被清除为止。
2.根据权利要求1所述的非易失性半导体存储器模块，其中，所述存储器控制器还可操作用于：
通过确定所述第一组块交叠所述活动组块一致性列表中的活动组块，确定所述第一组块是依赖组块；
在所述第一组块和被交叠的活动组块之间形成依赖性链路；以及
延迟提交所述第一组块用于访问所述存储器件直至所述依赖性链路被清除为止。
3.根据权利要求2所述的非易失性半导体存储器模块，其中，所述存储器控制器还可操作用于在被交叠的组块已在所述存储器件中完成执行之后清除所述依赖性链路。
4.根据权利要求2所述的非易失性半导体存储器模块，其中，所述存储器控制器还可操作用于在被交叠的活动组块中形成依赖性指针，以及其中在被交叠的活动组块已在所述存储器件中完成执行之后所述依赖性指针触发提交所述第一组块用于访问所述存储器件。
5.根据权利要求2所述的非易失性半导体存储器模块，其中，所述存储器控制器还可操作用于当所述第一组块中的至少一个LBA与所述活动组块中的至少一个LBA相同时确定所述第一组块和所述活动组块交叠。
6.根据权利要求2所述的非易失性半导体存储器模块，其中，所述存储器控制器包括缓冲器，以及其中所述控制器还可操作用于将所述第一组块存储在所述缓冲器中直至所述依赖性链路被清除为止。
7.根据权利要求1所述的非易失性半导体存储器模块，其中，所述活动组块一致性列表中的所述一个或更多个活动组块的每个没有在所述存储器件中完成执行。
8.根据权利要求1所述的非易失性半导体存储器模块，其中，所述一个或更多个组块还包括第二组块，其中所述第二组块包括至少一个LBA以及其中所述存储器控制器可操作用于：
通过确定所述第一组块交叠所述活动组块一致性列表中的活动组块，确定所述第一组块是依赖组块；
在所述第一组块和被交叠的活动组块之间形成依赖性链路；
延迟提交所述第一组块用于访问所述存储器件直至所述依赖性链路被清除为止；
通过确定所述第二组块不交叠所述活动组块一致性列表中的任何活动组块，确定所述第二组块是独立组块；以及
提交所述第二组块用于访问所述存储器件。
9.根据权利要求1所述的非易失性半导体存储器模块，其中，所述存储器控制器还可操作用于按照从最新到最旧活动组块的顺序对照所述活动组块一致性列表中的每个活动组块检查所述第一组块，直至被交叠的活动组块被标识或者全部活动组块已经被检查。
10.根据权利要求1所述的非易失性半导体存储器模块，其中，所述活动组块一致性列表中的所述一个或更多个活动组块的每个与先前接收的主机命令相关联。
11.根据权利要求1所述的非易失性半导体存储器模块，其中，所述第一组块具有与闪存的至少一个编程单元相对应的大小。
12.根据权利要求11所述的非易失性半导体存储器模块，其中，所述至少一个编程单元对应于闪存的页。
13.根据权利要求1所述的非易失性半导体存储器模块，其中，所述存储器件包括闪存存储器件。
14.一种操作包括存储器件的非易失性半导体存储器模块的方法，所述方法包括：
从主机接收命令；
将所述命令分离为一个或更多个组块，所述一个或更多个组块包括第一组块，所述第一组块包括至少一个逻辑块地址；以及
对照包括一个或更多个活动组块的活动组块一致性列表检查所述第一组块以确定所述第一组块是否是独立组块并且准备提交用于访问所述存储器件，或者是否是依赖组块并且延迟访问所述存储器件直至相关联的依赖性被清除为止。
15.根据权利要求14所述的方法，还包括：
通过确定所述第一组块交叠所述活动组块一致性列表中的活动组块，确定所述第一组块是依赖组块；
在所述第一组块和被交叠的活动组块之间形成依赖性链路；以及
延迟提交所述第一组块用于访问所述存储器件直至所述依赖性链路被清除为止。
16.根据权利要求15所述的方法，还包括在被交叠的组块在所述存储器件中已经完成执行之后清除所述依赖性链路。
17.根据权利要求15所述的方法，还包括在被交叠的活动组块中形成依赖性指针，以及其中所述依赖性指针在被交叠的活动组块已在所述存储器件中完成执行之后触发提交所述第一组块用于访问所述存储器件。
18.根据权利要求15所述的方法，还包括当所述第一组块中的至少一个逻辑块地址与所述活动组块中的至少一个逻辑块地址相同时确定所述第一组块和所述活动组块交叠。
19.根据权利要求15所述的方法，还包括将所述第一组块存储在缓冲器中直至所述依赖性链路被清除为止。
20.根据权利要求14所述的方法，其中，所述活动组块一致性列表中的所述一个或更多个活动组块的每个没有在所述存储器件中完成执行。
21.根据权利要求14所述的方法，其中，所述一个或更多个组块还包括第二组块，其中所述第二组块包括至少一个逻辑块地址，所述方法还包括：
通过确定所述第一组块交叠所述活动组块一致性列表中的活动组块，确定所述第一组块是依赖组块；
在所述第一组块和被交叠的活动组块之间形成依赖性链路；
延迟提交所述第一组块用于访问所述存储器件直至所述依赖性链路被清除为止；
通过确定所述第二组块不交叠所述活动组块一致性列表中的任何活动组块，确定所述第二组块是独立组块；以及
提交所述第二组块用于访问所述存储器件。
22.根据权利要求14所述的方法，还包括：按照从最新到最老活动组块的顺序对照所述活动组块一致性列表中的每个活动组块检查所述第一组块，直至被交叠的活动组块被标识或者全部活动组块已经被检查。
23.根据权利要求14所述的方法，其中，所述活动组块一致性列表中的所述一个或更多个活动组块的每个与先前接收的主机命令相关联。
24.根据权利要求14所述的方法，其中，所述第一组块具有与闪存的至少一个编程单元相对应的大小。
25.根据权利要求24所述的方法，其中，所述至少一个编程单元对应于闪存的页。
26.根据权利要求14所述的方法，其中，所述存储器件包括闪存存储器件。
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