CN102710236B - Wavelet transform implement structure based on FPGA - Google Patents
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Abstract
The invention discloses a wavelet transform implement structure based on an FPGA (Field-programmable Gate Array), which comprises an input multiplexer, a lifting filter module, a configuration register, a configurable crossbar switch unit, a feedback delay group, a delay register group and an address generator, wherein the configuration register controls the operation to the lifting filter module; the output end of the input multiplexer is connected with the configurable crossbar unit, the lifting filter module and the delay register group in sequence; and the output end of the address generator is connected with the input multiplexer and the feedback delay group. The invention has the advantage that wavelet conversion algorithm is implemented on the FPGA via a hardware description language (HDL), so as to greatly lower the complexity and further reduce the area and the consumption of a chip; and in addition, the FPGA can achieve high-speed signal processing via parallel and production line design, has reorganizable ability, and meets a demand of digital signal processing on real time.
Description
Technical field
The present invention relates to a kind of wavelet transformation implement device based on FPGA, belong to digital processing field.
Background technology
Traditional signal theory, be based upon on Fourier analysis foundation, and Fourier converts as a kind of variation of overall importance, and it has certain limitation.Wavelet analysis is a kind of emerging branch of mathematics, it is the most perfect crystallization of functional, Fourier analysis, harmonic analysis, numerical analysis, wavelet transformation is compared with Fourier conversion, be a time and frequency domain local conversion thereby can information extraction from signal effectively, by calculation functions such as flexible and translations, function or signal are carried out to multiscale analysis, solved the indeterminable many difficult problems of Fourier conversion.
Wavelet transformation data dependence complexity, operand is large, realizes the requirement that can not reach real-time processing by software.Along with the progress of FPGA technology and the decline of cost, for the realization of Wavelet Transformation Algorithm provides another optional approach.The parallel processing mode of FPGA hardware has ensured the high-speed of signal processing, and has restructural ability.Therefore realize possibility is provided for the hardware of wavelet transformation.
Summary of the invention
The object of this invention is to provide a kind of wavelet transformation implement device based on FPGA, to realize signal processing at a high speed, reach the requirement of real-time processing.
According to technical scheme provided by the invention, the described wavelet transformation implement device based on FPGA comprises:
Input multiplexer: detect that after online data stream, input multiplexer can be carried out two functions: the first, staggered online data and be chosen to be the low-pass data of further decomposition or filtering; The second, the data flow of importing into is divided into the odd even clock cycle required by boostfiltering device, also export and in boostfiltering device module, be used for selecting the address information of the delay register group of decomposition level separately;
Boostfiltering device module: according to boosting algorithm, input data are carried out to low pass or high-pass filter, the operation of boostfiltering device module is controlled by configuration register, described boostfiltering device module comprises: the first input end of boostfiltering device module connects the first input end of adder, the second input of boostfiltering device module connects the first input end of the first alternative selector and the first input end of the second alternative selector, the second input of boostfiltering device module also connects the second input of the first alternative selector and the second input of the second alternative selector by the delay register group as a time delay piece, the output of the first alternative selector connects the second input of adder through multiplier, the output of adder and the second alternative selector is through the output of rescaling device, multiplier, adder, delay register group connects respectively configuration register, boostfiltering device module is independently calculated not different data streams in the same time according to given tables of data, exports the low pass of each decomposition level, the wavelet conversion coefficient of high pass filter finally by rescaling device,
Configurable cross bar switch unit: be the selected cell of one two input two outputs, can be selected according to correspondence output or be intersected output by configuration information, decision is single lifting or two lifting, allows the alternating structure of lifting scheme;
Delay of feedback group: for cushioning the low pass output data of described boostfiltering device module calculating and rearranging low pass output data in predetermined sequential, delay of feedback group is sent to output data the input of input multiplexer, and input multiplexer is sent into described output data the input of next boostfiltering device module again;
Delay register group: walk in the calculating of independent lifting instruction at each, the input of multiplier or be directly, or postpone, the data that are delayed will be stored in register cell, be called delay register group; Delay register group has an address input, and the median of the wavelet decomposition of every layer need to be stored in this address;
Address generator: the delay register group that is used for selecting to require decomposition level;
The output of described input multiplexer connects configurable cross bar switch unit, boostfiltering device module, delay register group successively, and the output of address generator connects input multiplexer and delay of feedback group.
Described input multiplexer is made up of two alternative selectors and two latchs, the first input end of the 3rd alternative selector connects the first input traffic, the second input of the 3rd alternative selector connects the second input of the 4th alternative selector, the 3rd alternative selector output odd sequence data, the first input end of the 4th alternative selector connects the first input end of the 4th alternative selector, the second input of the 4th alternative selector connects the second input traffic through the first latch, the 4th alternative selector is by the second latch output even sequence data.
The first input end of described configurable cross bar switch unit connects the odd sequence data output end of input multiplexer, the second input of configurable cross bar switch unit connects the even sequence data output end of input multiplexer, the first output of configurable cross bar switch unit connects the first input end of boostfiltering device module, and the second output of configurable cross bar switch unit connects the second input of boostfiltering device module; By increasing the quantity of described configurable cross bar switch unit, realize more complicated filter.
Described delay of feedback group comprises two data buffers, 4 triple gates and a latch, described two data buffers are connected respectively configuration register with 4 triple gates, wherein, the input of the input of the first data buffer and the second data buffer is connected to respectively the input of delay of feedback group, delay of feedback group input connects the wavelet conversion coefficient of the low pass filter of boostfiltering device module output, the first triple gate, the second triple gate, the input of the 3rd triple gate connects respectively the output of the first data buffer, the output of the second data buffer, the input of delay of feedback group, the input end grounding of the 4th triple gate, the first triple gate, the second triple gate, the 3rd triple gate, the output of the 4th triple gate connects the input of latch, the output of latch connects the second input traffic of input multiplexer.
Described delay register group, in the data of read-write are cushioned, has feedback data, and information is not lost.
Advantage of the present invention is: hardware description language for Wavelet Transformation Algorithm (HDL) is realized on FPGA, greatly reduced complexity, thereby reduce chip area and power consumption.FPGA can realize signal processing at a high speed by parallel and the pipeline design, and has restructural ability, has met the requirement of real-time of Digital Signal Processing.
Brief description of the drawings
Fig. 1 is that the wavelet transformation based on FPGA is realized architecture block diagram.
Fig. 2 is input multiplexer schematic diagram.
Fig. 3 is delay of feedback group schematic diagram.
Fig. 4 is address bit allocation plan.
Fig. 5 is boostfiltering device module principle figure.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described.A kind of method that realizes wavelet transformation on FPGA that the present invention proposes, the method uses the modular design philosophy of FPGA that Wavelet Transformation Algorithm is divided into as six of Fig. 1 modules, will introduce in detail modules below.
(1) input multiplexer: detect that after online data stream, input multiplexer can be carried out two functions: the first, staggered online data and be chosen to be the low-pass data of further decomposition or filtering; The second, the data flow of importing into is divided into the odd even clock cycle required by boostfiltering device, also export and in boostfiltering device module, be used for selecting the address information of the delay register group of decomposition level separately.
This module is made up of multiple alternative selectors and latch, as Fig. 2, and according to controlling and configuration signal, data and the low pass output that obtains from delay of feedback group on cross hatch; The data flow of importing into is divided into the odd even clock cycle required by boostfiltering device, also exports and in boostfiltering device module, be used for selecting the address information of the delay register group of decomposition level separately.
(2) boostfiltering device module: according to boosting algorithm, input data are carried out to low pass or high-pass filter, the operation of boostfiltering device module is controlled by configuration register.Each promotes instruction need to carry out following function: be multiplied by and input in2 with a coefficient Coef, obtain Coef*in2, this result and another input in1 are added, obtain Coef*in2+in1, this result is delivered to next step again and promotes instruction, in2 is that determine whether need to be through a clock cycle delay according to feedback and configuration information.This unit is made up of several pieces that repeat interconnection, each control and the configuration signal being also connected to separately.This module connects the output of input multiplexer, and signal is connected to a series of repeatable blocks through configurable cross bar switch unit, and the output that final step promotes is connected to rescaling device, carries out convergent-divergent output, obtains high pass, low-pass filtering coefficient.
(3) configurable cross bar switch unit: this unit is in fact the selected cell of one two input two outputs, can select according to correspondence output or intersect output by configuration information, decision is single lifting or two lifting, allows the alternating structure of lifting scheme.Only need, simply by increasing the quantity of cross bar switch unit, just can realize more complicated filter.
(4) delay of feedback group: for cushioning the low pass output data that described boostfiltering device module calculates and rearranging low pass output data in predetermined sequential, then by input multiplexer, they are sent into the input of next boostfiltering device module.This module is used rlevel and wlevel as control inputs signal, determines which decomposition level is the data that are read and are written into belong to.For the input of correct data when the input multiplexer module, delay of feedback group need to transmit the value of two continuous low pass filters of identical level within two continuous clock cycle, and the value of all low pass filters must be sent to piece below before next one value is stored.Therefore, each decomposition level only needs two data buffer zones.The scheduling of this complexity can be divided into three observation situations below: even cycle value is stored before several cycles, and its successor value has been postponed one-period; Second input value can directly be sent to output without time delay; Two values of feedback several all after dates after it is stored are delivered to output.The control logic of this unit will detect this different input/output structure, and this depends on the delay of boostfiltering device and value of feedback separately.First this piece calculates required number of memory cells, then their output port is connected with the output of piece by tristate bus line.Also have two extra registers will be connected to output port.One is the input that is directly connected to data, by three-state driver control.Another one is that the free time section in the time not having valid data to process writes complete zero to bus.
(5) delay register group: walk in the calculating of independent lifting instruction at each, the input of multiplier or be directly, or postpone, the data that are delayed will be stored in register cell, be called delay register group; Delay register group has an address input, and the median of the wavelet decomposition of every layer need to be stored in this address.This element comprises one group of register, and storage promotes the intermediate data calculating.Input control end Control carrys out mask register as address bus according to the decomposition level of actual treatment, and the data of read-write are cushioned.The corresponding register of each decomposition layer and a control signal, each the corresponding one deck in Control.In delay register group, in the data of read-write are cushioned, have feedback data, information can not be lost.
(6) address generator: this piece, as an address generator, selects to require the delay register group of decomposition level.As Fig. 4, whether bit0 bit representation accesses first or second sample, other bit representations internal memory pair to be processed.Calculate the sample size obtaining so far with a counter.In order to calculate i layer, we need to have 2
iindividual sample, so will have 1 to be placed on position i when counter, we can know, we have had 2 at least
iindividual sample, thus we must do be one one ground scan counter, from the 1st (the namely second of word) until we run into first 1, so just can calculate enough samples.
The output of described input multiplexer connects configurable cross bar switch unit, boostfiltering device module, delay register group successively, and the output of address generator connects input multiplexer and delay of feedback group.
As shown in Figure 2, described input multiplexer is made up of two alternative selectors and two latchs, the first input end of the 3rd alternative selector Mux1 connects the first input traffic, the second input of the 3rd alternative selector Mux1 connects the second input of the 4th alternative selector Mux2, the 3rd alternative selector Mux1 output odd sequence data, the first input end of the 3rd alternative selector Mux1 connects the first input end of the 4th alternative selector Mux2, the second input of the 4th alternative selector Mux2 connects the second input traffic through the first latch D1, the 4th alternative selector Mux2 is by the second latch D2 output even sequence data.
Described boostfiltering device module, has been used a method of complementary filter in the lifting scheme of employing.
As shown in Figure 5, described boostfiltering device module comprises: the first input end of boostfiltering device module connects the input of adder, the second input of boostfiltering device module connects the first input end of the first alternative selector and the first input end of the second alternative selector, the second input of boostfiltering device module also connects the second input of the first alternative selector and the second input of the second alternative selector by delay register group as a time delay piece, the output of the first alternative selector connects the input of adder through multiplier, the output of adder and the second alternative selector is through the output of rescaling device, multiplier, adder, delay register group connects respectively configuration register.Boostfiltering device module is independently calculated not different data streams in the same time according to given tables of data, exports the low pass of each decomposition level, the wavelet conversion coefficient of high pass filter finally by rescaling device.
The first input end of described configurable cross bar switch unit connects the odd sequence data output end of input multiplexer, the second input of configurable cross bar switch unit connects the even sequence data output end of input multiplexer, the first output of configurable cross bar switch unit connects the first input end of boostfiltering device module, and the second output of configurable cross bar switch unit connects the second input of boostfiltering device module.By increasing the quantity of described configurable cross bar switch unit, just can realize more complicated filter.
As shown in Figure 3, described delay of feedback group comprises two data buffers, 4 triple gates and a latch D, described two data buffers are connected respectively configuration register with 4 triple gates, wherein, the input of the input of the first data buffer B1 and the second data buffer B2 is connected to respectively the input In of delay of feedback group, delay of feedback group input In connects the wavelet conversion coefficient of the low pass filter of boostfiltering device module output, the first triple gate, the second triple gate, the input of the 3rd triple gate connects respectively the output of the first data buffer B1, the output of the second data buffer B2, the input In of delay of feedback group, the input end grounding of the 4th triple gate, the first triple gate, the second triple gate, the 3rd triple gate, the output of the 4th triple gate connects the input of latch D, the output of latch connects the second input traffic of input multiplexer.In delay of feedback group, each decomposition level only needs two data buffer zones, and the value of all low pass filters is sent to piece below before next one value is stored.
The feature that the present invention proposes a kind of parallel and the pipeline design that can give full play to FPGA, realizes signal processing at a high speed, and has the wavelet algorithm implementation of restructural ability.Inquired into lifting scheme use complementary filter a new method, in scheme, we can find out computing unit quantity.Each step promotes with a multiplier and an adder calculating, then considers two multipliers for regulation output ratio.Be exactly Zong calculate N+2 multiplier of element number and N adder, or computing 2N+2 time altogether of every two samples, 4N-2 time of comparing FIR method representation, by the amount of calculation of minimizing approximately 50%.
A single computing unit is the conversion that is enough to carry out the random layer degree of depth.This framework has two major defects, and first is to calculate the high-level high latency that is, saved but compare greatly, and this is not key, and second is to grow path may limit clock speed.Can solve last problem by pipelining method of operation, this has been significant delay by increase.
Claims (4)
1. the wavelet transformation implement device based on FPGA, is characterized in that comprising:
Input multiplexer: detect that after online data stream, input multiplexer can be carried out two functions: the first, staggered online data and be chosen to be the low-pass data of further decomposition or filtering; The second, the data flow of importing into is divided into the odd even clock cycle required by boostfiltering device, also export and in boostfiltering device module, be used for selecting the address information of the delay register group of decomposition level separately;
Boostfiltering device module: according to boosting algorithm, input data are carried out to low pass or high-pass filter, the operation of boostfiltering device module is controlled by configuration register, described boostfiltering device module comprises: the first input end of boostfiltering device module connects the first input end of adder, the second input of boostfiltering device module connects the first input end of the first alternative selector and the first input end of the second alternative selector, the second input of boostfiltering device module also connects the second input of the first alternative selector and the second input of the second alternative selector by the delay register group as a time delay piece, the output of the first alternative selector connects the second input of adder through multiplier, the output of adder and the second alternative selector is through the output of rescaling device, multiplier, adder, delay register group connects respectively configuration register, boostfiltering device module is independently calculated not different data streams in the same time according to given tables of data, exports the low pass of each decomposition level, the wavelet conversion coefficient of high pass filter finally by rescaling device,
Configurable cross bar switch unit: be the selected cell of one two input two outputs, can be selected according to correspondence output or be intersected output by configuration information, decision is single lifting or two lifting, allows the alternating structure of lifting scheme;
Delay of feedback group: for cushioning the low pass output data of described boostfiltering device module calculating and rearranging low pass output data in predetermined sequential, delay of feedback group is sent to output data the input of input multiplexer, and input multiplexer is sent into described output data the input of next boostfiltering device module again;
Delay register group: walk in the calculating of independent lifting instruction at each, the input of multiplier or be directly, or postpone, the data that are delayed will be stored in register cell, be called delay register group; Delay register group has an address input, and the median of the wavelet decomposition of every layer need to be stored in this address;
Address generator: the delay register group that is used for selecting to require decomposition level; The output of address generator connects input multiplexer and delay of feedback group;
The output of described input multiplexer connects configurable cross bar switch unit, boostfiltering device module successively, the first input end of described configurable cross bar switch unit connects the odd sequence data output end of input multiplexer, the second input of configurable cross bar switch unit connects the even sequence data output end of input multiplexer, the first output of configurable cross bar switch unit connects the first input end of boostfiltering device module, and the second output of configurable cross bar switch unit connects the second input of boostfiltering device module.
2. the wavelet transformation implement device based on FPGA as claimed in claim 1, it is characterized in that, described input multiplexer is made up of two alternative selectors and two latchs, the first input end of the 3rd alternative selector connects the first input traffic, the second input of the 3rd alternative selector connects the second input of the 4th alternative selector, the 3rd alternative selector output odd sequence data, the first input end of the 3rd alternative selector connects the first input end of the 4th alternative selector, the second input of the 4th alternative selector connects the second input traffic through the first latch, the 4th alternative selector is by the second latch output even sequence data.
3. the wavelet transformation implement device based on FPGA as claimed in claim 1, it is characterized in that, described delay of feedback group comprises two data buffers, 4 triple gates and a latch, described two data buffers are connected respectively configuration register with 4 triple gates, wherein, the input of the input of the first data buffer and the second data buffer is connected to respectively the input of delay of feedback group, delay of feedback group input connects the wavelet conversion coefficient of the low pass filter of boostfiltering device module output, the first triple gate, the second triple gate, the input of the 3rd triple gate connects respectively the output of the first data buffer, the output of the second data buffer, the input of delay of feedback group, the input end grounding of the 4th triple gate, the first triple gate, the second triple gate, the 3rd triple gate, the output of the 4th triple gate connects the input of latch, the output of latch connects the second input traffic of input multiplexer.
4. the wavelet transformation implement device based on FPGA as claimed in claim 1, is characterized in that, described delay register group, in the data of read-write are cushioned, has feedback data, and information is not lost.
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| CN102970545A (en) * | 2012-12-11 | 2013-03-13 | 东南大学 | Static image compression method based on two-dimensional discrete wavelet transform algorithm |
| CN107430672B (en) * | 2015-12-31 | 2020-08-04 | 京微雅格（北京）科技有限公司 | Universal interface and chip for programmable logic block array edge |
| CN106712751A (en) * | 2016-11-25 | 2017-05-24 | 深圳市紫光同创电子有限公司 | Interconnection apparatus, field-programmable gate array device and signal transmission control method thereof |
| CN107888164A (en) * | 2017-12-15 | 2018-04-06 | 首都师范大学 | A kind of wavelet decomposition transform system and implementation method based on FPGA |
| CN109635233B (en) * | 2018-12-13 | 2023-06-02 | 上海集成电路研发中心有限公司 | Wavelet decomposition accelerating circuit |
| CN112532207B (en) * | 2020-11-19 | 2024-01-26 | 浙江集速合芯科技有限公司 | Method for fast tuning on-chip variable filter |
| CN112448867B (en) * | 2020-11-26 | 2022-06-21 | 海光信息技术股份有限公司 | Signal delay testing method and device, computer readable storage medium and electronic equipment |
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Effective date of registration: 20191212 Address after: 214122 building 3, K-park business center, 50 xiuxi Road, Binhu District, Wuxi City, Jiangsu Province 4013 Patentee after: Changguangxi intelligent manufacturing (Wuxi) Co., Ltd Address before: 1800 No. 214122 Jiangsu city of Wuxi Province Li Lake Avenue Patentee before: Jiangnan University |