CN102710228A - Method for one-click testing and automatic gain control of loop time constants - Google Patents
Method for one-click testing and automatic gain control of loop time constants Download PDFInfo
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- CN102710228A CN102710228A CN2012100178880A CN201210017888A CN102710228A CN 102710228 A CN102710228 A CN 102710228A CN 2012100178880 A CN2012100178880 A CN 2012100178880A CN 201210017888 A CN201210017888 A CN 201210017888A CN 102710228 A CN102710228 A CN 102710228A
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Abstract
The invention discloses a method for one-click testing and automatic gain control of loop time constants. According to the method, instruments and manual operation are not required, the test can be completed automatically. The technical scheme includes that firstly, a test beginning instruction is fomulated and received according to an automatic gain control (AGC) loop to be detected, which is arranged in a field programmable gate array (FPGA), the gain of the AGC loop to be detected is changed, a testing comparator which determines whether the AGC loop is in a stable state and a counter which counts the AGC loop system to be detected are produced, a testing program for time constants of the AGC loop to be detected is completed, a testing module is constructed on a module of the AGC loop to be detected, then the testing comparator determines whether the peak power Vout output by the AGC loop is less or more than the preset threshold value Vref, and then the result of the output counting value is reported to a computer, the loop stabilization time, and the result is showed. According to the method, a frequency spectrograph can be replaced for testing the signal amplitudes and the time constants of the AGC loop.
Description
Technical field
The present invention relates to a kind of test automatic gain control loop (AGC) time constant, i.e. loop stability time method of being mainly used in.
Background technology
Automatic gain control loop (AGC) time constant (settling time) is meant automatic gain control loop (AGC) the loop stable time of output when the input signal power changes; The setting of time constant (settling time) is all relevant with modulating frequency, the variable power frequency of information; Too weak point can not be oversize, so time constant is one of key index that characterizes the AGC loop.
Usually the method for test AGC time constant be with the AGC loop output convert analog signal into through digital to analog converter D/A, carry out through the mode of manual operation instrument test.It at first is to utilize signal source to produce the variable amplitude-modulated signal of amplitude modulation frequency to be input to the AGC loop, utilizes oscilloscope to test the variation of different amplitude-modulated signal subcarrier amplitudes then.Frequency according to amplitude-modulated signal obtains the AGC time constant, and the problem of this method of measurement is that measuring process is accomplished by manual operation, and measuring speed is slow, complex operation.
Summary of the invention
Slow in order to overcome above-mentioned prior art measuring speed, the problem of complex operation, the present invention proposes the method that a kind of testing efficiency is higher, cost is lower, test key test more accurately automatic gain is controlled (AGC) loop time constant.
The method of a kind of key test automatic gain control loop time constant that the present invention proposes has following technical characterictic:
(1) to the tested AGC loop of design in programmable gate array chip (FPGA); Establishment receives the beginning test command in FPGA; Change tested automatic gain control (AGC) loop gain; Produce one and judge whether the AGC loop is in the test comparator of stable state and the counter that tested AGC cyclic system clock is counted, accomplish test program, on tested AGC loop model, make up test model tested AGC loop time constant;
(2) computer is connected with FPGA through CPCI, PCI, serial ports, network, sends the control command that begins to test to FPGA, is judged the peak power V of tested AGC loop output by above-mentioned test comparator
OutWhether less than or greater than the threshold value V that sets
RefAfter, end of output arteries and veins and count value; Result with count value reports computer then, and computer calculates the loop stability time according to system's clock of reported result and tested AGC loop, and display result.
The present invention has following beneficial effect than prior art:
The present invention's programming in programmable gate array chip (FPGA) lining changes the gain of tested automatic gain control (AGC) loop, changes with the step that realizes input signal; Relatively the method for the reference value of the output of peak value circuit and designer's design judges whether loop is in stable state in the AGC loop; Method with statistics clock number is tested the stabilization time that automatic gain is controlled (AGC), i.e. time constant; Utilize the real working signal to test, substituted in the conventional test methodologies amplitude modulation test signal that produces changeable frequency by signal source.
The present invention utilizes the design of tested AGC loop in programmable gate array chip (FPGA), add or deduct that a constant value increases or the digital gain that reduces loop realizes that the step of tested AGC loop input signal changes in the gain of digital loop in programmable gate array chip (FPGA).Through the step response of test automatic gain control AGC loop, test automatic gain control AGC time constant.
The present invention programmes in programmable gate array chip (FPGA) lining; Produce a test comparator to realize judging whether loop is in stable state; Utilize the peak value detection output of tested AGC loop and the reference value of tested AGC loop design to compare; The stable condition that reaches setting is the end pulse of output counter; Substitute conventional test methodologies and utilized oscilloscope, frequency spectrograph test output signal amplitude, need not increase other program, also need not increase the digital to analog converter (D/A) that digital signal is converted into analog signal.
Programming receives the beginning test command in programmable gate array chip (FPGA) lining in the present invention; Start the test counter in the programmable gate array chip (FPGA); When receiving the end pulse; Counter in the programmable gate array chip (FPGA) finishes counting, and output system clock number utilizes interfaces such as CPCI, PCI, serial ports or network interface to report computer software.
The present invention also shows according to the time constant of system's clock frequency (fs) and counting (N) calculating AGC loop in computer software.
Utilize this method need not use instrument and manual operation, make that testing efficiency is higher, cost is lower, test is more accurate.The operator only needs on the computer software interface, to click " beginning test " key and just can start test and accomplish test automatically.Comprise the computer of control test starting and reception result, the programmable gate array chip (FPGA) of alternative frequency spectrograph test signal amplitude.The present invention reaches the purpose of test automatic gain control AGC time constant through the step response of test automatic gain control AGC loop.
Description of drawings
Fig. 1 is a testing hardware connected mode of the present invention.
Fig. 2 is the present invention's AGC loop model to be tested and test model.
Fig. 3 is a loop stability time statistical method.
Fig. 4 is the control flow chart of computer software programs of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further specified.
The hardware device of embodiment of the present invention method; Comprise control test starting and reception result computer, directly utilize working signal to test; Need not increase signal source and produce test signal, substitute the programmable gate array chip FPGA of frequency spectrograph test amplitude-modulated signal amplitude.The gain of automatic gain control loop (AGC) is determined by analog control voltage, and the digital gain decision that analog control voltage is produced by FPGA.To the tested AGC loop of design in programmable gate array chip FPGA; Establishment changes tested automatic gain control AGC loop gain in FPGA; Produce one and judge whether the AGC loop is in the test comparator of stable state; Completion is to the test program of tested AGC loop time constant and on tested AGC loop model, make up test model, and these programs comprise: receive the beginning test program, realize program that tested AGC input signal step changes, to the program of system's clock counting of tested AGC loop and judge that tested AGC loop is in stable program.Test counter of design in FPGA, the beginning of test counter and end are produced after the beginning pulse is received test command by FPGA by beginning, end pulse decision, and the end pulse is by the output of the test comparator in FPGA generation.When beginning to test; After tested AGC loop stability; Add or deduct a constant value on the loop digital gain in programmable gate array chip FPGA; To reach the purpose that changes input signal amplitude, digital gain value is value arbitrarily, as long as the analog control voltage that guarantees to export is in the control range of automatic gain control loop (AGC) chip.
Computer is through CPCI, PCI, serial ports, network startup test; FPGA receives the beginning test command; Programming produces a starting impulse signal and starts test counter among the FPGA, and test counter is counted system's clock of tested AGC loop, and programmable gate array chip FPGA adds or deduct a constant value C onst on the digital gain value Gain of tested AGC loop simultaneously; This constant value is variable; As long as guarantee variable gain amplifier in controlled range, when digital gain Gain was increase, the test comparator that programming produces in FPGA was judged the peak value V of the peak detection circuit output in the tested AGC loop
Out<reference value value V
Ref, the end of output pulse, this finishes pulse control test counter and finishes counting and output count value; When digital gain Gain when reducing, the test comparator is judged the peak value V of the peak detection circuit output in the tested AGC loop
Out>Reference value V
Ref, the end of output pulse, this finishes pulse control test counter and finishes counting and output count value.FPGA programs and reports the count value of test counter through interfaces such as CPCI, PCI, serial ports, networks, and computer is through system's clock programming calculating loop stabilization time of count value and tested AGC loop.
Among Fig. 1, computer sends the control command that begins to test through CPCI, PCI, serial ports, network to programmable gate array chip FPGA, tests after FPGA receives orders, from beginning to test the system clock frequency f of loop stability to tested AGC loop
sCount, count value is N, according to system's clock frequency f
sObtain loop stability time and time constant with count value N
T in the formula
STBe time constant, f
sBe system's clock frequency of tested AGC loop, N is for finishing the count value of test hour counter.
Result with count value behind the EOT reports computer through interfaces such as CPCI, PCI, serial ports, networks, and computer calculates loop stability time and display result according to reported result and system's clock by above formula.
In Fig. 2; Comprise tested AGC loop model and test model; Input signal is input among the FPGA through modulus converter A/D after controlling through variable gain amplifier; Amplifier's gain is by the tested AGC loop model control among the FPGA, and the digital gain that tested AGC loop produces converts control voltage to through digital to analog converter D/A, realizes the control to variable gain amplifier.Tested AGC loop model among the FPGA is exported peak detection values V with input signal through peak detection circuit
OutWith reference value V
RefCompare, comparator obtains peak detection values V
OutWith reference value V
RefDifference, the difference component produces the digital gain of adjustment gain through loop filter, the adjustment through digital gain makes that the peak detection values of output signal is consistent with reference value.When beginning to test; Add or deduct a constant value that can be provided with arbitrarily on the digital loop yield value of test model in tested AGC loop model; Output to digital to analog converter D/A; D/A converts digital gain the control voltage of variable gain amplifier into, has realized that the step of tested AGC loop input signal changes.Designed in the test comparator and judged that tested AGC loop is in the condition of stable state, when peak value detects output V
OutWith reference value V
RefWhen satisfying the loop stability status condition of test comparator; The end pulse of output counter; Judge in the test comparator that the condition that tested AGC loop is in stable state divides two kinds of situation: a kind of situation be the constant const that adds as digital loop gain G ain when beginning to test on the occasion of the time, test comparator and satisfy peak detection values V
OutLess than threshold value V
RefThe time end of output pulse; Another kind of situation is the constant const that adds as digital loop gain G ain when beginning to test when being negative value, tests comparator and satisfies peak detection values V
OutGreater than threshold value V
RefThe time end of output pulse.
In Fig. 3, test counter is received the beginning pulse, and beginning is with system's clock counting, and test counter finishes counting after receiving and finishing pulse, exports current count value simultaneously.
In the computer software that Fig. 4 describes, computer is connected with programmable gate array chip FPGA through CPCI, PCI, serial ports, network, when tested AGC loop working stability; The tester works out and starts test and acceptance test result and Program for Calculation on computers, and the operator only need click " the beginning test " on the computer software, and computer software sends a test command; FPGA starts test, behind the EOT after receiving this order; Initiatively pass through interfaces such as CPCI, PCI, serial ports, network; Test result is reported computer software, after computer software is received count value N, according to system's clock frequency f
sWith count value N constant computing time T
STAnd be presented on the interface.
Above-described only is the preferred embodiments of the present invention.Should be pointed out that for the person of ordinary skill of the art, under the prerequisite that does not break away from the principle of the invention, can also make some distortion and improvement, these changes and change should be regarded as belonging to protection scope of the present invention.
Claims (7)
1. a key is tested the method for automatic gain control loop time constant, has following technical characterictic:
(1) to the tested AGC loop of design in programmable gate array chip (FPGA); Establishment receives the beginning test command in FPGA; Change tested automatic gain control (AGC) loop gain; Produce one and judge whether the AGC loop is in the test comparator of stable state and the counter that tested AGC cyclic system clock is counted, accomplish test program, on tested AGC loop model, make up test model tested AGC loop time constant;
(2) computer is connected with FPGA through CPCI, PCI, serial ports, network, sends the control command that begins to test to FPGA, is judged the peak power V of tested AGC loop output by above-mentioned test comparator
OutWhether less than or greater than the threshold value V that sets
RefAfter, end of output arteries and veins and count value; Result with count value reports computer then, and computer calculates the loop stability time according to system's clock of reported result and tested AGC loop, and display result.
2. the method for key test automatic gain control loop time constant as claimed in claim 1; It is characterized in that; The beginning of test counter and end are by beginning, end pulse decision; Produce after the beginning pulse is received test command by FPGA, finish pulse and produce by the output of the test comparator in FPGA.
3. the method for key test automatic gain control loop time constant as claimed in claim 1; It is characterized in that; The test comparator compares according to the peak value output of the peak detection circuit of tested AGC loop and the reference value of tested AGC loop, and then end of output pulse satisfies condition.
4. the method for key test automatic gain control loop time constant as claimed in claim 1; It is characterized in that described test program comprises: receive the beginning test program, realize program that tested AGC input signal step changes, to the program of system's clock counting of tested AGC loop and judge that tested AGC loop is in stable program.
5. the method for key test automatic gain control loop time constant as claimed in claim 1 is characterized in that, tests after FPGA receives orders, from beginning to test the system clock frequency f of loop stability to tested AGC loop
sCount, count value is N, according to system's clock frequency f
sObtain loop stability time and time constant with count value N
, T in the formula
STBe time constant, f
sBe system's clock frequency of tested AGC loop, N is for finishing the count value of test hour counter.
6. the method for key test automatic gain control loop time constant as claimed in claim 1; It is characterized in that; Variable gain amplifier gain in the tested AGC loop model of FPGA is realized that the peak value of input signal detects, is compared by programmable gate array chip FPGA control, produces digital loop gain G ain; The digital loop gain generates the required control voltage of variable gain amplifier through digital to analog converter (D/A) conversion.
7. the method for key test automatic gain control loop time constant as claimed in claim 1; It is characterized in that; When beginning to test, test model adds or deducts a constant value that can be provided with arbitrarily on the digital loop yield value of tested AGC loop, output to digital to analog converter D/A; D/A converts digital gain the control voltage of variable gain amplifier into, the step response of test AGC loop input signal.
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| CN2012100178880A CN102710228A (en) | 2012-01-19 | 2012-01-19 | Method for one-click testing and automatic gain control of loop time constants |
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| CN2012100178880A CN102710228A (en) | 2012-01-19 | 2012-01-19 | Method for one-click testing and automatic gain control of loop time constants |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107528590A (en) * | 2016-06-22 | 2017-12-29 | 中芯国际集成电路制造（天津）有限公司 | The settling time method of testing and system of digital analog converter |
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| US20030202495A1 (en) * | 2002-04-30 | 2003-10-30 | Frank Poegel | Power normalization in WLAN receivers |
| US20040247057A1 (en) * | 2003-06-04 | 2004-12-09 | Gil-Yong Park | Automatic gain control apparatus with short settling time |
| CN101158708A (en) * | 2007-10-23 | 2008-04-09 | 无锡汉柏信息技术有限公司 | Multiple chips automatic test method based on programmable logic device |
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2012
- 2012-01-19 CN CN2012100178880A patent/CN102710228A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20030202495A1 (en) * | 2002-04-30 | 2003-10-30 | Frank Poegel | Power normalization in WLAN receivers |
| US20040247057A1 (en) * | 2003-06-04 | 2004-12-09 | Gil-Yong Park | Automatic gain control apparatus with short settling time |
| CN101158708A (en) * | 2007-10-23 | 2008-04-09 | 无锡汉柏信息技术有限公司 | Multiple chips automatic test method based on programmable logic device |
Non-Patent Citations (2)
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| 杨佳等: "数字AGC的设计与实现", 《综合电子信息技术》, 18 February 2007 (2007-02-18), pages 46 - 48 * |
| 王健等: "基于FPGA的快速自动增益控制系统设计", 《自动化技术与应用》, vol. 25, no. 12, 25 December 2006 (2006-12-25), pages 67 - 70 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107528590A (en) * | 2016-06-22 | 2017-12-29 | 中芯国际集成电路制造（天津）有限公司 | The settling time method of testing and system of digital analog converter |
| CN107528590B (en) * | 2016-06-22 | 2020-07-28 | 中芯国际集成电路制造（天津）有限公司 | Method and system for testing establishment time of digital-to-analog converter |
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Application publication date: 20121003 |