CN106053908A - Analog-to-digital signal conversion device of digital oscilloscope - Google Patents
Analog-to-digital signal conversion device of digital oscilloscope Download PDFInfo
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- CN106053908A CN106053908A CN201610529765.3A CN201610529765A CN106053908A CN 106053908 A CN106053908 A CN 106053908A CN 201610529765 A CN201610529765 A CN 201610529765A CN 106053908 A CN106053908 A CN 106053908A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R13/02—Arrangements for displaying electric variables or waveforms for displaying measured electric variables in digital form
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Abstract
The invention discloses an analog-to-digital signal conversion device of a digital oscilloscope. The analog-to-digital signal conversion device comprises a threshold level controller, N sets of ADC modules, speed reduction modules and digital comparison modules, wherein the threshold level controller, the speed reduction modules and the digital comparison modules are realized in FPGA. Each set of ADC module, speed reduction module and digital comparison module corresponds with one input signal channel. The threshold level controller generates a threshold level and a threshold sensitivity voltage which correspond with each channel in each functional module according to a user instruction and transmits the threshold level and the threshold sensitivity voltage to the corresponding digital comparison module. The ADC module performs analog-to-digital conversion on the input signal of the corresponding channel. The converted signal undergoes speed reduction of the speed reduction module, and then the speed-reduced signal is input into the digital comparison module. The digital comparison module performs determination on the speed-reduced digital signal according to the threshold level and the threshold sensitivity for obtaining a level signal, and then the level signal is input into a corresponding functional module for being processed. The analog-to-digital signal conversion device can independently set the threshold level and the threshold sensitivity for each functional module, thereby improving performance of the digital oscilloscope.
Description
Technical field
The invention belongs to digital oscilloscope technical field, more specifically, relate to the modulus letter of a kind of digital oscilloscope
Number conversion equipment.
Background technology
Digital oscilloscope, as universal tester, is widely used in industry-by-industry, it is therefore desirable to oscillography utensil
There is several functions to meet the demand of various test occasion.In digital oscilloscope in the current marketplace, triggering collection, agreement are divided
Analysis, waveform searching, frequency measurement function are the functions that a digital oscilloscope is indispensable, will realize these functions and be required for using ratio
Input signal is made decisions according to the threshold level preset and generates digital signal by relatively device, i.e. completes the modulus letter of input signal
Number conversion.Fig. 1 is digital oscilloscope analog-digital signal conversion device structure chart in prior art.As it is shown in figure 1, current domestic majority
Employing FPGA (Field-Programmable Gate Array, i.e. field programmable gate array) realizes triggering collection, agreement is divided
Analysis, waveform searching, frequency measurement function, it is to process a series of " 0 ", " 1 " digital signal that FPGA realizes essence, and counts
Word signal is produced by comparator, each input signal channel CHiConnect a comparator, i=1,2 ..., N, N represent passage
Number.Each channel C HiThe threshold level of input signal and comparator compare judgement, be 1 higher than threshold level, less than threshold
Value level is 0, thus realizes the conversion of modulus signal.The threshold level of comparator can pass through DAC (Digital to analog
Converter, digital analog converter) regulation.The program is properly termed as " comparator+DAC " technical scheme.
Finding through research, using " comparator+DAC " scheme to produce digital signal mainly has a following defect:
(1) key signal produces mistake.
Triggering equal to 20ns as arranged channel C H1 positive slope, existing scheme uses a railway digital signal by comparator 1
Producing, another railway digital signal is produced by comparator 5 after MUX selects, because of two comparator switching rates differences,
The problems such as circuit transmission delay, add the time delay between 2 railway digital signals, and this delay time and oscillograph device performance
Relevant, ultimately result in and gather the triggering signal needed and produce time of day error, so the waveform that show of screen and actual measured signal
Different.
(2) high speed protocol is parsed into power low.
As 100M Ethernet carries out protocal analysis, 100M ethernet physical layer signal frequency is 125MHz, and in FPGA
Portion's sampling clock is random less than the phase place between 400MHz, and sampling clock and 100M ethernet signal.Therefore right in FPGA
When 100M Ethernet information is sampled, if the sampled point of FPGA is located exactly at the metastable state region of digital signal, then
The data mistake that FPGA extracts, ultimately results in 100M Ethernet protocol and analyzes unsuccessfully；If FPGA sampling location does not exists
Metastable state region, then the data of extraction then meet physical layer specification, but Ethernet one frame data length is relatively big, as long as extracting number
According to mistake, may result in and analyze unsuccessfully, so it is low to be parsed into power.
(3) fixing threshold sensitivity affects oscillograph functional realiey.
In the scheme of " DAC+ comparator ", the sensitivity of threshold level is realized by the hysteresis voltage of regulation comparator,
And the size of hysteresis voltage is determined by comparator feedback resistance size, so threshold value cannot be realized according to input signal noise size
Level flexible, the most just cannot produce correct digital signal, affect functional realiey.As threshold level sensitivity was arranged
Little, can cause triggering signal in edging trigger and produce by mistake；Measurement data mistake can be caused in frequency measurement；Such as threshold level
Arranging excessive, when signal amplitude is less than sensitivity voltage, comparator can not produce digital signal so that frequency measurement can not be real
Now, do not trigger signal to produce.
(4) triggering collection, protocal analysis, 3 functions of waveform searching use same threshold level, affect oscillograph function real
Existing.
When oscillographic passage inputs standard I2During C protocol signal, and CH1 be clock signal, clock frequency 100KHz,
CH2 be data signal, level standard be LVTTL, when order operation in accordance with the following steps:
A () arranges trigger condition is to stop more than 800ns the CH1 rise time, and threshold value H is 2.8V, threshold value L is 1.2V, i.e.
Comparator 1 threshold value is 2.8V, comparator 5 threshold value is 1.2V；
B () arranges flag condition is CH1 rising edge, and threshold value CH2 is 3V, i.e. comparator 2 threshold value is 3V；
C () arranges I2C protocal analysis parameter is clock CH1, data CH2,7 bit address patterns, and threshold value CH1 is 1.5V, CH2
For 1.4V, the i.e. threshold value of comparator 1 be 1.5V, the threshold value of comparator 2 be 1.4V.
Because of each passage only one of which comparator, so threshold level is consistent with nearest operation, the i.e. threshold of comparator 1
Value is 1.5V, the threshold value of comparator 2 is 1.4V, comparator 5 threshold value is 1.2V.The program makes trigger module and waveform searching mould
The threshold value of block there occurs change, and the parameter that oscillograph does not give according to user realizes its function, causes the content that screen shows
It is not inconsistent with user setup parameter.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, it is provided that the modulus signal conversion dress of a kind of digital oscilloscope
Put, use " ADC+FPGA " technical scheme, independently carry out threshold level for each functional module and threshold sensitivity is arranged, thus
Improve the performance of digital oscilloscope.
For achieving the above object, the analog-digital signal conversion device of digital oscilloscope of the present invention, including a threshold value electricity
Flat controller and N group ADC ADCi, reduction of speed module SiWith numeral comparison module Ci, i=1,2 ..., N, wherein threshold level control
Device processed, reduction of speed module Si, numeral comparison module CiAll realize in FPGA, often group ADC ADCi, reduction of speed module SiAnd numeral
Comparison module CiA corresponding input signal channel；
Threshold level controller is for generating, according to user instruction, the threshold value electricity that in each functional module, each passage is corresponding
Gentle threshold sensitivity voltage, wherein threshold level is designated as Vij, threshold sensitivity voltage is designated asWherein 0≤Vij≤2K-1,AndJ=1,2 ..., M, M represent numeral comparison module CiMiddle numeral ratio
The quantity of relatively device, K represents the figure place of ADC；
ADC ADCiReceive corresponding signal condition channel C H respectivelyiInput signal, be converted into digital signal DATAi,
It is sent to corresponding reduction of speed module Si；
Reduction of speed module SiThe digital signal DATA that reception is obtainediCarry out reduction of speed and obtain digital signal S_DATAi, it is sent to
Corresponding numeral compares comparison module Ci；
Numeral comparison module CiIncluding M digital comparator cij, each digital comparator cijReceive digital signal S_
DATAi, according to threshold level VijWith threshold sensitivity voltageTo digital signal S_DATAiCompare judgement and obtain level letter
Number, input is to corresponding functional module.
The analog-digital signal conversion device of digital oscilloscope of the present invention, including a threshold level controller and N group ADC mould
Block, reduction of speed module and numeral comparison module, wherein threshold level controller, reduction of speed module, numeral comparison module are all in FPGA
Realize, often organize ADC, reduction of speed module and the numeral corresponding input signal channel of comparison module；Threshold level controller root
Generate, according to user instruction, threshold level and threshold sensitivity voltage that in each functional module, each passage is corresponding and be sent to correspondence
Digital comparison module, ADC carries out analog digital conversion to the input signal of respective channel, after reduction of speed module reduction of speed input number
Word comparison module, numeral comparison module compares judgement according to threshold level and threshold sensitivity to the digital signal after reduction of speed
Obtaining level signal, input processes to corresponding functional module.
The present invention uses " ADC+FPGA " technical scheme to realize by analog-digital signal conversion device, can improve generated number
The accuracy of word signal, improves the performance of digital oscilloscope；Achieve each functional module threshold level and threshold sensitivity
Be independently arranged, substantially increase digital oscilloscope and use the accuracy of two or more functional module simultaneously.
Accompanying drawing explanation
Fig. 1 is digital oscilloscope analog-digital signal conversion device structure chart in prior art；
Fig. 2 is the detailed description of the invention structure chart of the analog-digital signal conversion device of digital oscilloscope of the present invention；
Fig. 3 is the structure chart of numeral comparison module in the present embodiment；
Fig. 4 is the threshold level schematic diagram of various functions module in the present embodiment.
Detailed description of the invention
Below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is described, in order to those skilled in the art is preferably
Understand the present invention.Requiring particular attention is that, in the following description, when known function and design detailed description perhaps
When can desalinate the main contents of the present invention, these are described in and will be left in the basket here.
Embodiment
Fig. 2 is the detailed description of the invention structure chart of the analog-digital signal conversion device of digital oscilloscope of the present invention.Such as Fig. 2 institute
Showing, the analog-digital signal conversion device of digital oscilloscope of the present invention includes a threshold level controller and N group ADC ADCi、
Reduction of speed module SiWith numeral comparison module Ci, i=1,2 ..., N, wherein threshold level controller, reduction of speed module Si, numeral compares
Module CiAll realize in FPGA.Often group ADC ADCi, reduction of speed module SiWith numeral comparison module CiA corresponding input letter
Number passage.
Threshold level controller is for generating, according to user instruction, the threshold value electricity that in each functional module, each passage is corresponding
Gentle threshold sensitivity voltage, wherein threshold level is designated as Vij, threshold sensitivity voltage is designated asWherein j=1,2 ..., M, M
Represent numeral comparison module CiThe quantity of middle digital comparator.Threshold level VijSpan meet 0≤Vij≤2K-1, threshold value
Sensitivity voltageSpan also meetAndK represents ADC mould
The figure place of block.Threshold level controller is by threshold level VijIt is designated as with threshold sensitivity voltageIt is sent to the numeral ratio of correspondence
Relatively module Ci。
ADC ADCiReceive corresponding signal condition channel C H respectivelyiInput signal, be converted into digital signal DATAi,
It is sent to corresponding reduction of speed module Si。
Reduction of speed module SiThe digital signal DATA that reception is obtainediCarry out reduction of speed and obtain digital signal S_DATAi, it is sent to
Corresponding numeral compares comparison module Ci.Reduction of speed module S is setiIt is because current digital oscilloscope and typically uses high-speed sampling, number
Word signal DATAiSpeed the highest, can beyond FPGA process data rate the upper limit, it is therefore desirable to reduction of speed module SiCarry out going here and there also
Conversion, thus reduces the speed of digital signal so that it is being positioned at FPGA can be within the data rate ranges of normal process.Go here and there and turn
The parameter changed is that the design parameter according to digital oscilloscope high-speed sampling is arranged.
Numeral comparison module CiIncluding M digital comparator cij, each digital comparator cijReceive digital signal S_
DATAi, according to corresponding threshold level VijWith threshold sensitivity voltageTo digital signal S_DATAiCompare judgement to obtain
Level signal, thus the analogue signal of input is converted into the digital signal after threshold level multilevel iudge, input is to corresponding
Functional module.Then subsequent treatment is carried out by each functional module according to level signal.
As in figure 2 it is shown, functional module includes trigger module 5, protocol-analysis model 6, waveform searching module 7 in the present embodiment
4 functional modules are amounted to frequency measuring block 8.For trigger module 5 and waveform searching module 7, due to concrete triggering side
Formula or waveform searching mode are different, need a road or two paths of signals, i.e. need one group or two groups of threshold levels and threshold sensitivity
Voltage, wherein triggers and waveform searching needs the type of two paths of signals to have: owe width, slope, rise/fall time；Need a road
The type of signal has: edge, sequence, pulsewidth, logic, foundation and retention time violation, bus.If taking into account all modes,
So trigger module 5 and waveform searching module 7 needs to configure two digital comparators, protocol-analysis model 6 and frequency measurement mould
Block 8 respectively needs one group of threshold level and threshold sensitivity voltage, needs one digital comparator of each self-configuring.Understand numeral to compare
Device cijQuantity be to determine according to specifically arranging of functional module, understand each numeral in the present embodiment according to above analysis
Comparison module CiNeed to configure 6 digital comparators, i.e. M=6.
Fig. 3 is the structure chart of numeral comparison module in the present embodiment.As it is shown on figure 3, numeral comparison module in the present embodiment
Ci6 digital comparators in, digital comparator ci1And ci2Level signal export to trigger module 5, digital comparator ci3With
ci4Level signal export to waveform searching module 7, digital comparator ci5Level signal output to protocol-analysis model 6, number
Word comparator ci6Level signal export to frequency measuring block 8.
Digital comparator cijIn output level rule can be configured as required.Rule employed in the present embodiment
As follows:
If (a)Then digital comparator cijOutput high level 1；
If (b)Then digital comparator cijOutput low level 0；
If (c)Then digital comparator cijOutput keeps current level state not
Become.
In order to the technique effect of the present invention is better described, a specific embodiment is used to carry out experimental verification.This enforcement
In example, digital oscilloscope triggers and waveform searching type includes that edge, sequence, pulsewidth, deficient width, logic, foundation were disobeyed with the retention time
The types such as rule, slope, rise/fall time, bus；Protocal analysis type includes I2C、SPI、RS-232、USB、CAN、MIL-
STD-1553B、I2S/LJ/RJ/TDM, LIN, Ethernet, FlexRay etc.；Vertical direction has 10div, ADC resolution to be 8bit.
Below with edging trigger, edge waveform signature search, I2C protocal analysis, CH1Following operation (amplitude shelves are carried out as a example by frequency measurement
For 500mV/div).
Fig. 4 is the threshold level schematic diagram of various functions module in the present embodiment.As shown in Figure 4, the threshold of each functional module
Value level and threshold sensitivity are provided that
1) triggering menu, arrange triggering type be edge, trigger source be CH1, triggering level be 2.1V, threshold sensitivity
For 20mV；
2) at waveform searching menu, arrange search-type be edge, search passage be CH1, threshold level be 2.7V, threshold value
Sensitivity is 40mV；
3) at protocal analysis menu, arranging protocol type is I2C, type are 7bit address, SDL inputs is CH1, SDA input
For CH2, SDL threshold level be 1.3V, SDA threshold level be that 1.4V, SDL, SDA threshold sensitivity is 60mV；
4) at frequency measurement menu, Measurement channel CH is set1Opening, threshold level is 2.3V, and threshold sensitivity is 40mV.
In this experimental verification, ADC full scale is 500mV/div*10div=5V to induction signal amplitude peak voltage, institute
With numeral comparison module C1In digital comparator c11Threshold level V11Be 107, threshold sensitivityIt is 1；Numeral compares mould
Block C1In digital comparator c13Threshold level V13Be 137, threshold sensitivityIt is 2；Numeral comparison module C1In numeral
Comparator c15Threshold level V15Be 66, threshold sensitivityIt is 3, numeral comparison module C2In digital comparator c25Threshold
Value level V25Be 71, threshold sensitivityIt is 3；Numeral comparison module C1In digital comparator c16Threshold level V16For
117, threshold sensitivityIt is 2.
Therefore in this experimental verification, numeral comparison module C1In digital comparator c11Output level rule is as follows:
If (a) S_DATA1>=108, then digital comparator c11Output high level 1；
If (b) S_DATA1≤ 106, then digital comparator c11Output low level 0；
If (c) 106 ＜ S_DATA1＜ 108, then digital comparator c11Output keeps current level state constant.
Numeral comparison module C1In digital comparator c13Output level rule is as follows:
If (a) S_DATA1>=139, then digital comparator c13Output high level 1；
If (b) S_DATA1≤ 135, then digital comparator c13Output low level 0；
If (c) 135 ＜ S_DATA1＜ 139, then digital comparator c13Output keeps current level state constant.
Numeral comparison module C1In digital comparator c15Output level rule is as follows:
If (a) S_DATA1>=69, then digital comparator c15Output high level 1；
If (b) S_DATA1≤ 63, then digital comparator c15Output low level 0；
If (c) 63 ＜ S_DATA1＜ 69, then digital comparator c15Output keeps current level state constant.
Numeral comparison module C2In digital comparator c25Output level rule is as follows:
If (a) S_DATA2>=74, then digital comparator c25Output high level 1；
If (b) S_DATA2≤ 68, then digital comparator c25Output low level 0；
If (c) 68 ＜ S_DATA2＜ 74, then digital comparator c25Output keeps current level state constant.
Numeral comparison module C1In digital comparator c16Output level rule is as follows:
If (a) S_DATA1>=119, then digital comparator c16Output high level 1；
If (b) S_DATA1≤ 115, then digital comparator c16Output low level 0；
If (c) 115 ＜ S_DATA1＜ 119, then digital comparator c16Output keeps current level state constant.
Trigger module is according to 1) in the trigger parameter that arranges from channel C H1Digital comparator c11The digital signal of output is looked into
Look for qualified signal, if finding, generating and triggering signal, the most not generating triggering signal.
Waveform searching module is according to 2) in the waveform searching parameter that arranges from channel C H1Digital comparator c13The number of output
Word signal searches qualified signal, if found, labelling, the most not labelling.
Protocol-analysis model is according to 3) in the protocal analysis parameter that arranges from channel C H1Digital comparator c15And CH2's
Digital comparator c252 railway digital signals of output carry out protocol information extraction, and are analyzed according to I2C protocol specification.
Frequency measuring block is according to 4) in the frequency measurement parameter that arranges from channel C H1Digital comparator c16The number of output
Word signal carries out frequency measurement.
Understanding from the description above, the analog-digital signal conversion device of digital oscilloscope of the present invention is with existing " DAC+ compares
Device " technical scheme difference, " ADC+FPGA " technical scheme can be summarized as.As a example by the present embodiment, 4 functional module needs
Digital signal is produced by the digital comparison module within FPGA, then 4 digital comparison modules can use same clock,
Therefore the digital signal produced and the switching rate of comparator chip, circuit delay are unrelated, numeral comparison module and 4 merits simultaneously
Module can be realized by FPGA, use identical clock can reduce counting error further, count value produces relevant to signal.
Therefore, it is more accurate that the present invention is capable of the internal digital signal produced of FPGA, thus improves the accuracy of digital oscilloscope.
Assuming a width of 100M of ethernet signal band, signal rate 125MHz, using sample rate in the present embodiment is 5GSPS's
ADC, then be capable of the over-sampling of 40 times, 40 " 0 ", " 1 " data then can be analyzed by protocol-analysis model,
And the scheme of " DAC+ comparator " can only be to being analyzed less than 5 " 0 ", " 1 ", so for high speed protocol signal, using
The present invention can provide more initial data to protocol-analysis model, makes analysis result more accurate.
The sample rate of 5GSPS represents that the time difference between every 2 data points is 200ps simultaneously, namely compares through numeral
Time difference between 2 " 0 " that module is adjacent after changing, " 1 " signal is 200ps.And waveform in " DAC+ comparator " technical scheme
Search signal highest frequency is then relevant to the clock frequency of waveform searching module, and current FPGA internal system time clock is the highest
400MHz, corresponding temporal resolution is 2.5ns.In conjunction with nyquist sampling law, the present invention is capable of higher frequency
Waveform searching function and Search Results are more accurate.
Additionally, in the present invention digital comparator threshold sensitivity voltage can according to waveform quality by user setup, for
The signal of low signal-to-noise ratio can increase sensitivity voltage, and the signal for high s/n ratio can reduce sensitivity voltage.Therefore phase
For " DAC+ comparator " technical scheme, the threshold sensitivity of the present invention can be arranged flexibly, greatly facilitates user and observes sense
Interest waveform.
Owing to digital oscilloscope in the market mostly uses " ADC+FPGA " to realize its functional module, therefore existing
Being easy to extension on some digital oscilloscope platforms and realize the present invention, upgrading easily, can help manufacturing enterprise cost-effective.
Although detailed description of the invention illustrative to the present invention is described above, in order to the technology of the art
Personnel understand the present invention, the common skill it should be apparent that the invention is not restricted to the scope of detailed description of the invention, to the art
From the point of view of art personnel, as long as various change limits and in the spirit and scope of the present invention that determine in appended claim, these
Change is apparent from, and all utilize the innovation and creation of present inventive concept all at the row of protection.
Claims (2)
1. the analog-digital signal conversion device of a digital oscilloscope, it is characterised in that include a threshold level controller and N group
ADC ADCi, reduction of speed module SiWith numeral comparison module Ci, i=1,2 ..., N, wherein threshold level controller, reduction of speed module
Si, numeral comparison module CiAll realize in FPGA, often group ADC ADCi, reduction of speed module SiWith numeral comparison module CiCorresponding
One input signal channel；
Threshold level controller for according to user instruction generate each passage is corresponding in each functional module threshold level and
Threshold sensitivity voltage, wherein threshold level is designated as Vij, threshold sensitivity voltage is designated asWherein 0≤Vij≤2K-1,AndJ=1,2 ..., M, M represent the quantity of functional module, and K represents
The figure place of ADC；
ADC ADCiReceive corresponding signal condition channel C H respectivelyiInput signal, be converted into digital signal DATAi, send
Give corresponding reduction of speed module Si；
Reduction of speed module SiThe digital signal DATA that reception is obtainediCarry out reduction of speed and obtain digital signal S_DATAi, it is sent to correspondence
Numeral compare comparison module Ci；
Numeral comparison module CiIncluding M numeral comparison module device cij, each digital comparator cijReceive digital signal S_
DATAi, according to threshold level VijWith threshold sensitivity voltageTo digital signal S_DATAiCompare and obtain level signal,
Thus the analogue signal of input is converted into the digital signal after threshold level multilevel iudge, input is to corresponding function mould
Block.
Analog-digital signal conversion device the most according to claim 1, it is characterised in that described digital comparator cijComparison rule
As follows:
If (a)Then digital comparator cijOutput high level 1；
If (b)Then digital comparator cijOutput low level 0；
If (c)Then digital comparator cijOutput keeps current level state constant.
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Application publication date: 20161026 |