CN102710122A - Positive high-voltage charge pump - Google Patents
Positive high-voltage charge pump Download PDFInfo
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- CN102710122A CN102710122A CN2012101840661A CN201210184066A CN102710122A CN 102710122 A CN102710122 A CN 102710122A CN 2012101840661 A CN2012101840661 A CN 2012101840661A CN 201210184066 A CN201210184066 A CN 201210184066A CN 102710122 A CN102710122 A CN 102710122A
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Abstract
The invention relates to the technical field of an integrated circuit, and discloses a positive high-voltage charge pump. The charge pump comprises a charge pump circuit which is connected in multi-level series and a one-level output circuit; and the input end of the output circuit is connected with the output end of the last level charge pump circuit. According to the charge pump provided by the invention, an auxiliary circuit is added to reduce the PMOS (P-channel Metal Oxide Semiconductor) grid voltage in the charge pump circuit and increase the voltage difference of the grid electrode and the source electrode, thus, the PMOS grid voltage can be zero when the switch is switched on, and the voltage loss can be reduced during switching on and the PMOS conductive performance can be improved, thereby enhancing the capability of switch pumping charge.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of positive high voltage charge pump.
Background technology
Charge pump circuit is as one of basic module of EEPROM/Flash memory, determined the initial programming of EEPROM/Flash/wipe/reading speed to a great extent.Along with the progress of integrated circuit fabrication process, to the pursuit of low-power consumption, the supply voltage of integrated circuit constantly descends.On the other hand, in the Flash memory, the required high voltage of the program/erase operations of unit descends to some extent, but is much more slowly than the decrease speed of supply voltage.Make that like this charge pump circuit progressively shows its important effect and status in the continuous evolution of integrated circuit.In the design of EEPROM/Flash memory, the research of various High Performance Charge Pumps is become gradually one of focus of current integrated circuit research.
Charge pump is also referred to as the switched capacitor voltage changer, be a kind of utilize so-called " fast " (flying) or " pumping " electric capacity (but not inductance or transformer) come the DC-DC (DC-DC converter) of energy storage.They can make input voltage raise or reduce; Also can be used to produce negative voltage charge pump; It utilizes inner field-effect transistor (Field Effect Transistor, FET) the switch arrays transmission of electric charge, discharging and recharging with electric capacity in the clock signal control charge pump usually on the control capacitance in some way; Thereby input voltage is raise (or reduction) in some way, to reach needed output voltage.
Desirable CMOS charge pump model the earliest is that J.Dickson proposed in 1976; Its basic thought is an one-way flow of utilizing the metal-oxide-semiconductor restriction electric charge of diode; And the build-up effect of electric charge producing high pressure through electric capacity, sort circuit was for erasable EPROM is provided needed voltage at that time.People such as J.Witters, Toru Tranzawa improved the charge pump model of J.Dickson afterwards, had proposed more accurate theoretical model, and confirmed to have proposed the series of theories formula through experiment.Along with the continuous development of integrated circuit, according to scaled principle, supply voltage constantly descends, and in some circuit application, required voltage can not descend according to dwindling of technology, and the application of charge pump in integrated circuit more and more widely like this.
In the integrated circuit technology of standard, NMOS all is produced on the same substrate, makes like this in the charge pump of NMOS as switch, to have serious substrate bias effect.PMOS is as switch, and its substrate can be drawn separately, does not have substrate bias effect, and the substrate bias effect in the time of can overcoming NMOS as switch well reduces in the voltage transmission process because the loss of voltage that switch causes significantly.
Fig. 1 is a level Four Dickson positive high voltage charge pump circuit schematic diagram.Symbol T representes input voltage source among the figure; Symbol
expression NMOS pipe, wherein CK1 and CK2 are two clock signals that do not overlap mutually.
Fig. 2 is the level Four Dickson positive high voltage charge pump circuit schematic diagram of PMOS as switch, symbol
expression PMOS pipe.
Factors such as the amplitude of oscillation of clock, the threshold value of metal-oxide-semiconductor and parasitic capacitance determined each grade charge pump voltage can lifting (or reduction) the voltage maximum amplitude.The existence of metal-oxide-semiconductor threshold value and rising directly have influence on the quantity of electric charge of each grade of charge pump pumping, thereby finally influence rise of output voltage speed and the highest exportable voltage.
Summary of the invention
The technical problem that (one) will solve
The technical problem that the present invention will solve is: at PMOS is in the charge pump of switch, how to dwindle the voltage rise time, improves rate of voltage rise.
(2) technical scheme
In order to solve the problems of the technologies described above, the present invention provides a kind of positive high voltage charge pump, comprises the charge pump circuit of plural serial stage, and the one-level output circuit, and the input of said output circuit is connected with the output of the said charge pump circuit of afterbody;
Wherein, The said charge pump circuit of each grade comprises a NMOS pipe, two PMOS pipes and a capacitor; The drain electrode and the substrate of one end of said capacitor, PMOS pipe; And source electrode and the substrate of the 2nd PMOS pipe be connected together, and as the output of charge pump circuit at the corresponding levels, the drain electrode and the first gate pmos utmost point that the drain electrode of the 2nd PMOS pipe, NMOS manage are connected together; The grid of said NMOS pipe links to each other with control signal; The other end of said capacitor links to each other with clock signal; Source electrode, the substrate ground connection of said NMOS pipe; The source electrode of the one PMOS pipe links to each other with the grid of the 2nd PMOS pipe, as the input of charge pump circuit at the corresponding levels, links to each other with the output of input voltage or upper level charge pump circuit.
Said output circuit is that said charge pump circuit is removed the circuit that forms after the capacitor.
Preferably; Said charge pump circuit has level Four; The other end of the electric capacity in the first order, the third level charge pump circuit is connected with the first clock signal C K1; The other end of the electric capacity in the second level and the fourth stage charge pump circuit is connected with second clock signal CK2; The grid of the NMOS pipe in the first order, third level charge pump circuit and the said output circuit is connected with the first control signal CTL1, and the grid of the NMOS pipe in the second level, the fourth stage charge pump circuit is connected with the second control signal CTL2, and the first clock signal C K1 does not overlap with second clock signal CK2 two mutually.
Preferably, the first control signal CTL1 produces according to the first clock signal C K1, and the second control signal CTL2 produces according to second clock signal CK2.
Preferably, the following jumping edge that the edge is later than the corresponding first clock signal C K1 is jumped in going up of the first control signal CTL1, and the second control signal CTL2 goes up jumping along the following jumping edge that is later than corresponding second clock signal CK2; The following of the first control signal CTL1 jumped along jumping the edge early than going up of the corresponding first clock signal C K1, and the following of the second control signal CTL2 jumped along jumping the edge early than going up of corresponding second clock signal CK2.
(3) beneficial effect
Technique scheme has following advantage: reduce PMOS grid voltage in the charge pump circuit through increasing auxiliary circuit; Improve the voltage difference of its grid and source electrode; The PMOS grid voltage is zero when making switch conduction; Thereby the loss of voltage when reducing conducting also improves the PMOS conduction property, thereby strengthens switch thus pumps charges ability.
Description of drawings
Fig. 1 is the level Four Dickson positive high voltage charge pump circuit schematic diagram of switch for NMOS;
Fig. 2 is the level Four Dickson positive high voltage charge pump circuit schematic diagram of switch for PMOS;
Fig. 3 is the circuit theory diagrams according to the single-stage positive high voltage charge pump of one embodiment of the present invention;
Fig. 4 is the circuit theory diagrams according to the positive high voltage charge pump output stage of one embodiment of the present invention;
Fig. 5 is the circuit theory diagrams according to the level Four positive high voltage charge pump of one embodiment of the present invention;
Fig. 6 is the waveform input signal sketch map according to one embodiment of the present invention;
Fig. 7 is level Four positive high voltage charge pump and level Four PMOS switch Dickson positive high voltage charge pump output ceiling voltage-output load current curve comparison diagram according to one embodiment of the present invention;
Fig. 8 for according to the level Four positive high voltage charge pump of one embodiment of the present invention and level Four PMOS switch Dickson positive high voltage charge pump output voltage the rise time-output load current curve comparison diagram;
Fig. 9 is level Four positive high voltage charge pump and the level Four PMOS switch Dickson positive high voltage charge pump output voltage rate of rise-output load current curve comparison diagram according to one embodiment of the present invention;
Figure 10 is for exporting ceiling voltage-output load current curve comparison diagrams according to the secondary of one embodiment of the present invention, Pyatyi, eight grades of positive high voltage charge pumps with secondary, Pyatyi, eight grades of PMOS switch Dickson positive high voltage charge pumps;
Figure 11 for according to the secondary of one embodiment of the present invention, Pyatyi, eight grades of positive high voltage charge pumps and secondary, Pyatyi, eight grades of PMOS switch Dickson positive high voltage charge pump output voltages the rise time-output load current curve comparison diagram;
Figure 12 is for according to the secondary of one embodiment of the present invention, Pyatyi, eight grades of positive high voltage charge pumps and secondary, Pyatyi, the eight grades of PMOS switch Dickson positive high voltage charge pump output voltage rate of rise-output load current curve comparison diagrams.
Embodiment
Below in conjunction with accompanying drawing and embodiment, specific embodiments of the invention describes in further detail.Following examples are used to explain the present invention, but are not used for limiting scope of the present invention.
Core concept of the present invention reduces PMOS grid voltage in the charge pump circuit for increasing auxiliary circuit; PMOS charge pump master branch road wherein; Under the control of PMOS grid voltage control auxiliary branch, electric charge is carried out one-way flow, stored charge reaches the effect of lifting voltage; PMOS grid voltage control auxiliary branch utilizes in the PMOS charge pump master branch road PMOS switching tube grid voltage in the voltage node and input control signal control PMOS charge pump master branch road; Improve the voltage difference of grid and source electrode, the PMOS grid voltage is zero when making switch conduction, improves the voltage difference of its grid and source electrode; Improve its charge transport ability; Thereby improve the maximum exportable voltage of charge pump, reduce the charge pump output voltage rise time, the loss of voltage when reducing conducting also improves the PMOS conduction property; Improve rate of voltage rise, thereby strengthen switch thus pumps charges ability.Integrated circuit comprises two parts: one, PMOS charge pump master branch road; Two, PMOS grid voltage control auxiliary branch.The PMOS of first charge pump master branch road utilizes the PMOS switch, in conjunction with clock signal, and the flow direction of electric charge in the control capacitance; Second portion PMOS grid voltage control auxiliary branch is dynamically controlled PMOS switch gate voltage in the first; Thereby reach the effect that improves PMOS switching tube ducting capacity in the PMOS of the first charge pump master branch road; Final under identical circuit condition; Improve the final exportable voltage of circuit, and reduced the voltage rise time.
Particularly, as shown in Figure 4, according to the level Four PMOS switch-charge pump of one embodiment of the present invention, comprising: PMOS switch-charge pump master branch road, (MP0～MP4) and four capacitors are formed by five PMOS pipes; PMOS grid voltage control auxiliary branch is made up of five auxiliary PMOS pipe MPX0～MPX4 and five auxiliary NMOS pipe MNX0～MNX4.Wherein, The grid of the source electrode of the one PMOS pipe MP0, the first auxiliary PMOS pipe MPX0 links to each other with input voltage VDD; The end of first to fourth capacitor C1～C4 links to each other with first to fourth PMOS pipe MP0～MP3 drain electrode and substrate respectively; The end of first to fourth capacitor C1～C4 also links to each other with first to fourth auxiliary PMOS pipe MPX0～MPX3 source electrode and substrate respectively; The end of first to fourth capacitor C1～C4 also links to each other with second to the 5th PMOS pipe MP1～MP4 source electrode respectively; In addition; The end of first to fourth capacitor C1～C4 also links to each other with second to the 5th auxiliary PMOS pipe MPX1～MPX4 grid respectively, and the other end of the first, the 3rd capacitor C1, C3 links to each other with the first clock signal C K1 of two phase clock signal, and the other end of the second, the 4th capacitor links to each other with the second clock signal CK2 of two phase clock signal; First to the 5th PMOS pipe MP0～MP4 grid links to each other with first to the 5th auxiliary PMOS pipe MPX0～MPX4 drain electrode respectively; In addition, first to the 5th PMOS pipe MP0～MP4 grid also links to each other with first to the 5th auxiliary NMOS pipe MNX0～MNX1 drain electrode, and first to the 5th auxiliary NMOS pipe MNX0～MNX4 source electrode and substrate are connected to ground; The first, the 3rd, the 5th auxiliary NMOS tube grid is connected to first control signal CTL1 in two control signals, and the second, the 4th auxiliary NMOS tube grid is connected to second control signal CTL2 in two control signals.MP4 drain electrode of the 5th PMOS pipe and substrate link together, and the 5th auxiliary PMOS pipe MPX4 source electrode and substrate link together, as voltage output end Vout.
Wherein, Shown in accompanying drawing 6; Two control signals (CTL1, CTL2) produce according to the two phase clock signal; Following characteristics are arranged: the following jumping edge that the edge slightly is later than the corresponding first clock signal C K1 is jumped in going up of the first control signal CTL1, and the second control signal CTL2 goes up jumping along the following jumping edge that slightly is later than corresponding second clock signal CK2; The following of the first control signal CTL1 jumped along slightly jumping the edge early than going up of corresponding first clock signal, and the following of the second control signal CTL2 jumped along slightly jumping the edge early than going up of corresponding second clock signal.
Clock signal C K1, CK2 and the control signal CTL1 that two phases do not overlap, the state that CTL2 determines the PMOS switching tube jointly; The voltage difference of PMOS switching tube source electrode and grid is increased; Improve PMOS switching tube ducting capacity; Reduce the loss of voltage, improve final output voltage, reduce the rise time of charge pump.Its concrete course of work is following: when CK1 is that low level, CK2 are high level when beginning, CTL1, CTL2 are low level, and MP0 pipe left end voltage is higher than right-hand member voltage, the MP0 conducting, and VDD charges to V with node N1
1'=VDD-|V
Thp|, V wherein
ThpBe the threshold voltage of MP0, this moment, MPX0 tube grid voltage was lower than source voltage, and MPX0 breaks off, and CTL1 is 0, and MNX0 also breaks off, and X1 becomes the suspension node; Afterwards, CTL1 is 1, and the MNX0 conducting makes that to the X1 node electric charge of releasing the MP0 tube grid is 0, and the MP0 ducting capacity strengthens, and since the difference (VDD-0=VDD) of source voltage and grid voltage greater than the absolute value of PMOS pipe threshold, VDD charges to V to the N1 node once more
1p=VDD; CTL1 becomes 0 then, and MNX0 breaks off, and X1 becomes the suspension node once more; When CK1 converts high level CK2 into and converts low level into, N1 node level rising, the MPX0 grid voltage is lower than source voltage will begin conducting; To the X1 charging, MP1 pipe source voltage also will be higher than grid voltage simultaneously, and MP1 manages conducting; Node N1, N2, X1 carry out charge transfer at this moment; Wherein N1 is identical with the X1 current potential, and the N2 node is than both lower slightly PMOS threshold voltages, and MP0 manages disconnection; CTL2 converts high level into afterwards, and MNX1 manages conducting, and nodes X 2 is discharged to 0, and MP1 pipe ducting capacity strengthens, and no longer has the threshold value loss, and node N1, X1, N2 reach common level V
1(VDD＜V
1＜V
1p+ VDD=2VDD); CTL2 is converted to low level then, and MNX1 breaks off, and X2 becomes the suspension node; Get worse and be high level along with CK1 converts low level CK2 into, N1 node level is pulled to V by the CK1 signal through capacitor C 1
1With node N1 charging, N2 node level is raised to V by the CK2 signal through capacitor C 2 once more for-VDD＜VDD, VDD
1+ VDD, the MP2 conducting, node N2 charges to node N3; Afterwards, CTL1 becomes high level, MNX0, MNX2 conducting, and X1, X3 are pulled to 0, and node N1 is recharged to VDD once more, and node N2, N3 do not have the electric charge of threshold value loss to share.Along with the continuous upset of clock signal and control signal, electric charge constantly reaches node Vout (being output) from VDD, makes the output electric charge constantly accumulate, and voltage constantly is lifted.
PMOS switch Dickson charge pump and charge pump of the present invention to shown in Figure 2 carry out emulation; Fig. 7 has provided the variation along with load current; The peaked data of output voltage can be found out, because this inventive principle has improved the charge transport ability of PMOS pipe in the charge pump; The charge pump that designs compare with common PMOS switch Dickson charge pump, under identical load current, higher output voltage can be provided.
Fig. 8 has provided the variation along with load current; Output end voltage rises to the required time graph of the corresponding maximum of output voltage 80% by 0; Can find out; The charge pump that designs compare with common PMOS switch Dickson charge pump, under the same load current situation, can in the shorter time, reach 80% of maximum output voltage.
Fig. 9 has provided the variation along with load current; Output end voltage is by the 0 G-bar comparison diagram that rises in corresponding maximum 80% process of output voltage; Can find out; The charge pump that designs compare with common PMOS switch Dickson charge pump, under identical load current, significantly have the higher rate of rise.
Figure 10 has provided under different progression (secondary, Pyatyi, the eight grades) situation; The output voltage maximum is with the comparative result of load current size variation curve; Can find out, under different progression charge pump situation, the charge pump that designs all can provide than original higher output voltage; And along with the increase of load current, advantage is obvious further.
Figure 11 has provided under different progression (secondary, Pyatyi, the eight grades) situation; Rise time is with the comparative result of load current size variation curve; Can find out; The charge pump that designs compare with common PMOS switch Dickson charge pump, under identical load current condition, all can reach 80% of maximum output voltage faster.
Figure 12 has provided under different progression (secondary, Pyatyi, the eight grades) situation; The voltage rate of rise is with the comparative result of load current size variation curve; Can find out; Along with the increase of charge pump progression, the circuit voltage rate of rise that designs descends to some extent, still has the obviously bigger rate of rise but compare with common PMOS switch Dickson charge pump.
Can find out by above embodiment; The present invention reduces PMOS grid voltage in the charge pump circuit through increasing auxiliary circuit; Improve the voltage difference of its grid and source electrode; The PMOS grid voltage is zero when making switch conduction, thus the loss of voltage when reducing conducting and improve the PMOS conduction property, thus strengthen switch thus pumps charges ability.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from know-why of the present invention; Can also make some improvement and replacement, these improvement and replacement also should be regarded as protection scope of the present invention.
Claims (4)
1. a positive high voltage charge pump is characterized in that, comprises the charge pump circuit of plural serial stage, and the one-level output circuit, and the input of said output circuit is connected with the output of the said charge pump circuit of afterbody;
Wherein, The said charge pump circuit of each grade comprises a NMOS pipe, two PMOS pipes and a capacitor; The drain electrode and the substrate of one end of said capacitor, PMOS pipe; And source electrode and the substrate of the 2nd PMOS pipe be connected together, and as the output of charge pump circuit at the corresponding levels, the drain electrode and the first gate pmos utmost point that the drain electrode of the 2nd PMOS pipe, NMOS manage are connected together; The grid of said NMOS pipe links to each other with control signal; The other end of said capacitor links to each other with clock signal; Source electrode, the substrate ground connection of said NMOS pipe; The source electrode of the one PMOS pipe links to each other with the grid of the 2nd PMOS pipe, as the input of charge pump circuit at the corresponding levels, links to each other with the output of input voltage or upper level charge pump circuit.
Said output circuit is that said charge pump circuit is removed the circuit that forms after the capacitor.
2. positive high voltage charge pump as claimed in claim 1; It is characterized in that; Said charge pump circuit has level Four; The other end of the electric capacity in the first order, the third level charge pump circuit is connected with the first clock signal C K1, and the other end of the electric capacity in the second level and the fourth stage charge pump circuit is connected with second clock signal CK2, and the grid of the NMOS pipe in the first order, third level charge pump circuit and the said output circuit is connected with the first control signal CTL1; The grid of the NMOS pipe in the second level, the fourth stage charge pump circuit is connected with the second control signal CTL2, and the first clock signal C K1 does not overlap with second clock signal CK2 two mutually.
3. positive high voltage charge pump as claimed in claim 2 is characterized in that, the first control signal CTL1 produces according to the first clock signal C K1, and the second control signal CTL2 produces according to second clock signal CK2.
4. positive high voltage charge pump as claimed in claim 3 is characterized in that, the following jumping edge that the edge is later than the corresponding first clock signal C K1 is jumped in going up of the first control signal CTL1, and the second control signal CTL2 goes up jumping along the following jumping edge that is later than corresponding second clock signal CK2; The following of the first control signal CTL1 jumped along jumping the edge early than going up of the corresponding first clock signal C K1, and the following of the second control signal CTL2 jumped along jumping the edge early than going up of corresponding second clock signal CK2.
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| CN201210184066.1A CN102710122B (en) | 2012-06-05 | 2012-06-05 | Positive high-voltage charge pump |
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| CN201210184066.1A CN102710122B (en) | 2012-06-05 | 2012-06-05 | Positive high-voltage charge pump |
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| CN102710122B CN102710122B (en) | 2014-04-23 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107733223A (en) * | 2017-11-16 | 2018-02-23 | 上扬无线射频科技扬州有限公司 | Charge pump compress cell circuit |
| CN109842290A (en) * | 2017-11-24 | 2019-06-04 | 北京兆易创新科技股份有限公司 | A kind of high pressure bleeder circuit, charge pump circuit and NOR FLASH |
| CN113110684A (en) * | 2021-03-30 | 2021-07-13 | 东方微电科技(武汉)有限公司 | Power supply voltage output integrated circuit for magnetic sensing |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107733223A (en) * | 2017-11-16 | 2018-02-23 | 上扬无线射频科技扬州有限公司 | Charge pump compress cell circuit |
| CN107733223B (en) * | 2017-11-16 | 2024-03-01 | 上扬无线射频科技扬州有限公司 | Charge pump boosting unit circuit |
| CN109842290A (en) * | 2017-11-24 | 2019-06-04 | 北京兆易创新科技股份有限公司 | A kind of high pressure bleeder circuit, charge pump circuit and NOR FLASH |
| CN113110684A (en) * | 2021-03-30 | 2021-07-13 | 东方微电科技(武汉)有限公司 | Power supply voltage output integrated circuit for magnetic sensing |
| CN113110684B (en) * | 2021-03-30 | 2022-05-17 | 东方微电科技(武汉)有限公司 | Power supply voltage output integrated circuit for magnetic sensing |
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