CN102692879B - A kind of one line control circuit and chip - Google Patents
A kind of one line control circuit and chip Download PDFInfo
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- CN102692879B CN102692879B CN201110073454.8A CN201110073454A CN102692879B CN 102692879 B CN102692879 B CN 102692879B CN 201110073454 A CN201110073454 A CN 201110073454A CN 102692879 B CN102692879 B CN 102692879B
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Abstract
The present invention is applicable to integrated circuit fields, provide a kind of one line control circuit and chip, comprise: its input end is the status toggle unit of described chip one pin, quick cell and unit at a slow speed, described status toggle unit judges outside logic input signal, export activation signal and control described quick cell or described unit activating at a slow speed, control multiple mode bit internally circuit export many bit logic signal or control single status position internally circuit export single-bit logical signal.The present invention is by having the status toggle unit receive logic input signal of external pin, activation quick cell or at a slow speed unit, the many bit logic signal of corresponding output or single-bit logical signal control multiple mode bit or the single status position of internal circuit, realize one line control, meet the requirement of a small amount of pin package chip, simplify the peripheral applications environment of circuit, reduce packaging cost.
Description
Technical field
The invention belongs to integrated circuit fields, particularly relate to a kind of one line control circuit and chip.
Background technology
Along with improving constantly of integrate circuit function closeness, in chip internal circuits, need the change with several functions or performance to meet different application.At present, the circuit of high integration all can be transmitted by data, is controlled each mode bit of internal circuit by external signal, and with the change of realizing circuit function or performance, but this data transmission needs follow specific bus protocol, as I
2c (Inter Integrated Circuit) bus protocol, SPI (Serial Peripheral interface) agreement etc., therefore need multiple external signal port to carry out data and transmit the control realizing internal circuit status position.
But, for Small Scale Integration, only need the mode bit of relatively small amount control internal circuit, when peripheral applied environment is succinct, so various external signal port makes Data Transport Protocol become relative complex, in addition, one is required with the little circuit of 4,8 or 16 pin package, when meeting circuit core function and performance completely, chip can not have enough pins to add this host-host protocol, to such an extent as to the requirement of a small amount of pin package cannot be realized, increase the cost of IC encapsulation.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of one line control circuit, is intended to solve Small Scale Integration and cannot realizes a small amount of pin package, peripheral applications circumstance complication, and the problem that packaging cost is high.
The embodiment of the present invention is achieved in that a kind of one line control circuit, is packaged in chip internal, and described one line control circuit comprises:
Status toggle unit, its input end is described chip one pin, described status toggle unit judges outside logic input signal, when logic input signal is fast logic signal, described one line control circuit is switched to quick mode, corresponding exports quick active signal, when logic input signal be at a slow speed logical signal time, described one line control circuit is switched to slow speed mode, corresponding output slow active signal;
Quick cell, its control end is connected with the output terminal of described status toggle unit, input end is connected with the input end of described status toggle unit, clock signal terminal is connected with internal circuit, feedback output end is connected with the reset terminal of described status toggle unit, described quick cell is activated when receiving quick active signal, responds under the effect of clock signal to the Rapid Variable Design composition of logic input signal, control multiple mode bit internally circuit export many bit logic signal; And
Unit at a slow speed, its control end is connected with the output terminal of described status toggle unit, input end is connected with the input end of described status toggle unit, described unit is at a slow speed activated when receiving slow active signal, the varying component at a slow speed of logic input signal is responded, controls single status position internally circuit output single-bit logical signal;
Described quick cell comprises:
Timing module, for according to clock signal, output gets the location time and to described status toggle unit feedback reset signal, the clock control end of described timing module is the clock signal terminal of described quick cell, the feedback signal output of described timing module is the feedback output end of described quick cell, and the reset terminal of described timing module is the control end of described quick cell;
Get location module, the location time is got for basis, export effective status bit address, the location time output terminal of getting of described location time of the getting input end and described timing module of getting location module is connected, the described input end of clock getting location module is the input end of described quick cell, described in get location module Enable Pin be the control end of described quick cell;
Assignment module, for getting under the time of location effective status bit address assignment, be many bit logic signal by the Rapid Variable Design composition conversion in logic input signal, location time of the getting input end of described assignment module is connected with the location time output terminal of getting of described timing module, the address input end of described assignment module is connected with the described address output end getting location module, the logic signal input end of described assignment module is the input end of described quick cell, and the address inverting input of described assignment module is connected with the secondary address reversed-phase output getting location module.
Another object of the embodiment of the present invention is to provide a kind of chip adopting above-mentioned one line control circuit.
In embodiments of the present invention, by having the status toggle unit receive logic input signal of external pin, activation quick cell or at a slow speed unit, the many bit logic signal of corresponding output or single-bit logical signal control multiple mode bit or the single status position of internal circuit, realize one line control, meet the requirement of a small amount of pin package chip, simplify the peripheral applications environment of circuit, reduce packaging cost.
Accompanying drawing explanation
The scantling plan of the one line control circuit that Fig. 1 provides for one embodiment of the invention;
The topology example figure of the quick cell of the one line control circuit that Fig. 2 provides for one embodiment of the invention and at a slow speed unit;
The exemplary circuit structural drawing of the timing module of the status toggle unit that Fig. 3 provides for one embodiment of the invention and quick cell;
The exemplary circuit structural drawing getting location module of the quick cell that Fig. 4 provides for one embodiment of the invention;
The exemplary circuit structural drawing of the assignment module of the quick cell that Fig. 5 provides for one embodiment of the invention;
The exemplary circuit structural drawing of the unit at a slow speed that Fig. 6 provides for one embodiment of the invention;
The logical waveform sequential chart of 2 change-over periods of one line control circuit that Fig. 7 provides for one embodiment of the invention;
The sequential chart of cell operation at a slow speed that Fig. 8 provides for one embodiment of the invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Logic input signal is converted into many bit logic signal or single-bit logical signal by means of only a logic input signal end by the embodiment of the present invention, realizes the mode bit controlling internal circuit fast or at a slow speed.
Fig. 1 illustrates the general construction of the one line control circuit that the embodiment of the present invention provides, and for convenience of explanation, illustrate only part related to the present invention.
As the one line control circuit that one embodiment of the invention provides, be packaged in chip, this one line control circuit comprises:
Status toggle unit 11, its input end is chip one pin, status toggle unit 11 judges outside logic input signal, when logic input signal is fast logic signal, export quick active signal, this one line control circuit be switched to quick mode, when logic input signal be at a slow speed logical signal time, export slow active signal, this one line control circuit is switched to slow speed mode;
Quick cell 12, its control end is connected with the output terminal of status toggle unit 11, input end is connected with the input end of status toggle unit 11, clock signal terminal is connected with internal circuit 14, feedback output end is connected with the reset terminal of status toggle unit 11, this quick cell 12 is activated when receiving quick active signal, responds under the effect of clock signal to the Rapid Variable Design composition of logic input signal, control multiple mode bit internally circuit 14 export many bit logic signal; And
Unit 13 at a slow speed, its control end is connected with the output terminal of status toggle unit 11, input end is connected with the input end of status toggle unit 11, this at a slow speed unit 13 be activated when receiving slow active signal, respond to the varying component at a slow speed of logic input signal, control single status position internally circuit 14 exports single-bit logical signal.
Below in conjunction with specific embodiment, realization of the present invention is described in detail.
Fig. 2 illustrates the sub modular structure example of the one line control circuit that the embodiment of the present invention provides, and for convenience of explanation, illustrate only part related to the present invention.
As one embodiment of the invention, quick cell 12 comprises:
According to clock signal C lock, export and get location time Add_time and to the timing module 121 of status toggle unit 11 feedback reset signal Reset, its clock control end is the clock signal terminal of quick cell 12, feedback signal output is the feedback output end of quick cell 12, and reset terminal is the control end of quick cell 12;
According to getting location time Add_time, what export effective status bit address Add gets location module 122, it is got location time input end and is connected with the location time output terminal of getting of timing module 121, and input end of clock is the input end of quick cell 12, and Enable Pin is the control end of quick cell 12;
Getting under location time Add_time effective status bit address Add assignment, by the assignment module 123 that the Rapid Variable Design composition conversion in logic input signal is many bit logic signal, it is got location time input end and is connected with the location time output terminal of getting of timing module 121, address input end is connected with the address output end getting location module 122, logic signal input end is the input end of quick cell 12, and address inverting input is connected with the secondary address reversed-phase output getting location module 122.
In an initial condition, quick cell 12 is in dormant state, and unit 13 is in state of activation at a slow speed, and logic input signal passes through unit 13 at a slow speed and is converted to the output of single-bit logical signal, this conversion only to logic input signal delay disposal slightly, does not change the logic state of its signal.
Until when logic input signal first time, logic state changed, namely using the negative edge of logic input signal or rising edge as trigger condition, change-over period starts, one line control circuit is switched to quick mode by status toggle unit 11, and export quick active signal, quick cell 12 is activated, simultaneously, unit 13 enters dormant state at a slow speed, and the single-bit logical signal of output is maintained at the logic state before dormancy, no longer affects by logic input signal.
As one embodiment of the invention, can set quick active signal is high level, then slow active signal is low level; Also can set quick active signal is low level, then slow active signal is high level.
After quick cell 12 is activated, under the effect of clock signal, timing by timing module 121, and export get the location time to getting location module 122 and assignment module 123, get in the time of location at this, by the rising edge number of getting location module 122 statistic logic input signal, and using the mode bit address of the number of rising edge as many bit logic signal.At the end of getting the location time, namely at assignment point, assignment module 123, by crawl logic input signal logic state now, carries out assignment to the mode bit of corresponding address in many bit logic signal.After completing assignment, the assignment of quick cell 12 hold mode position, enters dormant state.One line control circuit is switched to slow speed mode by status toggle unit 11, and unit 13 enters state of activation again at a slow speed, and quick cell 12 enters dormant state, and one line control circuit gets back to original state, completes a change-over period.
As one embodiment of the invention, can using the single rising edge of logic input signal or multiple rising edge as counting condition, also can using the single negative edge of logic input signal or multiple negative edge as counting condition.
In embodiments of the present invention, the logic change of logic input signal within the change-over period belongs to Rapid Variable Design composition, is responded by quick cell 12; The logic change of logic input signal outside the change-over period belongs to varying component at a slow speed, is responded by unit 13 at a slow speed.
Fig. 3 illustrates the exemplary circuit structure of the status toggle unit that one embodiment of the invention provides and timing module, for convenience of explanation, illustrate only part related to the present invention.
As one embodiment of the invention, status toggle unit 11 comprises phase inverter INV0, d type flip flop DFF1, delayer Delay0 and diode Diode, the input end of phase inverter INV0 is the input end of status toggle unit 11, the output terminal of phase inverter INV0 is connected with the input end of clock of d type flip flop DFF1, the data input pin of d type flip flop DFF1 connects high level, the reset terminal of d type flip flop DFF1 is the reset terminal of status toggle unit 11, the data output end of d type flip flop DFF1 is connected with the input end of delayer Delay0, the output terminal of delayer Delay0 is connected with the negative electrode of diode Diode, tie point is the output terminal of status toggle unit 11, the plus earth of diode Diode.
Timing module 121 can be counter, the first data input pin of counter connects high level, the input end of clock of counter is the clock control end of timing module 121, the reset terminal of counter is the reset terminal of timing module 121, the last digit of counter is the feedback signal output of timing module 121 according to reversed-phase output, the secondary last digit of counter according to output terminal be timing module 121 get location time output terminal.
In embodiments of the present invention, with four digit counters be made up of d type flip flop DFF2, d type flip flop DFF3, d type flip flop DFF4, d type flip flop DFF5 for realizing example, being described, being to be understood that, can also increase or reduce the quantity of trigger during specific implementation, its annexation repeats no more.
In embodiments of the present invention, after diode Diode ensures that circuit powers on, the original state of activation signal Enable is 0.As reset signal Reset=1, trigger during first negative edge of logic input signal, make activation signal Enable=1.
As one embodiment of the invention, when can make Enable=1, this activation signal Enable is quick active signal, and when making Enable=0, this activation signal Enable is slow active signal.
Clock is reference clock, can by generations such as the crystal oscillating circuit in internal circuit, phaselocked loop or oscillators.
Fig. 4 illustrates and the exemplary circuit structure of getting location module that one embodiment of the invention provides for convenience of explanation, illustrate only part related to the present invention.
Get location module 122 and comprise counter, phase inverter INV1 and rejection gate NOR1, the input end of phase inverter INV1 be get location module 122 get location time input end, an input end of the output terminal AND OR NOT gate NOR1 of phase inverter INV1 connects, another input end of rejection gate NOR1 be get location module 122 get location time input end, the output terminal of rejection gate NOR1 is connected with the reset terminal of counter, the first data input pin of counter connects high level, the input end of clock of counter is the input end of clock getting location module 122, every data output end of counter is the address output end getting location module 122, the first data inversion output terminal of counter is unsettled, secondary bit data reversed-phase output OPADD reverse signal AddB.
In embodiments of the present invention, address inversion signal Add (N) B, Add (N-1) B ... Add1B is the inversion signal of address bit Add [N:0].
In embodiments of the present invention, with four digit counters be made up of d type flip flop DFF6, d type flip flop DFF7, d type flip flop DFF8, d type flip flop DFF9 for realizing example, the rising edge be used in computational logic input signal, and export four bit address positions Add [3:0], the quantity of trigger can also be increased or reduce when should be appreciated that specific implementation, to adapt to the needs of address bit, this address bit Add [3:0] follows thermometer code establishment, is used for judging that whether one of four states bit address is effective.
When getting location time Add_time=0, and during activation signal Enable=1, counter is activated, and gets location module 122 and starts to carry out getting location, and counter can according to the rising edge number of logic input, corresponding change address bit.If only have a rising edge, address bit Add [3:0]=0001, first mode bit address is effective; If there are three rising edges, address bit Add [3:0]=0111, the 3rd mode bit address is effective, in like manner can push away.
Fig. 5 illustrates the exemplary circuit structure of the assignment module that one embodiment of the invention provides, and for convenience of explanation, illustrate only part related to the present invention.
Assignment module 123 comprises d type flip flop DFF10, d type flip flop DFF11, d type flip flop DFF12, d type flip flop DFF13, phase inverter INV10, phase inverter INV11, phase inverter INV12, phase inverter INV13, phase inverter INV14, three end input nand gate NAND0, three end input nand gate NAND1, three end input nand gate NAND2 and two end input nand gate NAND4, the data input pin of d type flip flop DFF10 and d type flip flop DFF11 is the logic signal input end of assignment module 123, d type flip flop DFF12 is connected with the data input pin of d type flip flop DFF13 and is connected with the output terminal of phase inverter INV14 simultaneously, the input end of phase inverter INV14 is the logic signal input end of assignment module 123, d type flip flop DFF10, d type flip flop DFF11, d type flip flop DFF12 is all connected high level with the reset terminal of d type flip flop DFF13, and the logical signal output terminal that the data output end of d type flip flop DFF10 and d type flip flop DFF11 is respectively assignment module 123 exports many bit logic signal Reg0, Reg1, the logical signal output terminal that the data back output terminal of d type flip flop DFF12 and d type flip flop DFF13 is respectively assignment module 123 exports many bit logic signal Reg2, Reg3, three end input nand gate NAND0, three end input nand gate NAND1, two input ends of three end input nand gate NAND2 and two end input nand gate NAND4 are the address input end of assignment module 123 respectively and get location time input end, three end input nand gate NAND0, an other input end of three end input nand gate NAND1 and three end input nand gate NAND2 is the anti-phase address input end of assignment module 123, three end input nand gate NAND0, three end input nand gate NAND1, the output terminal of three end input nand gate NAND2 and two end input nand gate NAND3 is respectively by phase inverter INV10, phase inverter INV11, phase inverter INV12 and phase inverter INV13 and d type flip flop DFF10, d type flip flop DFF11, d type flip flop DFF12 is connected with the input end of clock of d type flip flop DFF13.
In embodiments of the present invention, d type flip flop DFF10, d type flip flop DFF11, d type flip flop DFF12 and d type flip flop DFF13 are used for as one of four states position assignment, after circuit powers on, be set as " 0 " by the initial value of the 2nd and the 1st mode bit Reg [1:0], the initial value of the 4th and the 3rd mode bit REG [3:2] is set as " 1 ".As Add [3:0]=0001, Add1B=1, Add2B=1, during Add3B=1, first mode bit address is effective, and d type flip flop DFF10 is triggered at the rising edge of Add_time, capture the magnitude of voltage of logic input signal now, assignment is carried out to many bit logic signal Reg0; As Add [3:0]=0011, Add1B=0, Add2B=1, Add3B=1, second mode bit address is effective, and d type flip flop DFF11 is triggered at the rising edge of Add_time, capture the magnitude of voltage of logic input signal now, assignment is carried out to many bit logic signal Reg1; As Add [3:0]=0111, Add1B=0, Add2B=0, during Add3B=1,3rd mode bit address is effective, d type flip flop DFF12 is triggered at the rising edge of Add_time, captures the inverse value of the voltage of logic input signal at that time, again anti-phasely carries out assignment to many bit logic signal Reg2 afterwards; As Add [3:0]=1111, Add1B=0, Add2B=0, during Add3B=0, one of four states bit address is effective, d type flip flop DFF13 is triggered at the rising edge of Add_time, captures the inverse value of the voltage of logic input signal at that time, again anti-phasely carries out assignment to many bit logic signal Reg3 afterwards.
Fig. 6 illustrates the exemplary circuit structure of the unit at a slow speed that one embodiment of the invention provides, and for convenience of explanation, illustrate only part related to the present invention.
Unit 13 comprises delayer Delay1, delayer Delay2, rejection gate NOR2 and phase inverter INV2 at a slow speed, the input end of delayer Delay1 is the input end of unit 13 at a slow speed, the output terminal of delayer Delay1 is connected with the input end of delayer Delay2, an input end of the output terminal AND OR NOT gate NOR2 of delayer Delay2 connects, another input end of rejection gate NOR2 is the control end of unit 13 at a slow speed, the output terminal of rejection gate NOR2 is connected with the input end of phase inverter INV2, and the output terminal of phase inverter INV2 is the input end of unit 13 at a slow speed.
In embodiments of the present invention, as Enable=0, quick cell 12 is in dormant state, and logic input signal is directly transferred to single-bit logic and exports; Activation signal Enable is when the negative edge saltus step of logic input signal is " 1 ", quick cell 12 is activated, unit 13 dormancy at a slow speed, single-bit logical signal by locked in " 1 ", logic input signal is after delayer Delay1, delayer Delay2 postpone, the rising edge of the single-bit logical signal negative edge that order exports and activation signal Enable staggers, and the single-bit logical signal avoiding output produces pulse burr signal.
Fig. 7 illustrates the logical waveform sequential of 2 change-over periods of one line control circuit that one embodiment of the invention provides, and for convenience of explanation, illustrate only part related to the present invention.
Before the instant t 0, Enable=0, the quick cell 12 of one line control circuit is in dormant state, and unit 13 is activated at a slow speed, and single-bit logic output signal State equals logic input signal, but slightly some postpone.
After first negative edge of logic input signal arrives, through postponing slightly, in the t0 moment, Enable=1, the quick cell 12 of one line control circuit is activated, unit 13 dormancy at a slow speed, now one line control circuit entered for the first change-over period, and within this change-over period, quick cell 12 pairs of logic input signals respond, export many bit logic signal Reg [3:0], single-bit logical signal State is locked in " 1 ";
In embodiments of the present invention, from the t0 moment to the t1 moment for getting location time Tadd, this gets location time Tadd between 2ms and 3ms, get in location time Tadd at this, logic input signal has three rising edges, therefore Add [3:0]=0111, namely the 3rd mode bit address is effective, the t1 moment is assignment point, assignment module 123 now capture logic input signal and assignment give the 3rd mode bit address, make many bit logic signal Reg2=0.After assignment completes, reset signal Reset carries out saltus step, and the t2 moment after short delay makes Enable reset, i.e. Enable=0, quick cell 12 dormancy of one line control circuit, each correlation module is all reset, and mode bit keeps its assignment constant, the unit at a slow speed 13 of one line control device is activated simultaneously, exports the single-bit slightly postponed compared with logic input signal and patrols signal State.
The frequency arranging Clock is f, according to the number n of d type flip flop before Add_time, can arrange the time of minimum triggering for (n-1)/f.In embodiments of the present invention, the frequency of Clock is 1KHz, and the time of minimum triggering is 2ms, 1ms after Add_time=1, and state handover module 11 is reset.
In embodiments of the present invention, this t2 moment is switching point, and be a change-over period Twork from the t0 moment to the t2 moment, this change-over period, Twork was between 3ms and 4ms.
After the negative edge of logic input signal arrives again, after postponing slightly, in the t3 moment, the quick cell 12 of one line control circuit is activated again, Enable=1, and one line control circuit entered for the second change-over period, unit 13 dormancy at a slow speed, single-bit logical signal is locked in " 1 " simultaneously.Get in location time Tadd in this section of t3 moment to t4 moment, logic input signal only has a rising edge, therefore Add [3:0]=0001, first mode bit address is effective, the t4 moment is assignment point, assignment module 123 now capture logic input signal and assignment give first mode bit address, make many bit logic signal Reg0=1.In the t5 moment, the second change-over period terminated, quick cell 12 dormancy of one line control circuit, and unit 13 activates at a slow speed, and now logic input signal is " 0 ", single-bit patrol signal State also thereupon saltus step for " 0 ".
In the present embodiment, there is Rapid Variable Design composition in logic input, also there is varying component at a slow speed.After first negative edge, enter the change-over period that duration is Twork, the signal logic change of logic input in Twork all belongs to Rapid Variable Design, and what meeting was corresponding provides many bit logic signal; Logic input is after the change-over period terminates, and the logic state before comparing the change-over period, the logic still existed changes, and belongs to and changes at a slow speed, and what meeting was corresponding provides single-bit logical signal, until again encounter negative edge to enter the next change-over period.
Fig. 8 illustrates and the sequential of cell operation at a slow speed that one embodiment of the invention provides for convenience of explanation, illustrate only part related to the present invention.
In embodiments of the present invention, after first negative edge of logic input signal, one line control device quick cell is activated, but the time maintaining " 0 " due to logic input signal is greater than change-over period Twork, therefore one line control device get location module 122 and assignment module 123 does not all work, it is constant that the many bit logic signal Reg [3:0] exported maintains former logic state all the time, is equivalent to the conductively-closed of one line control circuit quick cell.Single-bit logical signal State saltus step after the change-over period, Twork terminated is " 0 "; When logic input saltus step is " 1 ", single-bit logical signal State is and then saltus step one-tenth " 1 " also.The whole course of work is equivalent to only has the unit at a slow speed of one line control circuit in work, and single-bit logic exports follows logic input change, and negative edge saltus step exists the delay of about Twork.
The one line control circuit that the embodiment of the present invention provides can be applied in the one line control chip of any series.
In embodiments of the present invention, by having the status toggle unit receive logic input signal of external pin, activation quick cell or at a slow speed unit, the many bit logic signal of corresponding output or single-bit logical signal control multiple mode bit or the single status position of internal circuit, realize one line control, meet the requirement of a small amount of pin package chip, simplify the peripheral applications environment of circuit, reduce packaging cost.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. an one line control circuit, is packaged in chip internal, it is characterized in that, described one line control circuit comprises:
Status toggle unit, its input end is described chip one pin, described status toggle unit judges outside logic input signal, when logic input signal is fast logic signal, described one line control circuit is switched to quick mode, corresponding exports quick active signal, when logic input signal be at a slow speed logical signal time, described one line control circuit is switched to slow speed mode, corresponding output slow active signal;
Quick cell, comprise control end, input end, clock signal terminal and feedback output end, described control end is connected with the output terminal of described status toggle unit, described input end is connected with the input end of described status toggle unit, described clock signal terminal is connected with internal circuit, described feedback output end is connected with the reset terminal of described status toggle unit, described quick cell is activated when receiving quick active signal, under the effect of clock signal, the Rapid Variable Design composition of logic input signal is responded, control multiple mode bit internally circuit export many bit logic signal, and
Unit at a slow speed, its control end is connected with the output terminal of described status toggle unit, input end is connected with the input end of described status toggle unit, described unit is at a slow speed activated when receiving slow active signal, the varying component at a slow speed of logic input signal is responded, controls single status position internally circuit output single-bit logical signal;
Described quick cell comprises:
Timing module, for according to clock signal, output gets the location time and to described status toggle unit feedback reset signal, the clock control end of described timing module is the clock signal terminal of described quick cell, the feedback signal output of described timing module is the feedback output end of described quick cell, and the reset terminal of described timing module is the control end of described quick cell;
Get location module, the location time is got for basis, export effective status bit address, the location time output terminal of getting of described location time of the getting input end and described timing module of getting location module is connected, the described input end of clock getting location module is the input end of described quick cell, described in get location module Enable Pin be the control end of described quick cell;
Assignment module, for getting under the time of location effective status bit address assignment, be many bit logic signal by the Rapid Variable Design composition conversion in logic input signal, location time of the getting input end of described assignment module is connected with the location time output terminal of getting of described timing module, the address input end of described assignment module is connected with the described address output end getting location module, the logic signal input end of described assignment module is the input end of described quick cell, and the address inverting input of described assignment module is connected with the secondary address reversed-phase output getting location module.
2. circuit as claimed in claim 1, it is characterized in that, described status toggle unit comprises:
Phase inverter INV0, d type flip flop DFF1, delayer Delay0 and diode Diode;
The input end of described phase inverter INV0 is the input end of described status toggle unit, the output terminal of described phase inverter INV0 is connected with the input end of clock of described d type flip flop DFF1, the data input pin of described d type flip flop DFF1 connects high level, the reset terminal of described d type flip flop DFF1 is the reset terminal of described status toggle unit, the data output end of described d type flip flop DFF1 is connected with the input end of described delayer Delay0, the output terminal of described delayer Delay0 is connected with the negative electrode of described diode Diode, its tie point is the output terminal of described status toggle unit, the plus earth of described diode Diode.
3. circuit as claimed in claim 1, it is characterized in that, described unit at a slow speed comprises:
Delayer Delay1, delayer Delay2, rejection gate NOR2 and phase inverter INV2;
The input end of described delayer Delay1 for described in the input end of unit at a slow speed, the output terminal of described delayer Delay1 is connected with the input end of described delayer Delay2, the output terminal of described delayer Delay2 is connected with an input end of described rejection gate NOR2, another input end of described rejection gate NOR2 for described in the control end of unit at a slow speed, the output terminal of described rejection gate NOR2 is connected with the input end of described phase inverter INV2, the output terminal of described phase inverter INV2 for described in the input end of unit at a slow speed.
4. circuit as claimed in claim 2, it is characterized in that, described timing module is counter;
The first data input pin of described counter connects high level;
The input end of clock of described counter is the clock control end of described timing module;
The reset terminal of described counter is the reset terminal of described timing module;
The last digit of described counter is the feedback signal output of described timing module according to reversed-phase output;
The secondary last digit of described counter according to output terminal be described timing module get location time output terminal.
5. circuit as claimed in claim 2, is characterized in that, described in get location module and comprise:
Counter, phase inverter INV1 and rejection gate NOR1;
The input end of described phase inverter INV1 for described in get location module get location time input end, the output terminal of described phase inverter INV1 is connected with an input end of described rejection gate NOR1, another input end of described rejection gate NOR1 for described in get location module get location time input end, the output terminal of described rejection gate NOR1 is connected with the reset terminal of described counter, the first data input pin of described counter connects high level, the input end of clock of described counter for described in get the input end of clock of location module, every data output end of described counter for described in get the address output end of location module, the first data inversion output terminal of counter is unsettled, secondary bit data reversed-phase output OPADD reverse signal.
6. circuit as claimed in claim 2, it is characterized in that, described assignment module comprises:
D type flip flop DFF10, d type flip flop DFF11, d type flip flop DFF12, d type flip flop DFF13, phase inverter INV10, phase inverter INV11, phase inverter INV12, phase inverter INV13, phase inverter INV14, three end input nand gate NAND0, three end input nand gate NAND1, three end input nand gate NAND2 and two end input nand gate NAND4;
The data input pin of described d type flip flop DFF10 and d type flip flop DFF11 is the logic signal input end of described assignment module, described d type flip flop DFF12 is connected with the data input pin of described d type flip flop DFF13 and is connected with the output terminal of described phase inverter INV14 simultaneously, the input end of described phase inverter INV14 is the logic signal input end of described assignment module, described d type flip flop DFF10, d type flip flop DFF11, d type flip flop DFF12 is all connected high level with the reset terminal stating d type flip flop DFF13, the data output end of described d type flip flop DFF10 and d type flip flop DFF11 is respectively the logical signal output terminal of described assignment module, internally circuit exports many bit logic signal Reg0, Reg1, the data back output terminal of described d type flip flop DFF12 and d type flip flop DFF13 is respectively the logical signal output terminal of described assignment module, internally circuit exports many bit logic signal Reg2, Reg3, described three end input nand gate NAND0, three end input nand gate NAND1, two input ends of three end input nand gate NAND2 and two end input nand gate NAND4 are address input end and the described location time input end of getting of described assignment module respectively, described three end input nand gate NAND0, an other input end of three end input nand gate NAND1 and three end input nand gate NAND2 is the anti-phase address input end of described assignment module, described three end input nand gate NAND0, three end input nand gate NAND1, the output terminal of three end input nand gate NAND2 and two end input nand gate NAND3 is respectively by described phase inverter INV10, phase inverter INV11, phase inverter INV12 and phase inverter INV13 and described d type flip flop DFF10, d type flip flop DFF11, d type flip flop DFF12 is connected with the input end of clock of d type flip flop DFF13.
7. adopt a chip for one line control circuit, it is characterized in that, the one line control circuit of described chip is the one line control circuit described in any one of claim 1 to 6.
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| CN201110073454.8A CN102692879B (en) | 2011-03-25 | 2011-03-25 | A kind of one line control circuit and chip |
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| CN111221760A (en) * | 2018-11-23 | 2020-06-02 | 珠海格力电器股份有限公司 | Communication control method and device of I2C bus and storage medium |
| CN115459565B (en) * | 2022-11-10 | 2023-03-10 | 成都智融微电子有限公司 | State switching control device |
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| JPS62224848A (en) * | 1986-03-26 | 1987-10-02 | Nec Corp | Logic circuit switching circuit |
| CN2816925Y (en) * | 2005-03-22 | 2006-09-13 | 赖嘉德实业有限公司 | General bus detecting module |
| CN101848033A (en) * | 2010-04-28 | 2010-09-29 | 成都优博创技术有限公司 | Dual-rate receiving device |
| WO2010150303A1 (en) * | 2009-06-22 | 2010-12-29 | 株式会社アドバンテスト | Timing generator and tester |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS62224848A (en) * | 1986-03-26 | 1987-10-02 | Nec Corp | Logic circuit switching circuit |
| CN2816925Y (en) * | 2005-03-22 | 2006-09-13 | 赖嘉德实业有限公司 | General bus detecting module |
| WO2010150303A1 (en) * | 2009-06-22 | 2010-12-29 | 株式会社アドバンテスト | Timing generator and tester |
| CN101848033A (en) * | 2010-04-28 | 2010-09-29 | 成都优博创技术有限公司 | Dual-rate receiving device |
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