CN102683368B - Complementary metal oxide semiconductor (CMOS) imaging sensor and producing method thereof - Google Patents
Complementary metal oxide semiconductor (CMOS) imaging sensor and producing method thereof Download PDFInfo
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Abstract
The invention relates to a CMOS imaging sensor and a producing method thereof. The CMOS imaging sensor comprises a semiconductor substrate. The semiconductor substrate comprises a first active region and a second active region, wherein the first active region comprises a photodiode and a transistor, the second active region is close to a trap of the photodiode and has the same conduction type as that of the photodiode, the second active region is connected to a reference electric potential, and traps of the second active region and the photodiode are formed by one-time ion implantation.
Description
Technical field
The present invention relates to imageing sensor, and particularly relate to a kind of cmos image sensor and manufacture method thereof.
Background technology
Cmos image sensor is for CCD (Charge Coupled Device), and have integrated level high, low in energy consumption, the advantages such as cost is low, obtain and apply more and more widely.Its photosensitive unit, i.e. institute's pixel, be used to opto-electronic conversion, it plays conclusive effect for the quality of image.
Pixel is modal is 3T and 4T structure.Fig. 1 and Fig. 2 shows a kind of pixel of 4T structure.As shown in Figure 1, photodiode 11, transmission transistor 12, reset transistor 13, transistor 14 is followed in source, row gate transistor 15 is prepared in active area.Wherein, photodiode 11 is used for light signal to change into the signal of telecommunication, thus reaches photosensitive object.Specifically, photodiode 11 produces photo-generated carrier under incident light irradiates, when transmission transistor 12 is opened, electronics is collected by floating diffusion region FD, the source electrode that simultaneously transistor 14 is followed in source follows the change of grid voltage, the change of grid voltage is expert at when gate transistor 15 is opened and is read, thus produces the signal of telecommunication.Can reset to floating diffusion region FD by opening reset transistor 13.
But in existing pixel structure, when photodiode 11 is subject to strong illumination, the photo-generated carrier exceeding trap capacity can spill into adjacent pixel, result causes crosstalk or the halation of image.
For this problem, a kind of solution does lower by the potential barrier between photodiode 11 and floating diffusion region FD, makes the electronics overflowed easily be pulled to floating diffusion region FD.
But, still need other technology for alleviating or removal of images crosstalk or halation.
Summary of the invention
The problem that the method for the potential barrier between aforesaid reduction photodiode 11 and floating diffusion region FD exists is: normal light electric diode 11 and floating diffusion region FD are defined by different lithography steps, therefore, with regard to whole sensor chip surface, distance between the photodiode 11 of different pixels and floating diffusion region FD is not uniform, thus causes the effect of the horizontal anti-blooming between different pixels (lateral overflow drain) uneven.
According to an aspect of the present invention, provide a kind of cmos image sensor, comprise: semiconductor chip, comprise the first active area, wherein, described first active area comprises photodiode, transistor, and second active area, wherein, the trap of the contiguous described photodiode in described second active area, and there is the conduction type identical with the trap of described photodiode, described second active area is connected to reference potential, and wherein, the trap of described second active area and described photodiode is injected by primary ions and formed.
In one example in which, described first active area also comprises at least two horizontal doped regions, described horizontal doped region has the conduction type identical with described first active area, between the trap and described second active area of described photodiode, the width of described horizontal doped region is equal to, or greater than the width in the gap between the trap of described photodiode and described second active area.
In one example in which, described at least two horizontal doped regions cover the adjacent corners of described trap and the adjacent corners of described second active area.
In one example in which, described first active area also comprises first longitudinal doped region, described first longitudinal doped region has the conduction type identical with described first active area, is positioned at the below in described gap, covers the adjacent corners of described trap and the adjacent corners of described second active area.
In one example in which, described first active area also comprises second longitudinal doped region, described second longitudinal doped region has the conduction type identical with described first active area, is positioned at the top in described gap, covers the adjacent corners of described trap and the adjacent corners of described second active area.
In one example in which, described first active area also comprises at least one longitudinal doped region, described longitudinal doped region has the conduction type identical with described first active area, the below in the gap between the trap and described second active area of described photodiode, covers the adjacent corners of described trap and the adjacent corners of described second active area.
In one example in which, described first active area comprises two photodiodes, and described second active area is between the trap of described two photodiodes.
In one example in which, described first active area also comprises the heavily doped region being connected to described second active area, and described heavily doped region has the conduction type identical with described second active area.
According to another aspect of the present invention, a kind of method for the manufacture of cmos image sensor of the present invention is provided, comprises the following steps: form the first active area on the semiconductor substrate; Form the trap of photodiode and the second active area of contiguous described trap in described first active area simultaneously; Form described second active area to be connected with the electricity of reference potential.
In one example in which, the trap of described photodiode and the second active area are formed by ion implantation.
In one example in which, described method also comprises: in described first active area, form at least two horizontal doped regions simultaneously, wherein, described horizontal doped region has the conduction type identical with described first active area, between the trap and described second active area of described photodiode, the width of described horizontal doped region is equal to, or greater than the width in the gap between the trap of described photodiode and described second active area.
In one example in which, described method is also included in described first active area and forms first longitudinal doped region, wherein, described first longitudinal doped region has the conduction type identical with described first active area, be positioned at the below in described gap, cover the adjacent corners of described trap and the adjacent corners of described second active area.
In one example in which, described method is also included in described first active area and forms second longitudinal doped region, wherein, described second longitudinal doped region has the conduction type identical with described first active area, be positioned at the top in described gap, cover the adjacent corners of described trap and the adjacent corners of described second active area.
Accompanying drawing explanation
Embodiments of the invention can be understood better with reference to following accompanying drawing.Parts in accompanying drawing may not be drawn in proportion:
Fig. 1 is a kind of vertical view of 4T structure-pixel;
Fig. 2 is the profile along the direction shown in arrow of the 4T structure-pixel of Fig. 1;
Fig. 3 a is the pixel schematic diagram of an embodiment according to cmos image sensor of the present invention;
Fig. 3 b is a change case of the embodiment shown in Fig. 3 a;
Fig. 3 c is another change case of the embodiment shown in Fig. 3 a;
Fig. 4 a is the schematic diagram of another embodiment according to cmos image sensor of the present invention;
Fig. 4 b is a change case of the embodiment shown in Fig. 4 a;
Fig. 4 c is another change case of the embodiment shown in Fig. 4 a;
Fig. 4 d is another change case of the embodiment shown in Fig. 4 a;
Fig. 5 a is the pixel vertical view of the embodiment shown in Fig. 4 a;
Fig. 5 b is an exemplary cross sectional view of the embodiment shown in Fig. 4 a;
Fig. 5 c is another exemplary cross sectional view of the embodiment shown in Fig. 4 a;
Fig. 6 a is the pixel schematic diagram of another embodiment according to cmos image sensor of the present invention;
Fig. 6 b is an exemplary cross sectional view of the embodiment shown in Fig. 6 a;
Fig. 6 c is another exemplary cross sectional view of the embodiment shown in Fig. 6 a;
Fig. 7 a is the pixel schematic diagram of another embodiment according to cmos image sensor of the present invention;
Fig. 7 b is an exemplary cross sectional view of the embodiment shown in Fig. 7 a;
Fig. 8 a is the schematic diagram of another embodiment according to cmos image sensor of the present invention;
Fig. 8 b is the schematic diagram of another embodiment according to cmos image sensor of the present invention; And
Fig. 9 is the schematic diagram of another embodiment according to cmos image sensor of the present invention.
In above-mentioned each accompanying drawing, similar Reference numeral should be understood to represent identical, similar or corresponding feature or function.
Embodiment
In the specific descriptions of following preferred embodiment, with reference to the accompanying drawing formed appended by a part of the present invention.Appended accompanying drawing shows by way of example and can realize specific embodiment of the present invention.The embodiment of example is not intended to limit according to all embodiments of the present invention.Be appreciated that under the prerequisite not departing from scope of the present invention, other embodiments can be utilized, also can carry out amendment that is structural or logicality.Therefore, following specific descriptions are also nonrestrictive, and scope of the present invention limited by appended claim.
In following specific descriptions, with reference to appended accompanying drawing.Figures constitute a part of the present invention, show by way of example in the accompanying drawings and can implement specific embodiment of the present invention.In this regard, the term of directivity, such as "left", "right" " top ", " bottom ", "front", "rear", " guiding ", " forward ", " delaying " etc., use with reference to the direction described in accompanying drawing.Therefore the parts of embodiments of the invention can be placed in multiple different direction, and the term of directivity is nonrestrictive for the object of example.Be appreciated that under the prerequisite not departing from scope of the present invention, other embodiments can be utilized, also can carry out structural or logicality amendment.Therefore, following specific descriptions are also nonrestrictive, and scope of the present invention limited by appended claim.
According to an embodiment of cmos image sensor of the present invention, this cmos image sensor comprises semiconductor chip (such as, N-type or P-type silicon sheet), this semiconductor chip comprises the first active area (such as, extension life is at P type epitaxial loayer on the semiconductor substrate), as shown in Figure 3 a, this first active area comprises photodiode 11, transistor 12,13,14,15, and the second active area 31.
Below describe the second active area 31 in detail.
The trap (position of this trap and area are namely if label in Fig. 3 a is shown in the block schematic of 11) of the second active area 31 adjacent photodiode 11, and the second active area 31 has the conduction type identical with the trap of photodiode, that is, when the trap of photodiode is N-type, second active area 31 is also N-type, when the trap of photodiode is P type, the second active area 31 is also P type.Further, the second active area 31 is connected to reference potential V
rEF.Further, the trap of the second active area 31 and photodiode 11 is injected by primary ions and is formed.
It should be noted that, reference potential V
rEFimplication be: when the trap of photodiode is N-type, this reference potential V
rEFthe current potential higher compared to the trap of photodiode, when the trap of photodiode is P type, this reference potential V
rEFthe current potential lower compared to the trap of photodiode; Also it should be noted that, reference potential V
rEFcan be the current potential (it can pass through second active area 31 is connected to tie point realization that label be 16) identical with reset potential, reference potential V
rEFalso can be the current potential different from reset potential.
Although do not illustrate the second active area 31 and reference potential V in Fig. 3 a
rEFconnect and compose, it will be appreciated by those skilled in the art that the current potential that by through hole, metal level etc., the second active area 31 can be connected to needs, a joint area do not described in detail at this to the concrete formation of a current potential, mode.
Below illustrate as shown in Fig. 3 a, according to the advantage of the embodiment of cmos image sensor of the present invention:
The trap of the second active area 31 adjacent photodiode 11 and arrange and be connected to reference potential V
rEF, therefore when cmos image sensor is subject to strong illumination, the photo-generated carrier exceeding the trap capacity of photodiode 11 is pulled to the second active area 31, thus reduce or avoid photo-generated carrier and spill into neighbor, because the trap of the second active area 31 and photodiode 11 injects formation by primary ions, therefore with regard to whole sensor chip surface, distance D1 between second active area 31 of each pixel and the trap of photodiode 11 is identical, therefore the anti-blooming effect of each pixel is identical, thus obtain the cmos image sensor of anti-blooming uniform in effect.
Fig. 3 b is a change case of the embodiment shown in Fig. 3 a, as shown in the figure, the left side of the trap of the second active area 31 adjacent photodiode 11 and arranging, because the trap of the second active area 31 and photodiode 11 injects formation by primary ions, the distance D2 between the second active area 31 of each pixel and the trap of photodiode 11 is identical.
Fig. 3 c is another change case of the embodiment shown in Fig. 3 a, as shown in the figure, the right side of the trap of the second active area 31 adjacent photodiode 11 and arranging, because the trap of the second active area 31 and photodiode 11 injects formation by primary ions, the distance D3 between the second active area 31 of each pixel and the trap of photodiode 11 is identical.
It should be noted that, any applicable distance and bearing can be arranged to relative to the trap of photodiode 11 in the second active area 31.Such as, second active area 31 is nearer apart from the trap of photodiode 11, overflow charge carrier and be more easily pulled to the second active area 31, and also correspondingly increase for generation of the tendency that the photo-generated carrier of photosignal is pulled to the second active area 31, can according to the distance and bearing of adjustment second active areas 31 such as the anti-blooming needs of reality, transducer are specifically formed relative to the trap of photodiode 11.
Fig. 4 a is the schematic diagram of another embodiment according to cmos image sensor of the present invention.In this embodiment, the first active area also comprises two horizontal doped regions 41.Particularly, this horizontal doped region 41 has the conduction type identical with the first active area, and that is, when the first active area is P type, horizontal doped region 41 is also P type, and when the first active area is N-type, horizontal doped region 41 is also N-type.Further, this horizontal doped region 41 is between the trap and the second active area 31 of photodiode 11, and, the width of horizontal doped region 41 is greater than the width in the gap between the trap of photodiode 11 and the second active area 31, thus these two horizontal doped regions 41 cover the adjacent corners of this trap and the adjacent corners of the second active area 31 respectively.
Except can realizing the advantage of the embodiment of Fig. 3 a, the embodiment of Fig. 4 a can also realize following advantage:
Because these two horizontal doped regions 41 occupy the part in the outer part in the gap between the trap of photodiode 11 and the second active area 31, therefore the passage (going out as shown by arrows in FIG.) that photo-generated carrier is released from photodiode 11 to the second active area 31 has been limited, the tendency being consequently pulled to the second active area 31 for generation of the photo-generated carrier of photosignal reduces, and the charge carrier simultaneously exceeding trap capacity under intense light conditions still can be released.
In addition to the advantages described above, the embodiment of Fig. 4 a can also realize following advantage:
This two or more horizontal doped region 41 can define in a photoetching, injected or spread, thus the size of confined carrier pathway is uniform on whole sensor chip by primary ions.
In addition, because the effect of anti-blooming and this confined carrier pathway are insensitive relative to the position in the gap between the trap of photodiode 11 and the second active area 31, therefore for horizontal doped region 41 relative to the trap of photodiode 11 and the alignment precision of the second active area 31 less demanding, therefore the embodiment of Fig. 4 a is simple in technique.
Fig. 4 b is a change case of the embodiment shown in Fig. 4 a, and in this example embodiment, the width of horizontal doped region 41 equals the width in the gap between the trap of photodiode 11 and the second active area 31, still can obtain confined photo-generated carrier flow path.
Fig. 4 c is another change case of the embodiment shown in Fig. 4 a, and in this example embodiment, the width of horizontal doped region 41 equals the width in the gap between the trap of photodiode 11 and the second active area 31, still can obtain confined photo-generated carrier flow path.
Fig. 4 d is another change case of the embodiment shown in Fig. 4 a, and in this example embodiment, the first active area also comprises three horizontal doped regions 41, and the confined photo-generated carrier flow path of permission two is arranged in these three horizontal doped regions 41.
Fig. 5 a is the pixel vertical view of the embodiment shown in Fig. 4 a, Fig. 5 b is an exemplary cross sectional view along straight line 5-5 ' of the embodiment shown in Fig. 4 a, as shown in the figure, horizontal doped region 41 extends to certain degree of depth from chip surface in z-direction, such as, can be the degree of depth being substantially equal to the second active area 31.Horizontal doped region 41 can be formed by such as ion diffuse.
Fig. 5 c is another exemplary cross sectional view of the embodiment shown in Fig. 4 a, and as shown in the figure, horizontal doped region 41 extends to certain degree of depth in z-direction below chip surface, such as, can be the degree of depth being substantially equal to the second active area 31.Horizontal doped region 41 can be formed by such as ion implantation.
Fig. 6 a is the pixel schematic diagram of another embodiment according to cmos image sensor of the present invention, and in this embodiment, the first active area also comprises longitudinal doped region 61.Particularly, this longitudinal doped region 61 has the conduction type identical with the first active area, and that is, when the first active area is P type, longitudinal doped region 61 is also P type, and when the first active area is N-type, longitudinal doped region 61 is also N-type.Further, this longitudinal doped region 61 is between the trap and the second active area 31 of photodiode 11, and the width of longitudinal doped region 61 is greater than the width in the gap between the trap of photodiode 11 and the second active area 31.
Fig. 6 b is an exemplary cross sectional view of the embodiment shown in Fig. 6 a, in this formation, first active area comprises a longitudinal doped region 61, gap between the trap and the second active area 31 of photodiode 11 (in Z-direction) top, thus the flow path of photo-generated carrier is limited in the below in gap.
Fig. 6 c is another exemplary cross sectional view of the embodiment shown in Fig. 6 a, in this formation, first active area comprises two longitudinal doped regions 61, gap between the trap and the second active area 31 of photodiode 11 (in Z-direction) above and below, thus the flow path of photo-generated carrier is limited in the mid portion in gap.
Except can realizing the advantage of the embodiment of Fig. 3 a, the embodiment of Fig. 6 a can also realize following advantage:
Because these two longitudinal doped regions 61 occupy the part in the gap between the trap of photodiode 11 and the second active area 31, therefore the passage (going out as shown by arrows in FIG.) that photo-generated carrier is released from photodiode 11 to the second active area 31 has been limited, the tendency being consequently pulled to the second active area 31 for generation of the photo-generated carrier of photosignal reduces, and the charge carrier simultaneously exceeding trap capacity under intense light conditions still can be released.
In addition to the advantages described above, the embodiment of Fig. 6 c can also realize following advantage:
Can by controlling the energy of ion implantation thus controlling this two or more longitudinal doped region 61 distance in z-direction, thus the size of confined carrier pathway is uniform on whole sensor chip, thus anti-blooming effect is uniform on sensor chip, therefore the embodiment of Fig. 6 a-c is simple in technique.
Fig. 7 a is the pixel schematic diagram of another embodiment according to cmos image sensor of the present invention, in this example embodiment, first active area comprises two horizontal doped regions 41 and a longitudinal doped region 61, Fig. 7 b is the profile along curve 7-7 ' of the embodiment shown in Fig. 7 a, as shown in the figure, the longitudinal gap of doped region 61 between the trap and the second active area 31 of photodiode 11 (in Z-direction) below, thus two horizontal doped regions 41 and longitudinal doped region 61 limit the flow path of photo-generated carrier jointly, as in Fig. 7 b shown by arrow.
Disclosed in preceding sections, the basis of the embodiment shown in Fig. 7 can also comprise a longitudinal doped region again, the gap between the trap and the second active area 31 of photodiode 11 (in Z-direction) top.
Fig. 8 a is the schematic diagram of another embodiment according to cmos image sensor of the present invention, as shown in the figure, two photodiodes 11,11 ' share second active area 31 as the photo-generated carrier overflow path under intense light conditions, the second active area 31 can be defined as equal respectively with the distance of two photodiodes 11,11 ' in lithography step, thus obtain identical anti-blooming effect.
Fig. 8 b is the schematic diagram of another embodiment according to cmos image sensor of the present invention, as shown in the figure, two photodiodes 11,11 ' share second active area 31 as the photo-generated carrier overflow path under intense light conditions, further, horizontal doped region 41 is also respectively arranged with between the second active area 31 and two photodiodes 11,11 '.
According to disclosing above, the basis of the embodiment of Fig. 8 b can further include longitudinal doped region 61.
Fig. 9 is the schematic diagram of another embodiment according to cmos image sensor of the present invention, first active area also comprises the heavily doped region being connected to the second active area 31, this heavily doped region has the conduction type identical with described second active area 31, thus reduces the contact resistance of the second active area 31.
According to another aspect of the present invention, a kind of method for cmos image sensor according to the present invention is provided, comprises the following steps: form the first active area on the semiconductor substrate; Form the trap of photodiode and the second active area of contiguous described trap in described first active area simultaneously; Form described second active area to be connected with the electricity of reference potential.
In one example in which, the trap of described photodiode and the second active area are formed by ion implantation.
In one example in which, described method also comprises: in described first active area, form at least two horizontal doped regions simultaneously, wherein, described horizontal doped region has the conduction type identical with described first active area, between the trap and described second active area of described photodiode, the width of described horizontal doped region is equal to, or greater than the width in the gap between the trap of described photodiode and described second active area.
In one example in which, described method is also included in described first active area and forms first longitudinal doped region, wherein, described first longitudinal doped region has the conduction type identical with described first active area, be positioned at the below in described gap, cover the adjacent corners of described trap and the adjacent corners of described second active area.
In one example in which, described method is also included in described first active area and forms second longitudinal doped region, wherein, described second longitudinal doped region has the conduction type identical with described first active area, be positioned at the top in described gap, cover the adjacent corners of described trap and the adjacent corners of described second active area.
Be appreciated that embodiment only unrestricted the present invention for description of foregoing description, it will be understood by those skilled in the art that and can modify to the present invention and be out of shape, as long as without departing from the spirit and scope of the present invention.Above-mentioned amendment and distortion are considered to the scope of the present invention and claims.Protection scope of the present invention limited by appended claim.In addition, any Reference numeral in claim should not be understood to limitation of the present invention.Verb " comprises " and its distortion is not got rid of and to be occurred in claim other element beyond statement or step.Indefinite article " one " before element or step is not got rid of and is occurred multiple such element or step.
Claims (11)
1. a cmos image sensor, comprising:
Semiconductor chip, comprises the first active area,
Wherein, described first active area comprises photodiode, transistor, and the second active area,
Wherein, the trap of the contiguous described photodiode in described second active area, and there is the conduction type identical with the trap of described photodiode, described second active area is connected to reference potential, wherein, the trap of described second active area and described photodiode is injected by primary ions and is formed, when the trap of described photodiode is N-type, described reference potential is the current potential higher compared to the trap of described photodiode, when the trap of described photodiode is P type, described reference potential is the current potential lower compared to the trap of described photodiode;
Wherein, described first active area also comprises at least two horizontal doped regions, described horizontal doped region has the conduction type identical with described first active area, between the trap and described second active area of described photodiode, the width of described horizontal doped region is equal to, or greater than the width in the gap between the trap of described photodiode and described second active area.
2. cmos image sensor as claimed in claim 1, wherein, described at least two horizontal doped regions cover the adjacent corners of described trap and the adjacent corners of described second active area.
3. cmos image sensor as claimed in claim 1, wherein, described first active area also comprises first longitudinal doped region, described first longitudinal doped region has the conduction type identical with described first active area, be positioned at the below in described gap, cover the adjacent corners of described trap and the adjacent corners of described second active area.
4. cmos image sensor as claimed in claim 3, wherein, described first active area also comprises second longitudinal doped region, described second longitudinal doped region has the conduction type identical with described first active area, be positioned at the top in described gap, cover the adjacent corners of described trap and the adjacent corners of described second active area.
5. cmos image sensor as claimed in claim 1, wherein, described first active area also comprises at least one longitudinal doped region, described longitudinal doped region has the conduction type identical with described first active area, the below in the gap between the trap and described second active area of described photodiode, covers the adjacent corners of described trap and the adjacent corners of described second active area.
6. cmos image sensor as claimed in claim 1, wherein, described first active area comprises two photodiodes, and described second active area is between the trap of described two photodiodes.
7. cmos image sensor as claimed in claim 1, described first active area also comprises the heavily doped region being connected to described second active area, and described heavily doped region has the conduction type identical with described second active area.
8., for the manufacture of a method for cmos image sensor according to claim 1, comprise the following steps:
Form the first active area on the semiconductor substrate,
Form the trap of photodiode and the second active area of contiguous described trap in described first active area simultaneously,
Form described second active area to be connected with the electricity of reference potential;
Wherein, this manufacture method also comprises:
Form at least two horizontal doped regions in described first active area simultaneously,
Wherein, described horizontal doped region has the conduction type identical with described first active area, between the trap and described second active area of described photodiode, the width of described horizontal doped region is equal to, or greater than the width in the gap between the trap of described photodiode and described second active area.
9. method as claimed in claim 8, wherein, trap and second active area of described photodiode are formed by ion implantation.
10. method as claimed in claim 8, also comprises:
First longitudinal doped region is formed in described first active area,
Wherein, described first longitudinal doped region has the conduction type identical with described first active area, is positioned at the below in described gap, covers the adjacent corners of described trap and the adjacent corners of described second active area.
11. methods as claimed in claim 10, also comprise:
Second longitudinal doped region is formed in described first active area,
Wherein, described second longitudinal doped region has the conduction type identical with described first active area, is positioned at the top in described gap, covers the adjacent corners of described trap and the adjacent corners of described second active area.
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| CN1812507A (en) * | 2005-01-14 | 2006-08-02 | 佳能株式会社 | Solid-state image pickup device and control method thereof, and camera |
| CN101800861A (en) * | 2009-02-09 | 2010-08-11 | 索尼公司 | Solid-state image pickup device and camera system |
| CN102201419A (en) * | 2010-03-26 | 2011-09-28 | 索尼公司 | Solid-state image pickup element, method of manufacturing the same and electronic apparatus |
| CN202585419U (en) * | 2012-03-20 | 2012-12-05 | 格科微电子（上海）有限公司 | Cmos image sensor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1812507A (en) * | 2005-01-14 | 2006-08-02 | 佳能株式会社 | Solid-state image pickup device and control method thereof, and camera |
| CN101800861A (en) * | 2009-02-09 | 2010-08-11 | 索尼公司 | Solid-state image pickup device and camera system |
| CN102201419A (en) * | 2010-03-26 | 2011-09-28 | 索尼公司 | Solid-state image pickup element, method of manufacturing the same and electronic apparatus |
| CN202585419U (en) * | 2012-03-20 | 2012-12-05 | 格科微电子（上海）有限公司 | Cmos image sensor |
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