CN102683368A - Complementary metal oxide semiconductor (CMOS) imaging sensor and producing method thereof - Google Patents
Complementary metal oxide semiconductor (CMOS) imaging sensor and producing method thereof Download PDFInfo
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- CN102683368A CN102683368A CN2012100748210A CN201210074821A CN102683368A CN 102683368 A CN102683368 A CN 102683368A CN 2012100748210 A CN2012100748210 A CN 2012100748210A CN 201210074821 A CN201210074821 A CN 201210074821A CN 102683368 A CN102683368 A CN 102683368A
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Abstract
The invention relates to a CMOS imaging sensor and a producing method thereof. The CMOS imaging sensor comprises a semiconductor substrate. The semiconductor substrate comprises a first active region and a second active region, wherein the first active region comprises a photodiode and a transistor, the second active region is close to a trap of the photodiode and has the same conduction type as that of the photodiode, the second active region is connected to a reference electric potential, and traps of the second active region and the photodiode are formed by one-time ion implantation.
Description
Technical field
The present invention relates to imageing sensor, and relate in particular to a kind of cmos image sensor and manufacturing approach thereof.
Background technology
Advantages such as cmos image sensor has the integrated level height for CCD (Charge Coupled Device), low in energy consumption, and cost is low have obtained application more and more widely.Its photosensitive unit, promptly institute's pixel is used for accomplishing opto-electronic conversion, and it is for the quality decisive role of image.
Pixel is modal to be 3T and 4T structure.Fig. 1 and Fig. 2 show a kind of pixel of 4T structure.As shown in Figure 1, transistor 14 is followed in photodiode 11, transmission transistor 12, reset transistor 13, source, row gate transistor 15 is prepared in the active area.Wherein, photodiode 11 is used for light signal is changed into the signal of telecommunication, thereby reaches the purpose of sensitization.Particularly; Photodiode 11 produces photo-generated carrier under the incident light irradiation; When transmission transistor 12 was opened, electronics was collected by floating diffusion region FD, and the source source electrode of following transistor 14 is followed the variation of grid voltage simultaneously; The variation of grid voltage is expert at and is read when gate transistor 15 is opened, thereby produces the signal of telecommunication.Can reset to floating diffusion region FD through opening reset transistor 13.
But in existing pixel structure, receive at photodiode 11 under the situation of strong illumination, the photo-generated carrier that exceeds the trap capacity can spill into adjacent pixels, and the result causes crosstalking or halation of image.
To this problem, a kind of solution is to do the potential barrier between photodiode 11 and the floating diffusion region FD lower, makes the electronics that overflows be pulled to floating diffusion region FD easily.
Yet, still need other technology to be used to alleviate or removal of images is crosstalked or halation.
Summary of the invention
The problem that the method for the potential barrier between aforesaid reduction photodiode 11 and the floating diffusion region FD exists is: normal light electric diode 11 is to be defined by different lithography steps with floating diffusion region FD; Therefore; With regard to the whole sensor chip surface; The photodiode 11 of different pixels and the distance between the floating diffusion region FD are not uniformly, thereby cause the effect of laterally anti-dizzy (lateral overflow drain) between the different pixels inhomogeneous.
According to an aspect of the present invention, a kind of cmos image sensor is provided, has comprised: semiconductor chip; Comprise first active area, wherein, comprise photodiode in said first active area; Transistor, and second active area, wherein; The trap of the contiguous said photodiode of said second active area, and have the conduction type identical with the trap of said photodiode, said second active area is connected to reference potential; Wherein, the trap of said second active area and said photodiode injects through primary ions and forms.
In an example; Said first active area also comprises at least two horizontal doped regions; Said horizontal doped region has and the identical conduction type of said first active area; Between the trap and said second active area of said photodiode, the width of said horizontal doped region is equal to, or greater than the trap of said photodiode and the width in the gap between said second active area.
In an example, said at least two horizontal doped regions cover the adjacent corners of said trap and the adjacent corners of said second active area.
In an example; Said first active area also comprises first vertical doped region; Said first vertical doped region has and the identical conduction type of said first active area, is positioned at the below in said gap, covers the adjacent corners of said trap and the adjacent corners of said second active area.
In an example; Said first active area also comprises second vertical doped region; Said second vertical doped region has and the identical conduction type of said first active area, is positioned at the top in said gap, covers the adjacent corners of said trap and the adjacent corners of said second active area.
In an example; Said first active area also comprises at least one vertical doped region; Said vertical doped region has and the identical conduction type of said first active area; Below the trap of said photodiode and the gap between said second active area, cover the adjacent corners of said trap and the adjacent corners of said second active area.
In an example, said first active area comprises two photodiodes, and said second active area is between the trap of said two photodiodes.
In an example, said first active area also comprises the heavily doped region that is connected to said second active area, and said heavily doped region has and the identical conduction type of said second active area.
According to another aspect of the present invention, a kind of method that is used to make cmos image sensor of the present invention is provided, may further comprise the steps: on semiconductor chip, form first active area; In said first active area, form the trap of photodiode and second active area of contiguous said trap simultaneously; Forming said second active area is connected with the electricity of reference potential.
In an example, the trap of said photodiode and second active area inject through ion and form.
In an example; Said method also comprises: in said first active area, form at least two horizontal doped regions simultaneously; Wherein, Said horizontal doped region has and the identical conduction type of said first active area, and between the trap and said second active area of said photodiode, the width of said horizontal doped region is equal to, or greater than the trap of said photodiode and the width in the gap between said second active area.
In an example; Said method also is included in and forms first vertical doped region in said first active area; Wherein, Said first vertical doped region has and the identical conduction type of said first active area, is positioned at the below in said gap, covers the adjacent corners of said trap and the adjacent corners of said second active area.
In an example; Said method also is included in and forms second vertical doped region in said first active area; Wherein, Said second vertical doped region has and the identical conduction type of said first active area, is positioned at the top in said gap, covers the adjacent corners of said trap and the adjacent corners of said second active area.
Description of drawings
Can understand embodiments of the invention better with reference to following accompanying drawing.Parts in the accompanying drawing may not be drawn in proportion:
Fig. 1 is a kind of vertical view of 4T structure-pixel;
Fig. 2 is the profile along the direction shown in the arrow of the 4T structure-pixel of Fig. 1;
Fig. 3 a is the pixel sketch map according to an embodiment of cmos image sensor of the present invention;
Fig. 3 b is the variant of the embodiment shown in Fig. 3 a;
Fig. 3 c is another variant of the embodiment shown in Fig. 3 a;
Fig. 4 a is the sketch map according to another embodiment of cmos image sensor of the present invention;
Fig. 4 b is the variant of the embodiment shown in Fig. 4 a;
Fig. 4 c is another variant of the embodiment shown in Fig. 4 a;
Fig. 4 d is another variant of the embodiment shown in Fig. 4 a;
Fig. 5 a is the pixel vertical view of the embodiment shown in Fig. 4 a;
Fig. 5 b is the exemplary cross sectional view of the embodiment shown in Fig. 4 a;
Fig. 5 c is another exemplary cross sectional view of the embodiment shown in Fig. 4 a;
Fig. 6 a is the pixel sketch map according to another embodiment of cmos image sensor of the present invention;
Fig. 6 b is the exemplary cross sectional view of the embodiment shown in Fig. 6 a;
Fig. 6 c is another exemplary cross sectional view of the embodiment shown in Fig. 6 a;
Fig. 7 a is the pixel sketch map according to another embodiment of cmos image sensor of the present invention;
Fig. 7 b is the exemplary cross sectional view of the embodiment shown in Fig. 7 a;
Fig. 8 a is the sketch map according to another embodiment of cmos image sensor of the present invention;
Fig. 8 b is the sketch map according to another embodiment of cmos image sensor of the present invention; And
Fig. 9 is the sketch map according to another embodiment of cmos image sensor of the present invention.
In each above-mentioned accompanying drawing, similar Reference numeral should be understood that to represent identical, similar or corresponding feature or function.
Embodiment
In the specific descriptions of following preferred embodiment, will be with reference to the appended accompanying drawing that constitutes the present invention's part.The mode of appended accompanying drawing through example shows and can realize certain embodiments of the present invention.The embodiment of example is not intended to limit according to all embodiment of the present invention.Be appreciated that and under the prerequisite that does not depart from scope of the present invention, can utilize other embodiment, also can carry out the modification of structural or logicality.Therefore, following specific descriptions are also nonrestrictive, and scope of the present invention is limited appended claim.
In following specific descriptions, with reference to appended accompanying drawing.Accompanying drawing has constituted a part of the present invention, in the accompanying drawings the mode through example show can embodiment of the present invention certain embodiments.In this regard, the term of directivity, for example " left side ", " right side " " top ", " bottom ", " preceding ", " back ", " guiding ", " forward ", " delaying " etc. are used with reference to the direction of describing in the accompanying drawing.Therefore the parts of embodiments of the invention can be placed in multiple different direction, and the term of directivity is to be used for the purpose of example and nonrestrictive.Be appreciated that and under the prerequisite that does not depart from scope of the present invention, can utilize other embodiment, also can carry out structural or the logicality modification.Therefore, following specific descriptions are also nonrestrictive, and scope of the present invention is limited appended claim.
An embodiment according to cmos image sensor of the present invention; This cmos image sensor comprises semiconductor chip (for example, N type or P type silicon chip), and this semiconductor chip (for example comprises first active area; The extension life is at the P type epitaxial loayer on semiconductor chip); Shown in Fig. 3 a, comprise photodiode 11, transistor 12,13,14,15 in this first active area, and second active area 31.
Below specify second active area 31.
The trap of second active area, 31 adjacent photodiode 11 (position of this trap and area are that 11 square frame schematically shows like label among Fig. 3 a promptly); And second active area 31 has the conduction type identical with the trap of photodiode; That is to say, be under the situation of N type at the trap of photodiode, and second active area 31 also is the N type; Trap at photodiode is under the situation of P type, and second active area 31 also is the P type.Further, second active area 31 is connected to reference potential V
REFAnd the trap of second active area 31 and photodiode 11 injects through primary ions and forms.
Need to prove reference potential V
REFImplication be: the trap at photodiode is under the situation of N type, this reference potential V
REFBeing than the higher current potential of the trap of photodiode, is under the situation of P type at the trap of photodiode, this reference potential V
REFBe than the lower current potential of the trap of photodiode; Also need to prove reference potential V
REFCan be the current potential identical (it can be that 16 tie point is realized through second active area 31 being connected to label) with reset potential, reference potential V
REFAlso can be and the reset potential different potential.
Though second active area 31 and reference potential V is not shown among Fig. 3 a
REFConnect and compose, it will be appreciated by those skilled in the art that and can second active area 31 be connected to the current potential that needs that the concrete formation, the mode that a zone are connected to a current potential are not done detailed description at this through through hole, metal level etc.
Below explanation shown in Fig. 3 a, according to the advantage of the embodiment of cmos image sensor of the present invention:
The trap of second active area, 31 adjacent photodiode 11 and be provided with and be connected to reference potential V
REFTherefore working as cmos image sensor receives under the situation of strong illumination; The photo-generated carrier that exceeds the trap capacity of photodiode 11 is pulled to second active area 31, has avoided photo-generated carrier to spill into neighbor thereby reduce perhaps, because the trap of second active area 31 and photodiode 11 injects formation through primary ions; Therefore with regard to the whole sensor chip surface; Distance B 1 between second active area 31 of each pixel and the trap of photodiode 11 is identical, so the anti-dizzy effect of each pixel is identical, thereby obtains the anti-dizzy uniform cmos image sensor of effect.
Fig. 3 b is the variant of the embodiment shown in Fig. 3 a; As shown in the figure; The left side of the trap of second active area, 31 adjacent photodiode 11 and being provided with; Form because the trap of second active area 31 and photodiode 11 injects through primary ions, the distance B 2 between second active area 31 of each pixel and the trap of photodiode 11 is identical.
Fig. 3 c is another variant of the embodiment shown in Fig. 3 a; As shown in the figure; The right side of the trap of second active area, 31 adjacent photodiode 11 and being provided with; Form because the trap of second active area 31 and photodiode 11 injects through primary ions, the distance B 3 between second active area 31 of each pixel and the trap of photodiode 11 is identical.
Need to prove that second active area 31 can be arranged to any suitable distance and bearing with respect to the trap of photodiode 11.For example; Second active area 31 is near more apart from the trap of photodiode 11; Overflow charge carrier and be pulled to second active area 31 more easily; And the photo-generated carrier that is used to produce photosignal is pulled to the tendency of second active area 31 and also correspondingly increases, can be according to the concrete distance and bearing that adjustment second active areas 31 such as constitutes with respect to the trap of photodiode 11 of anti-dizzy needs, the transducer of reality.
Fig. 4 a is the sketch map according to another embodiment of cmos image sensor of the present invention.In this embodiment, first active area also comprises two horizontal doped regions 41.Particularly, this horizontal doped region 41 has the conduction type identical with first active area, that is to say, and be under the situation of P type at first active area, laterally doped region 41 also is the P type, is under the situation of N type at first active area, laterally doped region 41 also is the N type.Further; This horizontal doped region 41 is between the trap and second active area 31 of photodiode 11; And; The width of horizontal doped region 41 is greater than the trap of photodiode 11 and the width in the gap between second active area 31, thereby these two horizontal doped regions 41 cover the adjacent corners of this trap and the adjacent corners of second active area 31 respectively.
Except the advantage of the embodiment that can realize Fig. 3 a, the embodiment of Fig. 4 a can also realize following advantage:
Because these two horizontal doped regions 41 have occupied the trap of photodiode 11 and the part in the outer part in the gap between second active area 31; Therefore photo-generated carrier has been limited to the passage (arrow is shown like figure) that second active area 31 is released from photodiode 11; The tendency that the photo-generated carrier that consequently is used to produce photosignal is pulled to second active area 31 has reduced, and the charge carrier that under the high light condition, exceeds the trap capacity simultaneously still can be released.
Except above-mentioned advantage, the embodiment of Fig. 4 a can also realize following advantage:
These two perhaps more laterally doped regions 41 can define in a photoetching, inject or spread through primary ions and accomplish, thereby the size of confined charge carrier passage is uniform on the whole sensor chip.
In addition; Because anti-dizzy effect and this confined charge carrier passage are insensitive with respect to the position in the trap of photodiode 11 and the gap between second active area 31; Therefore less demanding for horizontal doped region 41 with respect to the alignment precision of the trap of photodiode 11 and second active area 31, so the embodiment of Fig. 4 a is simple on technology.
Fig. 4 b is the variant of the embodiment shown in Fig. 4 a, and in this example, laterally the width of doped region 41 equals the trap of photodiode 11 and the width in the gap between second active area 31, still can access confined photo-generated carrier flow path.
Fig. 4 c is another variant of the embodiment shown in Fig. 4 a, and in this example, laterally the width of doped region 41 equals the trap of photodiode 11 and the width in the gap between second active area 31, still can access confined photo-generated carrier flow path.
Fig. 4 d is another variant of the embodiment shown in Fig. 4 a, and in this example, first active area also comprises three horizontal doped regions 41, and these three horizontal doped regions 41 are arranged to allow two confined photo-generated carrier flow paths.
Fig. 5 a is the pixel vertical view of the embodiment shown in Fig. 4 a; Fig. 5 b is the exemplary cross sectional view along straight line 5-5 ' of the embodiment shown in Fig. 4 a; As shown in the figure; Laterally doped region 41 extends to certain degree of depth from chip surface on the Z direction, for example, can be the degree of depth that is substantially equal to second active area 31.Laterally doped region 41 can form through for example ions diffusion.
Fig. 5 c is another exemplary cross sectional view of the embodiment shown in Fig. 4 a, and is as shown in the figure, and laterally doped region 41 from extending to certain degree of depth below the chip surface, for example, can be the degree of depth that is substantially equal to second active area 31 on the Z direction.Laterally doped region 41 can inject through for example ion and form.
Fig. 6 a is the pixel sketch map according to another embodiment of cmos image sensor of the present invention, and in this embodiment, first active area also comprises vertical doped region 61.Particularly, this vertical doped region 61 has the conduction type identical with first active area, that is to say, and be under the situation of P type at first active area, vertically doped region 61 also is the P type, is under the situation of N type at first active area, vertically doped region 61 also is the N type.Further, this vertical doped region 61 is between the trap and second active area 31 of photodiode 11, and vertically the width of doped region 61 is greater than the trap of photodiode 11 and the width in the gap between second active area 31.
Fig. 6 b is the exemplary cross sectional view of the embodiment shown in Fig. 6 a; In this constitutes; First active area comprises a vertical doped region 61; (on the Z direction) top in the trap of photodiode 11 and the gap between second active area 31, thus with the flow path restrictions of photo-generated carrier below the gap.
Fig. 6 c is another exemplary cross sectional view of the embodiment shown in Fig. 6 a; In this constitutes; First active area comprises two vertical doped regions 61; (on the Z direction) above and below in the trap of photodiode 11 and the gap between second active area 31, thereby with the flow path restrictions of the photo-generated carrier mid portion in the gap.
Except the advantage of the embodiment that can realize Fig. 3 a, the embodiment of Fig. 6 a can also realize following advantage:
Because these two vertical doped regions 61 have occupied the trap of photodiode 11 and the part in the gap between second active area 31; Therefore photo-generated carrier has been limited to the passage (arrow is shown like figure) that second active area 31 is released from photodiode 11; The tendency that the photo-generated carrier that consequently is used to produce photosignal is pulled to second active area 31 has reduced, and the charge carrier that under the high light condition, exceeds the trap capacity simultaneously still can be released.
Except above-mentioned advantage, the embodiment of Fig. 6 c can also realize following advantage:
Thereby can control these two or the more vertically distance of doped region 61 on the Z direction through the energy that the control ion injects; Thereby the size of confined charge carrier passage is uniform on the whole sensor chip; Thereby anti-dizzy effect is uniformly on sensor chip, so the embodiment of Fig. 6 a-c is simple on technology.
Fig. 7 a is the pixel sketch map according to another embodiment of cmos image sensor of the present invention; In this example; First active area comprises two horizontal doped regions 41 and a vertical doped region 61; Fig. 7 b is the profile along curve 7-7 ' of the embodiment shown in Fig. 7 a, and is as shown in the figure, and vertically doped region 61 is in (on the Z direction) below in the trap of photodiode 11 and the gap between second active area 31; Thereby two horizontal doped regions 41 and vertical doped region 61 have limited the flow path of photo-generated carrier jointly, and be shown like arrow among Fig. 7 b.
Disclosed like aforementioned part, on the basis of the embodiment shown in Fig. 7, can also comprise a vertical doped region again, (on the Z direction) top in the trap of photodiode 11 and the gap between second active area 31.
Fig. 8 a is the sketch map according to another embodiment of cmos image sensor of the present invention; As shown in the figure; Two photodiodes 11,11 ' are shared one second active area 31 as the photo-generated carrier overflow path under the high light condition; Can in lithography step, be defined as second active area 31 and two photodiodes 11,11 ' distance equates respectively, thereby obtain identical anti-dizzy effect.
Fig. 8 b is the sketch map according to another embodiment of cmos image sensor of the present invention; As shown in the figure; Two photodiodes 11,11 ' are shared one second active area 31 as the photo-generated carrier overflow path under the high light condition; Further, second active area 31 and two photodiodes 11, also be respectively arranged with horizontal doped region 41 between 11 '.
According to disclosing of preamble, can further include vertical doped region 61 on the basis of the embodiment of Fig. 8 b.
Fig. 9 is the sketch map according to another embodiment of cmos image sensor of the present invention; First active area also comprises the heavily doped region that is connected to second active area 31; This heavily doped region has and the identical conduction type of said second active area 31, thereby reduces the contact resistance of second active area 31.
According to another aspect of the present invention, a kind of method that is used for according to cmos image sensor of the present invention is provided, may further comprise the steps: on semiconductor chip, form first active area; In said first active area, form the trap of photodiode and second active area of contiguous said trap simultaneously; Forming said second active area is connected with the electricity of reference potential.
In an example, the trap of said photodiode and second active area inject through ion and form.
In an example; Said method also comprises: in said first active area, form at least two horizontal doped regions simultaneously; Wherein, Said horizontal doped region has and the identical conduction type of said first active area, and between the trap and said second active area of said photodiode, the width of said horizontal doped region is equal to, or greater than the trap of said photodiode and the width in the gap between said second active area.
In an example; Said method also is included in and forms first vertical doped region in said first active area; Wherein, Said first vertical doped region has and the identical conduction type of said first active area, is positioned at the below in said gap, covers the adjacent corners of said trap and the adjacent corners of said second active area.
In an example; Said method also is included in and forms second vertical doped region in said first active area; Wherein, Said second vertical doped region has and the identical conduction type of said first active area, is positioned at the top in said gap, covers the adjacent corners of said trap and the adjacent corners of said second active area.
The embodiment that is appreciated that foregoing description only is used for describing and unrestricted the present invention, it will be understood by those skilled in the art that to make amendment and be out of shape the present invention, as long as without departing from the spirit and scope of the present invention.Above-mentioned modification and distortion are considered to the scope of the present invention and accompanying claims.Protection scope of the present invention is limited appended claim.In addition, any Reference numeral in the claim should not be understood that limitation of the present invention.Verb " comprises " and element or the step that other beyond the statement in the claim occur do not got rid of in its distortion.Indefinite article " " before element or step is not got rid of and a plurality of such elements or step are occurred.
Claims (13)
1. cmos image sensor comprises:
Semiconductor chip comprises first active area,
Wherein, comprise photodiode in said first active area, transistor, and second active area,
Wherein, The trap of the contiguous said photodiode of said second active area, and have the conduction type identical with the trap of said photodiode, said second active area is connected to reference potential; Wherein, the trap of said second active area and said photodiode injects through primary ions and forms.
2. cmos image sensor as claimed in claim 1; Wherein, Said first active area also comprises at least two horizontal doped regions; Said horizontal doped region has and the identical conduction type of said first active area, and between the trap and said second active area of said photodiode, the width of said horizontal doped region is equal to, or greater than the trap of said photodiode and the width in the gap between said second active area.
3. cmos image sensor as claimed in claim 2, wherein, said at least two horizontal doped regions cover the adjacent corners of said trap and the adjacent corners of said second active area.
4. cmos image sensor as claimed in claim 2; Wherein, Said first active area also comprises first vertical doped region; Said first vertical doped region has and the identical conduction type of said first active area, is positioned at the below in said gap, covers the adjacent corners of said trap and the adjacent corners of said second active area.
5. cmos image sensor as claimed in claim 4; Wherein, Said first active area also comprises second vertical doped region; Said second vertical doped region has and the identical conduction type of said first active area, is positioned at the top in said gap, covers the adjacent corners of said trap and the adjacent corners of said second active area.
6. cmos image sensor as claimed in claim 1; Wherein, Said first active area also comprises at least one vertical doped region; Said vertical doped region has and the identical conduction type of said first active area, below the trap of said photodiode and the gap between said second active area, covers the adjacent corners of said trap and the adjacent corners of said second active area.
7. cmos image sensor as claimed in claim 1, wherein, said first active area comprises two photodiodes, said second active area is between the trap of said two photodiodes.
8. cmos image sensor as claimed in claim 1, said first active area also comprises the heavily doped region that is connected to said second active area, said heavily doped region has and the identical conduction type of said second active area.
9. method that is used to make the described cmos image sensor of claim 1 may further comprise the steps:
On semiconductor chip, form first active area,
In said first active area, form the trap of photodiode and second active area of contiguous said trap simultaneously,
Forming said second active area is connected with the electricity of reference potential.
10. method as claimed in claim 9, wherein, the trap of said photodiode and second active area inject through ion and form.
11. method as claimed in claim 9 also comprises:
In said first active area, form at least two horizontal doped regions simultaneously,
Wherein, Said horizontal doped region has and the identical conduction type of said first active area; Between the trap and said second active area of said photodiode, the width of said horizontal doped region is equal to, or greater than the trap of said photodiode and the width in the gap between said second active area.
12. method as claimed in claim 11 also comprises:
In said first active area, form first vertical doped region,
Wherein, said first vertical doped region has and the identical conduction type of said first active area, is positioned at the below in said gap, covers the adjacent corners of said trap and the adjacent corners of said second active area.
13. method as claimed in claim 12 also comprises:
In said first active area, form second vertical doped region,
Wherein, said second vertical doped region has and the identical conduction type of said first active area, is positioned at the top in said gap, covers the adjacent corners of said trap and the adjacent corners of said second active area.
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| CN1812507A (en) * | 2005-01-14 | 2006-08-02 | 佳能株式会社 | Solid-state image pickup device and control method thereof, and camera |
| CN101800861A (en) * | 2009-02-09 | 2010-08-11 | 索尼公司 | Solid-state image pickup device and camera system |
| CN102201419A (en) * | 2010-03-26 | 2011-09-28 | 索尼公司 | Solid-state image pickup element, method of manufacturing the same and electronic apparatus |
| CN202585419U (en) * | 2012-03-20 | 2012-12-05 | 格科微电子（上海）有限公司 | Cmos image sensor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1812507A (en) * | 2005-01-14 | 2006-08-02 | 佳能株式会社 | Solid-state image pickup device and control method thereof, and camera |
| CN101800861A (en) * | 2009-02-09 | 2010-08-11 | 索尼公司 | Solid-state image pickup device and camera system |
| CN102201419A (en) * | 2010-03-26 | 2011-09-28 | 索尼公司 | Solid-state image pickup element, method of manufacturing the same and electronic apparatus |
| CN202585419U (en) * | 2012-03-20 | 2012-12-05 | 格科微电子（上海）有限公司 | Cmos image sensor |
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