CN102683284A - Method for forming double-stress layer - Google Patents
Method for forming double-stress layer Download PDFInfo
- Publication number
- CN102683284A CN102683284A CN2012101359972A CN201210135997A CN102683284A CN 102683284 A CN102683284 A CN 102683284A CN 2012101359972 A CN2012101359972 A CN 2012101359972A CN 201210135997 A CN201210135997 A CN 201210135997A CN 102683284 A CN102683284 A CN 102683284A
- Authority
- CN
- China
- Prior art keywords
- stress layer
- high pressure
- photoresistance
- pressure stress
- stressed layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Drying Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to the manufacture field of semiconductors, in particular to a method for forming a double-stress layer. The method includes first removing a high pressure stress portion above an N-channel metal oxide semiconductor (NMOS) area by dry etching and then adopting the far-end plasma chemical etching process to remove a high pressure stress layer on the remained NMOS. Due to the fact that the far-end plasma chemical etching process can be used for etching the lateral face of high pressure stress silicon nitride, and etching quantity of the lateral face of the high pressure stress silicon nitride can be controlled by controlling etching time, production of an overlapping area of a high pulling stress layer and a high pressure stress layer can be avoided.
Description
Technical field
The present invention relates to the manufacturing field of semiconductor integrated circuit, relate in particular to a kind of method that forms dual stressed layers.
Background technology
In the semiconductor integrated circuit manufacturing process, strained silicon technology (Strain silicon) integrated technique is used in 45 nanometer nodes on a large scale.Strained silicon technology (Strain silicon) is meant and is forming the stressor layers that can on substrate, produce stress on the doped region; The application of this stressor layers can increase mobility of charge carrier rate in the source-drain electrode; Wherein, The mobility in hole can be improved along the compression of channel direction, and the mobility of electronics can be improved along the tension stress of channel direction.For the carrier mobility in the raceway groove is had tangible improvement; The material layer of this introducing stress is formed at the surface near raceway groove usually; Realize lifting as on cmos device, directly forming silicon nitride etch barrier layer to the carrier mobility in the raceway groove with stress; Concrete forms tension stress SiN layer in the N of NMOS type channel surface, forms compression SiN layer in the P of PMOS type channel surface.
Yet in the technology on traditional two stress silicon nitrides barrier layer, the processing of the overlapping region of different stress SiN films is difficult points, and is easy to cause because of this overlapping region the loss of yield.
Fig. 1-5 is the process structure sketch map on traditional double stress silicon nitride barrier layer in the background technology of the present invention; Shown in Fig. 1-5; At first; Deposit high tensile stress (high tensile) silicon nitride (SiN) layer 11 on the semiconductor structure 1 in N/PMOS zone having, exposure, the back of developing form and cover the photoresistance 12 on the nmos area territory, and be that the mask etching removal covers high tensile stress silicon nitride layer on the PMOS zone with photoresistance 12; After removing photoresistance 12, form and only cover the residue high tensile stress silicon nitride layer 111 on the nmos area territory.Then; Deposit high pressure stress (high compressive) silicon nitride layer 13 covers the upper surface in residue high tensile stress silicon nitride layer 111 and the PMOS zone that exposes; Exposure, the back of developing form and cover the photoresistance 14 on the PMOS zone; And be that mask etching is removed and to be covered high pressure stress silicon nitride layer on the nmos area territory with photoresistance 14, remove photoresistance 14 after, form and only cover the residual high pressure stressed silicon nitride layers 131 on the PMOS zone; And form irregular defective, thereby cause the reduction of product yield at overlapping region 15 places of residue high tensile stress silicon nitride layer 111 and residual high pressure stressed silicon nitride layers 131.
At present for the problem of overlapping region 15, the mainly adjustment through dry etch process or in the time of layout design, consider reducing influence as far as possible to yield, but all increased the difficulty of technology controlling and process, be prone to produce defective workmanship.Therefore be badly in need of finding a kind of and the traditional handicraft compatibility, and do not produce the process of defective workmanship.
Summary of the invention
The invention discloses a kind of method that forms dual stressed layers, wherein, may further comprise the steps:
Step S1: deposition high tensile stress layer covering one has the upper surface of the semiconductor structure in NMOS and PMOS zone;
Step S2: after etching was removed and covered the high tensile stress layer on the PMOS zone, deposition high pressure stress layer covered the upper surface of residue high tensile stress layer and said semiconductor structure expose portion;
Step S3: adopt photoetching process; Formation covers second photoresistance on the PMOS zone; And be after mask etching is removed part and covered the high pressure stress layer on the nmos area territory with said second photoresistance; Continue to adopt remote plasma chemical etching technology to remove to cover the high pressure stress layer in the remaining high pressure stress layer and overlapping region on the nmos area territory, remove second photoresistance.
The method of above-mentioned formation dual stressed layers; Wherein, Also comprise: step S2 adopts photoetching process to form and covers first photoresistance on the nmos area territory, and is that mask etching is removed and covered the high tensile stress layer on the PMOS zone with said first photoresistance, and removes first photoresistance.
The method of above-mentioned formation dual stressed layers wherein, adopts dry etching to remove and covers the high tensile stress layer on the PMOS zone among the step S2.
The method of above-mentioned formation dual stressed layers wherein, adopts dry etching to remove part and covers the high pressure stress layer on the nmos area territory among the step S3.
The method of above-mentioned formation dual stressed layers, wherein, the material of said high pressure stress layer and said high tensile stress layer is silicon nitride.
The method of above-mentioned formation dual stressed layers wherein, adopts NH
3, H
2, NF
3Carry out remote plasma chemical etching technology Deng gas.
The method of above-mentioned formation dual stressed layers wherein, when carrying out remote plasma chemical etching technology, is controlled the high pressure stress silicon nitride layer in the overlapping region through the control etch period.
The method of above-mentioned formation dual stressed layers, wherein, said photoetching process comprises the spin coating photoresist, after exposure, the development, removes unnecessary photoresist, forms photoresistance.
The method of above-mentioned formation dual stressed layers, wherein, said overlapping region is the overlapping part of high tensile stress layer and high pressure stress layer.
The method of above-mentioned formation dual stressed layers, wherein, said semiconductor structure comprises the substrate that is provided with NMOS and PMOS zone, and is provided with side wall and grid structure on said NMOS and the PMOS zone, in the said substrate of a shallow ditch non-intercommunicating cells embedded part.
In sum; Owing to adopted technique scheme; The present invention proposes a kind of method that forms dual stressed layers; After earlier the high pressure stress of top, nmos area territory partly being removed through dry etching, adopt the remote plasma chemical etching technology to remove the high pressure stress layer on the residue NMOS then, because the remote plasma chemical etching process can carry out etching to the side of high pressure stress silicon nitride; And control the etch quantity of high pressure stress silicon nitride side through the control etching period, and then avoid the generation of high tensile stress layer and high pressure stress layer overlapping region.
Description of drawings
Fig. 1-5 is the process structure sketch map on traditional double stress silicon nitride barrier layer in the background technology of the present invention;
Fig. 6-the 13rd, the present invention form the process structure sketch map of the method for dual stressed layers;
Figure 14 is the process chart that the present invention forms the method for dual stressed layers.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
Fig. 6-the 13rd, the present invention form the process structure sketch map of the method for dual stressed layers, and Figure 14 is the process chart that the present invention forms the method for dual stressed layers; Shown in Fig. 6-14, a kind of method (A method to formulate the dual stress layer) that forms dual stressed layers may further comprise the steps:
At first, deposition high tensile stress layer (High Tensile) 24 on semiconductor structure 2 with NMOS and PMOS zone, this high tensile stress layer 24 covers the upper surface of semiconductor structure 2; Wherein, Semiconductor structure 2 comprises the substrate 20 that is provided with PMOS and nmos area territory; Shallow ditch non-intercommunicating cells 23 is between PMOS and nmos area territory in the embedded part substrate 20; To isolate PMOS and nmos area territory, be provided with side wall 21 and grid 22 on PMOS and the nmos area territory, high tensile stress layer 24 covers the upper surface of the substrate 20 of side wall 21, grid 22, shallow ditch non-intercommunicating cells 23 and exposure.
Secondly, the spin coating photoresist covers the upper surface of high tensile stress layer 24, after exposure, the development; Removing the residue photoresist, form and cover first photoresistance 25 on the nmos area territory, is mask with this first photoresistance 25; Adopt dry etching (dry etch) technology; Etching is removed first photoresistance 25 after removing and covering the high tensile stress layer on the PMOS zone, forms and covers the residue high tensile stress layer 241 on the nmos area territory.
Afterwards, deposition high pressure stress layer (high compressive) 26 is to cover the upper surface of residue high tensile stress layer 241 and the semiconductor structure 2 that exposes; Spin coating photoresist (photo), the upper surface of covering high pressure stress layer 26 is after exposure, the development; Remove unnecessary photoresist; Form to cover second photoresistance 27 in PMOS zone, and be mask, adopt dry etch process with second photoresistance 27; After partial etching is removed and covered the high pressure stress layer on the nmos area territory, continue to adopt NH
3, H
2, NF
3Carry out remote plasma chemical etching technology 29 Deng gas, cover the high pressure stress layer 261 on the nmos area territory, remove second photoresistance, 27 continued subsequent techniques to remove residue; Because; Carry out remote plasma chemical etching technology (Siconi etch) and can carry out etching to the side of high pressure stress layer at 28 o'clock; And can effectively remove the high pressure stress layer in the overlapping region 28 of high tensile stress layer and high pressure stress layer, thereby, this technology can effectively avoid the appearance of overlapping region 28 on finishing dual stressed layers (dual stress layer) 30 that the back prepares through the control etch period.
Wherein, the material of high tensile stress layer 24 and high pressure stress layer 26 is silicon nitride (SiN).
In sum; Owing to adopted technique scheme, the present invention to propose a kind of method that forms dual stressed layers, after earlier the high pressure stress of top, nmos area territory partly being removed through dry etching; Adopt the remote plasma chemical etching technology to remove the high pressure stress layer on the residue NMOS then; Because the remote plasma chemical etching process can carry out etching to the side of high pressure stress silicon nitride, and control the etch quantity of high pressure stress silicon nitride side, avoid the generation of high tensile stress layer and high pressure stress layer overlapping region (random defect) through the control etching period; And then the yield of increase product; And owing to what adopt all is existing process means, thereby can under the situation that does not produce defective workmanship, realize with traditional handicraft double.
Through explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, read above-mentioned explanation after, various variations and revise undoubtedly will be obvious.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents all should be thought still to belong in the intent of the present invention and the scope in claims scope.
Claims (10)
1. a method that forms dual stressed layers is characterized in that, may further comprise the steps:
Step S1: deposition high tensile stress layer covering one has the upper surface of the semiconductor structure in NMOS and PMOS zone;
Step S2: after etching was removed and covered the high tensile stress layer on the PMOS zone, deposition high pressure stress layer covered the upper surface of residue high tensile stress layer and said semiconductor structure expose portion;
Step S3: adopt photoetching process; Formation covers second photoresistance on the PMOS zone; And be after mask etching is removed part and covered the high pressure stress layer on the nmos area territory with said second photoresistance; Continue to adopt remote plasma chemical etching technology to remove to cover the high pressure stress layer in the remaining high pressure stress layer and overlapping region on the nmos area territory, remove second photoresistance.
2. the method for formation dual stressed layers according to claim 1; It is characterized in that; Also comprise: step S2 adopts photoetching process to form and covers first photoresistance on the nmos area territory; And be that mask etching is removed and to be covered the high tensile stress layer on the PMOS zone, and remove first photoresistance with said first photoresistance.
3. the method for formation dual stressed layers according to claim 2 is characterized in that, adopts dry etching to remove among the step S2 and covers the high tensile stress layer on the PMOS zone.
4. the method for formation dual stressed layers according to claim 3 is characterized in that, adopts dry etching to remove part among the step S3 and covers the high pressure stress layer on the nmos area territory.
5. the method for formation dual stressed layers according to claim 4 is characterized in that, the material of said high pressure stress layer and said high tensile stress layer is silicon nitride.
6. according to the method for any described formation dual stressed layers among the claim 1-5, it is characterized in that, adopt NH
3, H
2, NF
3Gas carries out remote plasma chemical etching technology.
7. the method for formation dual stressed layers according to claim 6 is characterized in that, when carrying out remote plasma chemical etching technology, controls the high pressure stress silicon nitride layer in the overlapping region through the control etch period.
8. the method for formation dual stressed layers according to claim 7 is characterized in that, said photoetching process comprises the spin coating photoresist, after exposure, the development, removes unnecessary photoresist, forms photoresistance.
9. the method for formation dual stressed layers according to claim 8 is characterized in that, said overlapping region is the overlapping part of high tensile stress layer and high pressure stress layer.
10. the method for formation dual stressed layers according to claim 9; It is characterized in that; Said semiconductor structure comprises the substrate that is provided with NMOS and PMOS zone, and is provided with side wall and grid structure on said NMOS and the PMOS zone, in the said substrate of a shallow ditch non-intercommunicating cells embedded part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101359972A CN102683284A (en) | 2012-05-04 | 2012-05-04 | Method for forming double-stress layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101359972A CN102683284A (en) | 2012-05-04 | 2012-05-04 | Method for forming double-stress layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102683284A true CN102683284A (en) | 2012-09-19 |
Family
ID=46814995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012101359972A Pending CN102683284A (en) | 2012-05-04 | 2012-05-04 | Method for forming double-stress layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102683284A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103855024A (en) * | 2012-12-05 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor, CMOS transistor and manufacturing method of NMOS transistor and CMOS transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330053A (en) * | 2007-06-18 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming stress layer of complementary metal oxide semiconductor device |
| CN101330054A (en) * | 2007-06-18 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming passivation layer of CMOS device |
| CN101425458A (en) * | 2007-10-22 | 2009-05-06 | 应用材料股份有限公司 | Methods and systems for forming at least one dielectric layer |
| US20100065919A1 (en) * | 2006-09-28 | 2010-03-18 | Seo-Woo Nam | Semiconductor Devices Including Multiple Stress Films in Interface Area |
-
2012
- 2012-05-04 CN CN2012101359972A patent/CN102683284A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100065919A1 (en) * | 2006-09-28 | 2010-03-18 | Seo-Woo Nam | Semiconductor Devices Including Multiple Stress Films in Interface Area |
| CN101330053A (en) * | 2007-06-18 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming stress layer of complementary metal oxide semiconductor device |
| CN101330054A (en) * | 2007-06-18 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming passivation layer of CMOS device |
| CN101425458A (en) * | 2007-10-22 | 2009-05-06 | 应用材料股份有限公司 | Methods and systems for forming at least one dielectric layer |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103855024A (en) * | 2012-12-05 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor, CMOS transistor and manufacturing method of NMOS transistor and CMOS transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100855977B1 (en) | Semiconductor device and methods for manufacturing the same | |
| CN105374874B (en) | For the structures and methods of FinFET | |
| CN102024761A (en) | Method for forming semiconductor integrated circuit device | |
| TW200633127A (en) | A novel process to improve programming of memory cells | |
| US20120132996A1 (en) | Strained silicon structure | |
| US20120021583A1 (en) | Semiconductor process | |
| CN104183473B (en) | The forming method and semiconductor devices of metal gate transistor | |
| CN104517901B (en) | The forming method of CMOS transistor | |
| KR100972900B1 (en) | Semicoductor device and method of fabricating the same | |
| CN108428709A (en) | Imaging sensor and its manufacture and control method | |
| TW200818496A (en) | Semiconductor device and manufacturing method thereof | |
| CN102369598B (en) | Reduced topography-related irregularities during the patterning of two different stress-inducing layers in the contact level of a semiconductor device | |
| TWI619170B (en) | Semiconductor device and method for manufacturing the same | |
| CN102655081B (en) | A kind of shallow junction of amorphous carbon sacrificial gate electrode structure and the preparation method of side wall | |
| KR20110081942A (en) | A transistor with embedded si/ge material having enhanced across-substrate uniformity | |
| CN102683284A (en) | Method for forming double-stress layer | |
| CN102683285A (en) | Method for forming dual stress layer | |
| CN102446857B (en) | Silicide mask etching method for enhancing performances of semiconductor device | |
| CN103545257A (en) | Production method of Complementary Metal-Oxide-Semiconductor (CMOS) transistor | |
| CN104362096A (en) | SiGe source-drain MOS (metal oxide semiconductor) device production method | |
| CN104637881A (en) | Method for forming shallow trench isolation structure | |
| CN103187269A (en) | Forming method of transistor | |
| CN102054686B (en) | Method for forming stress membrane of complementary metal-oxide-semiconductor transistor (CMOS) device | |
| CN103378151B (en) | A kind of silicon germanium structure reducing load effect and forming method thereof | |
| CN102891112B (en) | Improve method and the dual gate CMOS of dual gate CMOS depletion of polysilicon |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120919 |