CN102891112B - Improve method and the dual gate CMOS of dual gate CMOS depletion of polysilicon - Google Patents
Improve method and the dual gate CMOS of dual gate CMOS depletion of polysilicon Download PDFInfo
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- CN102891112B CN102891112B CN201210413925.XA CN201210413925A CN102891112B CN 102891112 B CN102891112 B CN 102891112B CN 201210413925 A CN201210413925 A CN 201210413925A CN 102891112 B CN102891112 B CN 102891112B
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Abstract
The invention provides a kind of method improving dual gate CMOS depletion of polysilicon and dual gate CMOS.Initiating structure is provided, initiating structure includes Semiconductor substrate, Semiconductor substrate includes nFET device area and pFET device area, initiating structure be additionally included in nFET device area and pFET device area in substrate top from bottom to the gate-dielectric of top layout, the first material comprising polysilicon and hard mask silicon nitride.Remove the part hard mask in nFET device area and pFET device area.Perform gas phase doping or plasma immersion and ion implantation, thus the region eliminating part hard mask on which is doped.The surface in the region eliminating part hard mask thereon forms dielectric layer；Utilize silicon nitride and another part hard mask described in dielectric selective removal.Perform gas phase doping or the plasma immersion and ion implantation of another kind of electric conductivity with dielectric layer for hard mask again, thus the region eliminating above-mentioned another part hard mask on which is doped.
Description
Technical field
The present invention relates to semiconductor fabrication process, it is more particularly related to the one method of improving dual gate CMOS (complementary metal oxide semiconductors (CMOS)) depletion of polysilicon and the dual gate CMOS thus made.
Background technology
Interface or exhaust (poly-depletion effect) of the electric charge carrier of this near interface between gate oxide and polysilicon gate have become as the problem in cmos device (pFET device the most therein).Exhaust the substantially increase causing gate dielectric thickness, thus device performance is had a negative impact.Along with being gradually reduced of gate oxide thicknesses, the effect exhausted becomes more and more important.
U.S. Patent application US20070238276 " ontrol of poly-Si depletion in CMOS via gas phase doping " proposes the manufacture method of a kind of CMOS structure, and wherein gas phase doping is employed for provision the described adulterant at gate-dielectric/polysilicon interface.Specifically, Fig. 1 shows initiating structure 10, includes at least one nFET device area 14 and at least one pFET device area 16 including this Semiconductor substrate of Semiconductor substrate 12().Initiating structure 10 is additionally included in the material laminate 18 in nFET device area 14 and pFET device area 16 on substrate 12 top.Material laminate 18 includes gate-dielectric 20, the first material 22 comprising polysilicon and hard mask 24 from bottom to top.After forming the hard mask 24 of material laminate 18, the equal thick-layer (not shown) of photosensitive resist material is subsequently formed on hard mask 24 top.After forming the equal thick-layer of photosensitive resist material in hard mask 24, photosensitive resist material carries out photoetching.Hard mask 24 not protected in nFET device area 14 is selectively removed by etch process subsequently, and the structure of the gained formed after performing selectivity and removing technique is such as shown in Fig. 2.Subsequently, n-type dopant gas phase doping to first is comprised the expose portion of the material 22 of polysilicon.Hereafter, removing is positioned at the hard mask 24 on material 22 top that pFET device area 16 first comprises polysilicon.Then, as it is shown on figure 3, the second hard mask 24 ' is formed in nFET device area 14 on the top of the first material 26 comprising polysilicon of N-shaped doping.After forming structure shown in Fig. 3, perform the second gas phase doping technique.The adulterant of (compared with the doping used above) films of opposite conductivity is introduced the material 22 comprising polysilicon exposed by younger brother two gas phase doping technique.Subsequently P-type dopant gas phase doping to first is comprised the expose portion of the material 22 of polysilicon.After removing the first hard mask 24 ' from this structure, the film (not shown) that second comprises polysilicon is formed at above the first material 26 comprising polysilicon of N-shaped doping and the first material 28 comprising polysilicon of p-type doping;Second polysilicon film will eventually become the layer 34 and 32 shown in Fig. 4.
But, two extra mask layers are needed for above-mentioned U.S. Patent application US20070238276, are therefore unfavorable for cost control.
Summary of the invention
The technical problem to be solved is for there is drawbacks described above in prior art, it is provided that a kind of method improving dual gate CMOS depletion of polysilicon of low cost and the dual gate CMOS thus made.
In order to realize above-mentioned technical purpose, according to the first aspect of the invention, provide a kind of method improving dual gate CMOS depletion of polysilicon, comprising: first step, for providing initiating structure, initiating structure includes Semiconductor substrate, described Semiconductor substrate includes at least one nFET device area and at least one pFET device area, described initiating structure is additionally included in the material laminate in nFET device area and pFET device area in substrate top, and described material laminate includes gate-dielectric, the first material comprising polysilicon and hard mask from bottom to top；Second step, for using the method for photoetching and etching to remove the part hard mask in nFET device area and pFET device area, and stay in nFET device area and pFET device area another on another part hard mask；Third step, for performing gas phase doping or the plasma immersion and ion implantation of a kind of electric conductivity after eliminating part hard mask, thus the region eliminating part hard mask on which is doped；4th step, the surface being used for eliminating thereon the region of part hard mask forms dielectric layer；5th step, utilizes silicon nitride and dielectric selectivity, uses the wet etching to dielectric layer with high selectivity to remove described another part hard mask；6th step, for performing gas phase doping or the plasma immersion and ion implantation of another kind of electric conductivity again with dielectric layer for hard mask, thus the region eliminating above-mentioned another part hard mask on which is doped.
Preferably, described hard mask is silicon nitride layer.
Preferably, in the 4th step, utilize the method for quick heated oxide processing procedure or boiler tube thermal oxide eliminate thereon part hard mask region surface formed dielectric layer.
Preferably, described dielectric layer is silicon oxide layer.
Preferably, the wet process soaking hot phosphoric acid is used to remove another part hard mask (silicon nitride).
Preferably, one in nFET device area and pFET device area is nFET device area.
Preferably, one in nFET device area and pFET device area is pFET device area.
According to the second aspect of the invention, it is provided that a kind of dual gate CMOS that have employed the method improving dual gate CMOS depletion of polysilicon described according to the first aspect of the invention and make.
Compared with prior art, decrease a mask according to the method improving dual gate CMOS depletion of polysilicon of the present invention, therefore significantly reduce cost.
Accompanying drawing explanation
In conjunction with accompanying drawing, and by with reference to detailed description below, it will more easily the present invention is had more complete understanding and its adjoint advantage and feature is more easily understood, wherein:
Fig. 1 to Fig. 4 schematically shows each step of the method improving dual gate CMOS depletion of polysilicon according to prior art.
Fig. 5 to Fig. 8 schematically shows each step of the method improving dual gate CMOS depletion of polysilicon according to embodiments of the present invention.
It should be noted that accompanying drawing is used for illustrating the present invention, and the unrestricted present invention.Note, represent that the accompanying drawing of structure may be not necessarily drawn to scale.Further, in accompanying drawing, same or like element indicates same or like label.
Detailed description of the invention
In order to make present disclosure more clear and understandable, below in conjunction with specific embodiments and the drawings, present disclosure is described in detail.
Fig. 5 to Fig. 8 schematically shows each step of the method improving dual gate CMOS depletion of polysilicon according to embodiments of the present invention.
As shown in Fig. 5 to Fig. 8, the method improving dual gate CMOS depletion of polysilicon according to embodiments of the present invention includes:
First step, is used for providing initiating structure 10, initiating structure 10 to include Semiconductor substrate 12, and this Semiconductor substrate includes at least one nFET device area 14 and at least one pFET device area 16.Initiating structure 10 is additionally included in the material laminate 18 in nFET device area 14 and pFET device area 16 on substrate 12 top.Material laminate 18 includes gate-dielectric 20, the first material 22 comprising polysilicon and hard mask 24 from bottom to top.Preferably, hard mask 24 is silicon nitride layer.The structure obtained by first step is as shown in Figure 5.
Second step, for using the method for photoetching and etching to remove the part hard mask 24 on one of nFET device area 14 and pFET device area 16, in the present embodiment, eliminate the part hard mask 24 on pFET device area 16, and leave another part hard mask 24 on nFET device area 14.The structure obtained by second step is as shown in Figure 6.
Third step, for performing gas phase doping or the plasma immersion and ion implantation of a kind of electric conductivity after eliminating part hard mask 24, thus the region (in the present embodiment for pFET device area 16) eliminating part hard mask 24 on which is doped.
4th step, for by such as quickly heated oxide processing procedure (Rapid Thermal Oxidation) or the method for boiler tube thermal oxide, the surface in the region (in the present embodiment for pFET device area 16) eliminating part hard mask 24 thereon forms dielectric layer 30；Preferably, described dielectric layer 30 is silicon oxide layer.The structure obtained by the 4th step is as shown in Figure 7.
5th step, is used for utilizing silicon nitride and dielectric selective removal above-mentioned another part hard mask 24.Preferably, employing has wet etching another part hard mask 24(such as silicon nitride of high selectivity to dielectric layer)；Such as, the wet process soaking hot phosphoric acid is used to remove another part hard mask 24(such as silicon nitride), the die staying dielectric layer 30 to be another region.The structure such as Fig. 8 obtained by the 5th step
Shown in.
6th step, for performing gas phase doping or the plasma immersion and ion implantation of another kind of electric conductivity again with dielectric layer 30 for hard mask, thus the region (in the present embodiment for nFET device area 14) eliminating above-mentioned another part hard mask 24 on which is doped.
It can be seen that compared with the U.S. Patent application US20070238276 of prior art, the method improving dual gate CMOS depletion of polysilicon of the embodiment of the present invention decreases a mask, therefore significantly reduces cost.
Although above embodiment illustrates in the case of first removing the hard mask 24 on pFET device area 16, it will be appreciated by those skilled in the art that it is of course possible to first remove the hard mask 24 on nFET device area 14.
According to another preferred embodiment of the invention, present invention also offers a kind of dual gate CMOS thus made by said method.
In addition, it should be noted that, unless stated otherwise or point out, otherwise the term in description " first ", " second ", " the 3rd " etc. describe be used only for distinguishing in description each assembly, element, step etc. rather than for representing the logical relation between each assembly, element, step or ordering relation etc..
Although it is understood that the present invention discloses as above with preferred embodiment, but above-described embodiment is not limited to the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit, technical solution of the present invention is made many possible variations and modification by the technology contents that all may utilize the disclosure above, or is revised as the Equivalent embodiments of equivalent variations.Therefore, every content without departing from technical solution of the present invention, the technical spirit of the foundation present invention, to any simple modification made for any of the above embodiments, equivalent variations and modification, all still falls within the range of technical solution of the present invention protection.
Claims (7)
1. the method improving dual gate CMOS depletion of polysilicon, it is characterised in that including:
First step, is used for providing initiating structure, initiating structure to include Semiconductor substrate, and described quasiconductor serves as a contrast
The end, includes at least one nFET device area and at least one pFET device area, and described initiating structure also wraps
Include the material laminate in substrate top, described material laminate in nFET device area and pFET device area
Include gate-dielectric, the first material comprising polysilicon and hard mask to top from bottom；
Second step, for using the method for photoetching and etching to remove nFET device area and pFET device region
The part hard mask on a region in territory, and stay in nFET device area and pFET device area
Another part hard mask on another region；
Third step, for perform after eliminating part hard mask a kind of electric conductivity gas phase doping or etc.
Gas ions immersion ion injects, thus the region eliminating part hard mask on which is doped；
4th step, the surface being used for eliminating thereon the region of part hard mask forms dielectric layer；
5th step, is used for utilizing hard mask and another part hard mask described in dielectric selective removal,
The hard mask staying dielectric layer to be another region；
6th step, for perform again with dielectric layer for hard mask another kind of electric conductivity gas phase doping or etc.
Gas ions immersion ion injects, thus the region eliminating above-mentioned another part hard mask on which is doped.
The method improving dual gate CMOS depletion of polysilicon the most according to claim 1, it is characterised in that
Described hard mask is silicon nitride layer.
The method improving dual gate CMOS depletion of polysilicon the most according to claim 1 and 2, its feature
It is, in the 4th step, utilizes the method for quick heated oxide processing procedure or boiler tube thermal oxide to go thereon
Except the surface in the region of part hard mask forms dielectric layer.
The method improving dual gate CMOS depletion of polysilicon the most according to claim 1 and 2, its feature
Being, described dielectric layer is silicon oxide layer.
The method improving dual gate CMOS depletion of polysilicon the most according to claim 1 and 2, its feature
It is, in the 5th step, uses wet etching to remove hard mask layer selectively, leave dielectric layer
Hard mask for another region.
The method improving dual gate CMOS depletion of polysilicon the most according to claim 1 and 2, its feature
Being, in nFET device area and pFET device area is nFET device area.
The method improving dual gate CMOS depletion of polysilicon the most according to claim 1 and 2, its feature
Being, in nFET device area and pFET device area is pFET device area.
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