CN102683203B - Method for manufacturing built-in stress nanowire - Google Patents
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Abstract
The invention provides a method for manufacturing a built-in stress nanowire. The method uses a gate-last process (Gate-last), the lateral face of an NWFET area is protected through a SiO2 layer when a grid electrode area is etched, the reverse stress direction borne by the nanowire (SiNW) of the grid electrode area is in the horizontal direction at the time so that the problem that reverse built-in stress of the semiconductor nanowire is not in the horizontal direction is solved, disposition which possibly occurs on the middle portion of the semiconductor nanowire is avoided, even the breaking problem can be solved. The upper surface of a source drain PAD is higher than the SiNW, so that upper surfaces of the source drain and the grid electrode are in a same plane, a grid electrode lateral wall process is not needed, and process flows are simplified.
Description
Technical field
The present invention relates to a kind of method of making semiconductor nanowires, relate in particular to a kind of method of built-in stress silicon nano wire, the method for making semiconductor device and prepared semiconductor device made.
Background technology
Current, in advanced semiconductor device manufacture, introduce strain engineering very general, the MOSFET that is <110> for channel direction, when channel direction has tensile stress, can effectively increase the current driving ability of NMOSFET, and when channel direction has compression, can effectively increase the current driving ability of PMOSFET.
As a same reason, for state-of-the-art semiconductor nanowires field-effect transistor (Nanowire Field Effect Transistor, NWFET), if introduce strain engineering in its nanowire length direction (being channel direction), also the current driving ability of NWFET will be increased greatly.As having reported to introduce after stress engineering in IEDM2010 meeting paper " Understanding of Short-Channel Mobility in Tri-Gate Nanowire MOSFETs and Enhanced Stress Memorization Technique for Performance Improvement ", the people such as Masumi Saitoh (adopt stress memory technique in for <110> crystal orientation NW-FET, SMT), current driving ability has increased 58%.
US Patent No. 2011/0104860 A1 discloses a kind of built-in stressed semiconductor the fabricate of nanowires method, its Semiconductor substrate (as SOI substrate) based on thering is oxygen buried layer, after prepared by semiconductor nanowires, deposition one deck strain film layer (compressive strain thin layer or tensile strain thin layer), as strain silicon nitride layer.If (being NWFET channel direction) has tensile stress along its length in semiconductor nanowires that need to be final, first deposit the thin layer that one deck has compressive strain, follow-up by the strain film etching of area of grid after, contraction due to the strain film of both sides source and drain areas, makes the semiconductor nanowires of area of grid (being channel region) have tensile stress.After grid technology completes, the tensile stress of this semiconductor nanowires length direction (being NWFET channel direction) is just fixed in semiconductor nanowires, and follow-up compressive strain thin layer can not make this tensile stress disappear yet after removing.
If (being NWFET channel direction) has compression along its length in semiconductor nanowires that need to be final, first deposit the thin layer that one deck has tensile strain, follow-up by the strain film etching of area of grid after, tension force effect due to the strain film of both sides source and drain areas, makes the semiconductor nanowires of area of grid (being channel region) have compression.After grid technology completes, the compression of this semiconductor nanowires length direction (being NWFET channel direction) is just fixed in semiconductor nanowires, and follow-up tensile strain thin layer can not make this compression disappear yet after removing.
Lower surface analysis the first situation, i.e. (being NWFET channel direction) tensile stress situation along its length in final semiconductor nanowires:
As shown in figure 16, the semiconductor nanowires 32C of this structure is connected with 32B with semiconductor liner (Pad) 32A, and semiconductor liner 32A is connected with 22B with dielectric base 22A with 32B, in its technique preparation process, there is a step to be, be wrapped in that compressive strain film on semiconductor nanowires is etched away and only retain and be wrapped in the compressive strain film on semiconductor liner 32A and 32B, at this moment, be subject to both sides shrinkage stress effect, the suffered power of semiconductor nanowires 32C is not in the horizontal direction in fact, but as the reverse tensile stress of the downward certain angle of level marking in figure.When semiconductor nanowires is enough thin, this not reverse tensile stress in the horizontal direction may cause semiconductor nanowires middle part to misplace, and even ruptures.
Lower surface analysis the second situation, i.e. (being NWFET channel direction) compression situation along its length in final semiconductor nanowires:
As shown in figure 17, the semiconductor nanowires 32C of this structure is connected with 32B with semiconductor liner (Pad) 32A, and semiconductor liner 32A is connected with 22B with dielectric base 22A with 32B, in its technique preparation process, there is a step to be, be wrapped in that tensile strain film on semiconductor nanowires is etched away and only retain and be wrapped in the tensile strain film on semiconductor liner 32A and 32B, at this moment, be subject to both sides tensile stress effect, the suffered power of semiconductor nanowires 32C is not in the horizontal direction in fact, but as the make progress reverse compression of certain angle of the level marking in figure.When semiconductor nanowires is enough thin, this not reverse compression in the horizontal direction may cause semiconductor nanowires middle part to misplace, and even ruptures.
Summary of the invention
In prior art, make stress that built-in stress nano wire technique exists and cause dislocation, the problem of fracture even, the invention provides a kind of method of built-in stress silicon nano wire, the method for making semiconductor device and semiconductor device prepared by described method made.
First object of the present invention is to provide a kind of method of making built-in stress silicon nano wire, and step comprises:
Step 1, provides soi wafer as substrate, and the described soi wafer the superiors are top silicon layer, and top silicon layer below is oxygen buried layer; At top silicon layer upper surface extension one deck germanium layer or germanium silicon layer;
Adopt germanium oxidation method for concentration, in germanium layer or the germanium silicon surface of extension, carry out oxidation processes, make Ge be concentrated into the top silicon layer of below, make top silicon layer become germanium silicon layer, and the top forms silicon dioxide layer;
Remove the silicon dioxide layer of the top, thereby substrate top layer becomes top layer germanium silicon layer from top silicon layer;
Step 2, extension one deck silicon layer and germanium silicon layer successively on top layer germanium silicon layer, by photoetching, determine that Si nano-wire field effect transistor prepares region, then by the determined Si nano-wire field effect transistor of etching, prepare region around germanium silicon layer, silicon layer and top layer germanium silicon layer, form Si nano-wire field effect transistor and prepare region; Described Si nano-wire field effect transistor is prepared region and is comprised the source-drain area liner at two ends and be connected to the Si nano wire region between source-drain area liner;
The germanium silicon of Si nano wire region upper and lower is removed, between Si nano wire region and below oxygen buried layer, formed cavity; Then by thermal oxidation technology wet method, remove the oxide layer of Si nanowire region field surface, make and obtain silicon nanowires;
Step 3, at source-drain area liner, silicon nanowires and oxide layer surface deposition strain film; Then on strain film, deposit Dummy spacer medium layer (as silicon dioxide), described cavity is filled with Dummy spacer medium.
Then can prepare grid according to conventional method.
Second object of this aspect is to provide a kind of method of making semiconductor device, and step comprises:
Step 1, provides soi wafer as substrate, and the described soi wafer the superiors are top silicon layer, and top silicon layer below is oxygen buried layer; At top silicon layer upper surface extension one deck germanium layer or germanium silicon layer;
Adopt germanium oxidation method for concentration, in germanium layer or the germanium silicon surface of extension, carry out oxidation processes, make Ge be concentrated into the top silicon layer of below, make top silicon layer become germanium silicon layer, and the top forms silicon dioxide layer;
Remove the silicon dioxide layer of the top, thereby substrate top layer becomes top layer germanium silicon layer from top silicon layer;
Step 2, extension one deck silicon layer and germanium silicon layer successively on top layer germanium silicon layer, by photoetching, determine that Si nano-wire field effect transistor prepares region, then by the determined Si nano-wire field effect transistor of etching, prepare region around germanium silicon layer, silicon layer and top layer germanium silicon layer, form Si nano-wire field effect transistor and prepare region; Described Si nano-wire field effect transistor is prepared region and is comprised the source-drain area liner at two ends and be connected to the Si nano wire region between source-drain area liner;
The germanium silicon of Si nano wire region upper and lower is removed, between Si nano wire region and below oxygen buried layer, formed cavity; Then by thermal oxidation technology wet method, remove the oxide layer of Si nanowire region field surface, make and obtain silicon nanowires;
Step 3, at source-drain area liner, silicon nanowires and oxide layer surface deposition strain film; Then on strain film, deposit Dummy spacer medium layer (as silicon dioxide), described cavity is filled with Dummy spacer medium;
Step 4, in step 3, on the Dummy spacer medium layer of deposition, by photoetching, determine that grid prepares region, being prepared by grid to the Dummy spacer medium layer-selective etching in region removes, expose grid and prepare the Si nano wire in region, in the Si nanowire surface of exposing, form grid oxide layer, then at grid, prepare area deposition grid material, form grid;
Step 5, removes the Dummy spacer medium layer depositing in remaining step 3, and remaining strain film;
Step 6, the product surface obtaining in step 5 deposition spacer medium layer, by grid and the isolation of both sides source-drain area liner; Then carry out the injection technology of source-drain area, form source region and drain region;
Step 7, in source region, drain region and gate upper surface carry out metal semiconductor alloy technique, then prepares contact hole above source region, drain region and grid, draws the source electrode of NWFET, drain and gate.
The 3rd aspect of the present invention is to provide the semiconductor device that a kind of said method is made.
In foregoing of the present invention, in described soi wafer, oxygen buried layer thickness is preferably 10 ~ 1000nm, and top silicon layer thickness is preferably 10 ~ 200nm.
In foregoing of the present invention, in step 2, the germanium silicon of Si nano wire region upper and lower is removed in technique, described etching is preferably selective etch technology, is specifically preferably: adopt the H of 600 ~ 800 ℃
2with HCl mist, utilize time normal pressure chemical gas phase etching method to carry out selective etch, wherein the dividing potential drop of HCl is greater than 300Torr.
In foregoing of the present invention, described Si nano wire cross sectional shape can be any available shape, as shapes such as circular, horizontal runway, longitudinal runways.
In foregoing of the present invention, described strain film can be compressive strain film or tensile strain film, and according to a preferred embodiment of the present invention, deposition compressive strain film, so that follow-up silicon nanowires length direction (being SiNWFET channel direction) has tensile stress; Or according to another kind of preferred embodiment of the present invention, deposition tensile strain film, so that follow-up silicon nanowires length direction (being SiNWFET channel direction) has compression.
Wherein, described strain film material is preferably silicon nitride.
In foregoing of the present invention, described grid oxide layer material can be to prepare SiO by thermal oxidation or depositing operation
2or SiON or Si
3n
4or the high κ material of preparing by depositing operation or the combination in any of above-mentioned substance, wherein, described high κ material is as HfO
2, ZrO
2, La
2o
3, Al
2o
3, TiO
2, SrTiO
3, LaAlO
3, Y
2o
3, HfO
xn
y, ZrO
xn
y, La
2o
xn
y, Al
2o
xn
y, TiO
xn
y, SrTiO
xn
y, LaAlO
xn
y, Y
2o
xn
ya kind of or arbitrarily several combination.
In foregoing of the present invention, described grid material can be polysilicon, amorphous silicon, metal or any several combination wherein.
In foregoing of the present invention, described spacer medium is preferably silicon dioxide.
The present invention adopts rear grid technique (Gate-last), and when carrying out area of grid etching, side, SiNWFET region has SiO
2layer protection; at this moment the reversal of stress direction that the SiNW of area of grid is subject to is horizontal direction; thereby efficiently solve the problem of US Patent No. 2011/0104860A1; avoided not problem in the horizontal direction of the reverse built-in stress of silicon nanowires; thereby avoided the contingent dislocation in silicon nanowires middle part, even breakage problem.
Simultaneously, owing to adopting the sandwich structure of germanium silicon layer+silicon layer+germanium silicon layer, can form well the empty structure in silicon nanowires below by selective etch technology, than other two patents of applicant, adopt etching to form empty method, solved the defect of " etch period and etching depth cannot accurately be controlled "; And, because substrate top surface is leaked higher than Si nano wire in source, can realize source leakage and gate upper surface at same plane, thereby not need grid curb wall technique, simplified technological process.
Accompanying drawing explanation
Fig. 1 ~ Figure 14 is that the present invention makes built-in stress silicon nano wire and semiconductor device method flow diagram, wherein:
Fig. 1 is silicon epitaxial layers or germanium silicon layer structural representation on substrate;
Fig. 2 is that top silicon layer is converted into top layer germanium silicon layer schematic diagram;
Fig. 3 is silicon epitaxial layers and germanium silicon layer schematic diagram successively on top layer germanium silicon layer;
Fig. 4 A is that etching formation SiNWFET prepares region cross section view; Fig. 4 B is that etching formation SiNWFET prepares region vertical view;
Fig. 5 A is selective removal Si nano wire region germanium silicon layer schematic diagram; Fig. 5 B is preparation Si nano wire schematic diagram;
Fig. 6 is deposit strained film schematic diagram;
Fig. 7 A is deposition Dummy spacer medium layer schematic diagram; Fig. 7 B is for removing unnecessary Dummy spacer medium layer schematic diagram;
Fig. 8 A is preparation gate regions generalized section; Fig. 8 B is preparation gate regions vertical view;
Fig. 9 A is for preparing grid oxide layer generalized section; Fig. 9 B is for preparing grid oxide layer vertical view;
Figure 10 A is deposition of gate material schematic diagram; Figure 10 B is for preparing grid schematic diagram;
Figure 11 is for removing Dummy spacer medium layer and strain film schematic diagram;
Figure 12 A is deposition spacer medium schematic diagram; Figure 12 B is for removing unnecessary spacer medium schematic diagram;
Figure 13 is metal semiconductor alloy technique schematic diagram;
Figure 14 is contact hole process schematic representation;
Figure 15 is Si nanowire cross-section schematic diagram, wherein: Figure 15 A be circular, Figure 15 B for laterally run-track shaped, Figure 15 C is for longitudinally run-track shaped;
Figure 16 is tensile stress situation along its length in semiconductor nanowires in prior art;
Figure 17 is compression situation along its length in semiconductor nanowires in prior art.
Embodiment
embodiment 1
Step 1
With reference to Fig. 1, provide soi wafer, the top silicon layer 2 of the oxygen buried layer 1 in the middle of soi wafer comprises and oxygen buried layer top.
In top silicon layer 2, deposit germanium layer or germanium silicon layer 3, utilize germanium oxygen concentration method, germanium layer or germanium silicon surface are carried out to oxidation processes, at this moment, Ge can be concentrated to downwards in top silicon layer 2 below, makes top silicon layer become top layer Si Ge layer 21, and becomes SiO topmost
2layer 31, as shown in Figure 2.
Step 2
Wet method is removed SiO
2layer 31, above top layer Si Ge layer 21 successively extension one deck silicon layer 4(in this silicon layer by the channel region of preparation SiNWFET, in epitaxial process, carry out SiNWFET channel doping simultaneously) and one deck germanium silicon layer 5, as shown in Figure 3.
With reference to Fig. 4 A, determine that SiNWFET prepares region, photoresist 50 covers described SiNWFET and prepares region, then prepared by described SiNWFET to region germanium silicon layer 5, silicon layer 4 and top layer germanium silicon layer 21 around and carry out photoetching removal, be etched to oxygen buried layer 1, form SiNWFET and prepare region, as shown in Figure 4 B, SiNWFET is Si nano wire region 51 in the middle of preparing region, and two ends are source region liner 52 and drain region liner 53.
With reference to Fig. 5 A, remove photoresist 50, selective etch technology is removed the germanium silicon layer of Si nano wire region 51 tops and the top layer germanium silicon layer of below, forms cavity 6 between Si nano wire region 51 and oxygen buried layer 1.Lithographic method is as follows: the H of 600 ~ 800 ℃
2with HCl mist, utilize time normal pressure chemical gas phase etching method to carry out selective etch, wherein the dividing potential drop of HCl is greater than 300Torr, and at this moment the germanium silicon in source region liner 52 and drain region liner 53 regions also can side direction be removed a part.
As Fig. 5 B removes the oxide layer of silicon surface by thermal oxidation technology+wet method, prepare semiconductor nanowires 54.According to different silicon nanowires region etching width and epitaxial silicon layer thickness, the cross sectional shape of semiconductor nanowires is also different, can be circular (Figure 15 A), horizontal track type (Figure 15 B) or longitudinal track type (Figure 15 C).
Step 3,
At source-drain area liner, silicon nanowires and oxide layer surface deposition strain film 7(as shown in Figure 6); Then on strain film, deposit Dummy spacer medium layer (as silicon dioxide) 8, described empty 6 use Dummy spacer mediums are filled to (as Fig. 7 A).Wherein, silicon nanowires length direction as follow-up in needs (being SiNWFET channel direction) has tensile stress, deposits compressive strain thin layer; Silicon nanowires length direction as follow-up in needs (being SiNWFET channel direction) has compression, deposits tensile strain thin layer.Then can according to common process carry out grid preparation, and finally prepare semiconductor device.
Semiconductor device preparation method of the present invention is preferably the method described in embodiment 2:
embodiment 2
Step 1
With reference to Fig. 1, provide soi wafer, the top silicon layer 2 of the oxygen buried layer 1 in the middle of soi wafer comprises and oxygen buried layer top.
In top silicon layer 2, deposit germanium layer or germanium silicon layer, utilize germanium oxygen concentration method, germanium layer or germanium silicon surface are carried out to oxidation processes, at this moment, Ge can be concentrated to downwards in top silicon layer 2 below, makes top silicon layer become top layer Si Ge layer 21, and becomes SiO topmost
2layer 31, as shown in Figure 2.
Step 2
Wet method is removed SiO
2layer 31, above top layer Si Ge layer 21 successively extension one deck silicon layer 4(in this silicon layer by the channel region of preparation SiNWFET, in epitaxial process, carry out SiNWFET channel doping simultaneously) and one deck germanium silicon layer 5, as shown in Figure 3.
With reference to Fig. 4 A, determine that SiNWFET prepares region, hard mask covers described SiNWFET and prepares region, then prepared by described SiNWFET to region germanium silicon layer 5, silicon layer 4 and top layer germanium silicon layer 21 around and carry out etching, be etched to oxygen buried layer 1, form SiNWFET and prepare region, as shown in Figure 4 B, SiNWFET is Si nano wire region 51 in the middle of preparing region, and two ends are source region liner 52 and drain region liner 53.
With reference to Fig. 5 A, remove hard mask, selective etch technology is removed the germanium silicon layer of Si nano wire region 51 tops and the top layer germanium silicon layer of below, forms cavity 6 between Si nano wire region 51 and oxygen buried layer 1.Lithographic method is as follows: the H of 600 ~ 800 ℃
2with HCl mist, utilize time normal pressure chemical gas phase etching method to carry out selective etch, wherein the dividing potential drop of HCl is greater than 300Torr, and at this moment the germanium silicon in source region liner 52 and drain region liner 53 regions also can side direction be removed a part.
As Fig. 5 B removes the oxide layer of silicon surface by thermal oxidation technology+wet method, prepare semiconductor nanowires 54.According to different silicon nanowires region etching width and epitaxial silicon layer thickness, the cross sectional shape of semiconductor nanowires is also different, can be circular (Figure 15 A), horizontal track type (Figure 15 B) or longitudinal track type (Figure 15 C).
Step 3,
At source-drain area liner, silicon nanowires and oxide layer surface deposition strain film 7(as shown in Figure 6); Then on strain film, deposit Dummy spacer medium layer (as silicon dioxide) 8, described empty 6 use Dummy spacer mediums are filled to (as Fig. 7 A).
With reference to Fig. 7 B, unnecessary Dummy spacer medium layer is removed by CMP technique, make the strain film upper surface flush in Dummy spacer medium layer 8 upper surface and source region substrate 52, drain region substrate 53.
Step 4
With reference to Fig. 8 A and Fig. 8 B, determine gate regions 90, adopt photoetching, etching (can adopt PR mask, also can adopt Hard mask) to define by the area of grid of SiNWFET 90 etchings out, strain film layer in this region is etched away, and till etching into oxygen buried layer 1 always.At this moment, if former strain film layer is compressive strain characteristic, due to the contraction that substrate region strain film layer is leaked in source, the Si nano wire 54 of area of grid just has tensile stress; And if former strain film layer is tensile strain characteristic, due to the tension force effect that cushion region strain film layer is leaked in source, the Si nano wire of area of grid just has compression.Simultaneously; from profile; due to the existing Dummy spacer medium layer protection in side, SiNWFET region, the reversal of stress direction that at this moment the Si nano wire of area of grid is subject to is horizontal direction, thereby efficiently solves the problem of US Patent No. 2011/0104860A1.
By grid oxygen technique, on the surface of Si nano wire 54, prepare grid oxide layer 10, described grid oxygen technique can be prepared SiO by thermal oxidation or depositing operation
2or SiON or Si
3n
4or the high κ material of preparing by depositing operation or the combination in any of above-mentioned substance, wherein, high κ material can be HfO
2, ZrO
2, La
2o
3, Al
2o
3, TiO
2, SrTiO
3, LaAlO
3, Y
2o
3, HfO
xn
y, ZrO
xn
y, La
2o
xn
y, Al
2o
xn
y, TiO
xn
y, SrTiO
xn
y, LaAlO
xn
y, Y
2o
xn
ya kind of or combination in any, as shown in Fig. 9 A and 9B.
Then in area of grid 90 deposition of gate material 11, grid material 11 can be polysilicon, amorphous silicon, metal or its combination, as Figure 10 A, then adopt CMP technique to remove unnecessary grid material, make Dummy spacer medium layer 8 upper surface flush of deposition in grid material upper surface and step 3, form grid.
Step 5
Wet method is removed Dummy spacer medium layer 8, wet method is removed remaining strain film 7, Dummy spacer medium layer 8, the strain film 7 in grid 9 both sides and cavity especially, as shown in figure 11; At this moment because grid oxide layer technique and grid technology complete, the stress in semiconductor nanowires is retained in semiconductor nanowires length direction (being NWFET channel direction) and can disappear because of the removal of strain film layer.
Step 6
With reference to Figure 12 A and Figure 12 B, between the source region of grid 9 and both sides liner 52 and drain region liner 53, deposit spacer medium (as SiO
2), by CMP technique, remove unnecessary spacer medium, and be ground to gate upper surface and source and leak liner upper surface at grade, due to source leak and gate upper surface at same plane, and between them, there is spacer medium to isolate, therefore do not need grid curb wall technique, thereby simplified technological process.
After CMP completes, carry out the injection technology of source-drain area, form source region and drain region.
Step 7
With reference to Figure 13 and Figure 14 in source region, drain region and gate upper surface carry out metal semiconductor alloy technique, form respectively source metal semiconductor compound 132, drain metal semiconductor compound 133 and gate metal semiconductor compound 131, then above source region, drain region and grid, prepare contact hole 14, the source electrode of NWFET, drain and gate are drawn, prepare semiconductor device.
Above specific embodiments of the invention be have been described in detail, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and alternative also all among category of the present invention.Therefore, equalization conversion and the modification done without departing from the spirit and scope of the invention, all should contain within the scope of the invention.
Claims (10)
1. make a method for built-in stress silicon nano wire, it is characterized in that, step comprises:
Step 1, provides soi wafer as substrate, and the described soi wafer the superiors are top silicon layer, and top silicon layer below is oxygen buried layer; At top silicon layer upper surface extension one deck germanium layer or germanium silicon layer;
Adopt germanium oxidation method for concentration, in germanium layer or the germanium silicon surface of extension, carry out oxidation processes, make Ge be concentrated into the top silicon layer of below, make top silicon layer become germanium silicon layer, and the top forms silicon dioxide layer;
Remove the silicon dioxide layer of the top, thereby substrate top layer becomes top layer germanium silicon layer from top silicon layer;
Step 2, extension one deck silicon layer and germanium silicon layer successively on top layer germanium silicon layer, by photoetching, determine that Si nano-wire field effect transistor prepares region, then by the determined Si nano-wire field effect transistor of etching, prepare region around germanium silicon layer, silicon layer and top layer germanium silicon layer, form Si nano-wire field effect transistor and prepare region; Described Si nano-wire field effect transistor is prepared region and is comprised the source-drain area liner at two ends and be connected to the Si nano wire region between source-drain area liner;
The germanium silicon of Si nano wire region upper and lower is removed, between Si nano wire region and below oxygen buried layer, formed cavity; Then by thermal oxidation technology wet method, remove the oxide layer of Si nanowire region field surface, make and obtain silicon nanowires;
Step 3, at source-drain area liner, silicon nanowires and oxide layer surface deposition strain film; Then on strain film, deposit Dummy spacer medium layer, described cavity is filled with Dummy spacer medium;
Wherein, grid technique after adopting, when carrying out area of grid etching, there is SiO side, SiNWFET region
2layer protection, the reversal of stress direction that at this moment SiNW of area of grid is subject to is horizontal direction, avoids the reverse built-in stress of silicon nanowires not in the horizontal direction, thus dislocation and the fracture of having avoided silicon nanowires middle part to occur.
2. method according to claim 1, is characterized in that, in described soi wafer, oxygen buried layer thickness is 10～1000nm, and top silicon layer thickness is 10～200nm.
3. method according to claim 1, is characterized in that, in step 2, the germanium silicon of Si nano wire region upper and lower is removed in technique, and described etching is selective etch technology.
4. method according to claim 3, is characterized in that, described selective etch technology is: adopt the H of 600～800 ℃
2with HCl mist, utilize time normal pressure chemical gas phase etching method to carry out selective etch, wherein the dividing potential drop of HCl is greater than 300Torr.
5. method according to claim 1, is characterized in that, described strain film is compressive strain film.
6. method according to claim 1, is characterized in that, described strain film is tensile strain film.
7. a method of making semiconductor device, is characterized in that, step comprises:
Step 1, provides soi wafer as substrate, and the described soi wafer the superiors are top silicon layer, and top silicon layer below is oxygen buried layer; At top silicon layer upper surface extension one deck germanium layer or germanium silicon layer;
Adopt germanium oxidation method for concentration, in germanium layer or the germanium silicon surface of extension, carry out oxidation processes, make Ge be concentrated into the top silicon layer of below, make top silicon layer become germanium silicon layer, and the top forms silicon dioxide layer;
Remove the silicon dioxide layer of the top, thereby substrate top layer becomes top layer germanium silicon layer from top silicon layer; Step 2, extension one deck silicon layer and germanium silicon layer successively on top layer germanium silicon layer, by photoetching, determine that Si nano-wire field effect transistor prepares region, then by the determined Si nano-wire field effect transistor of etching, prepare region around germanium silicon layer, silicon layer and top layer germanium silicon layer, form Si nano-wire field effect transistor and prepare region; Described Si nano-wire field effect transistor is prepared region and is comprised the source-drain area liner at two ends and be connected to the Si nano wire region between source-drain area liner;
The germanium silicon of Si nano wire region upper and lower is removed, between Si nano wire region and below oxygen buried layer, formed cavity; Then by thermal oxidation technology wet method, remove the oxide layer of Si nanowire region field surface, make and obtain silicon nanowires;
Step 3, at source-drain area liner, silicon nanowires and oxide layer surface deposition strain film; Then on strain film, deposit Dummy spacer medium layer, by described cavity Filled Dielectrics;
Step 4, in step 3, on the Dummy spacer medium layer of deposition, by photoetching, determine that grid prepares region, being prepared by grid to the Dummy spacer medium layer-selective etching in region removes, expose grid and prepare the Si nano wire in region, in the Si nanowire surface of exposing, form grid oxide layer, then at grid, prepare area deposition grid material, form grid;
Step 5, removes the Dummy spacer medium layer and the remaining strain film that in remaining step 3, deposit;
Step 6, the product surface obtaining in step 5 deposition spacer medium layer, by grid and the isolation of both sides source-drain area liner; Then carry out the injection technology of source-drain area, form source region and drain region;
Step 7, in source region, drain region and gate upper surface carry out metal semiconductor alloy technique, then prepares contact hole above source region, drain region and grid, and the source electrode of NWFET, drain and gate are drawn, and prepares semiconductor device.
8. method according to claim 7, is characterized in that, described grid oxide layer material is: the SiO preparing by thermal oxidation or depositing operation
2or SiON or Si
3n
4or the high κ material of preparing by depositing operation or the combination in any of above-mentioned substance.
9. method according to claim 7, is characterized in that, described spacer medium is preferably silicon dioxide.
10. the semiconductor device that method is made as claimed in claim 7.
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| CN102339754A (en) * | 2010-07-22 | 2012-02-01 | 中国科学院上海微系统与信息技术研究所 | Preparation method of metal-oxide-semiconductor field-effect transistor with silicon-on-nothing (SON) structure |
| CN102437017A (en) * | 2011-09-30 | 2012-05-02 | 中国科学院上海微系统与信息技术研究所 | Method for preparing nano structure on surface of (111) silicon wafer |
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