US9496356B2 - Under-spacer doping in fin-based semiconductor devices - Google Patents
Under-spacer doping in fin-based semiconductor devices Download PDFInfo
- Publication number
- US9496356B2 US9496356B2 US14/879,159 US201514879159A US9496356B2 US 9496356 B2 US9496356 B2 US 9496356B2 US 201514879159 A US201514879159 A US 201514879159A US 9496356 B2 US9496356 B2 US 9496356B2
- Authority
- US
- United States
- Prior art keywords
- fin
- epitaxial layer
- spacer
- void
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title description 4
- 125000006850 spacer group Chemical group 0.000 claims abstract description 39
- 230000005669 field effect Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000011800 void material Substances 0.000 claims description 16
- 230000003071 parasitic effect Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 38
- 230000008569 process Effects 0.000 description 23
- 238000000151 deposition Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Definitions
- the present invention relates to fin-based semiconductor devices, and more specifically, to decoupling extension resistance and parasitic capacitance.
- Fin-based semiconductor devices require raised source/drain structures that are fabricated using an epitaxial silicon layer (epi/raised S/D).
- the epi/raised S/D has a drawback of increased parasitic capacitance between the epitaxial layer and the gate.
- the extension resistance becomes the dominant component of total resistance. This extension resistance can be lowered by thickening the epitaxial layer.
- a thicker epitaxial layer has a consequence of a larger capacitor area (increased capacitance).
- a fin field effect transistor (FinFET) device includes a fin formed on a substrate, the fin including a channel region of the device; a spacer and a cap formed over a dummy gate line separating a source and drain of the device; and an epitaxial layer formed over portions of the fin, the epitaxial layer being included between the fin and the spacer.
- FinFET fin field effect transistor
- a method of fabricating a fin field effect transistor (FinFET) device includes forming a fin on a substrate, the fin including a channel region of the device; forming a spacer and a cap over a dummy gate line separating a source and drain of the device; and growing an epitaxial layer over portions of the fin including a region between the fin and the spacer.
- FinFET fin field effect transistor
- FIG. 1 depicts aspects of a field effect transistor device with an epitaxial layer formed according to an embodiment of the invention
- FIG. 2 shows additional aspects of the device shown in FIG. 1 ;
- FIG. 3 is a process flow of a method of forming a void for growth of the epitaxial layer between the fin and the fat spacer and cap according to one embodiment of the invention
- FIG. 4 illustrates the fin structure used to form the device according to embodiments of the invention
- FIG. 5 illustrates the structure resulting from forming the capped dummy gate lines
- FIG. 6 shows a structure that results from forming the spacer and cap layer
- FIG. 7 shows the structure resulting from growing the dummy epitaxial layer
- FIG. 8 illustrates the structure that includes the fat spacer and cap
- FIG. 9 depicts the structure including the void resulting from the embodiment described by the method shown in FIG. 3 ;
- FIG. 10 is a process flow of a method of forming a void for growth of the epitaxial layer between the fin and the fat spacer and cap according to another embodiment of the invention.
- FIG. 11 shows the structure resulting from the deposition of the etch stop and spacing film on the FinFET structure shown in FIG. 4 ;
- FIG. 12 illustrates the structure resulting from formation of the dummy gates lines and gate caps
- FIG. 13 shows the structure that results from forming the spacers
- FIG. 14 shows the structure that results from etching the spacing film
- FIG. 15 depicts the structure including the void according to the embodiment described by the method shown in FIG. 10 .
- epitaxial raised source/drain (epi/raised S/D) regions present a tradeoff challenge because lowering extension resistance by using a thicker epitaxial layer has the unwanted consequence of increasing parasitic capacitance.
- Embodiments of the system and method detailed herein relate to decoupling extension resistance and capacitance so that extension resistance may be lowered without a parasitic capacitance penalty. While the details below relate to an exemplary silicon on insulator (SOI) fin, the descriptions below also pertain to bulk fins, as well. In addition, while embodiments of the invention are described in the context of a finFET, the embodiments detailed below also apply to other device structures such as nanowires, for example.
- SOI silicon on insulator
- FIG. 1 depicts aspects of a field effect transistor device 100 with an epitaxial layer 130 formed according to an embodiment of the invention.
- the device 100 is, for example, a fin-based metal-oxide-semiconductor field-effect transistor (MOSFET) in which one or more fins 110 include a channel between a source and drain. Only a source or drain is depicted in FIG. 1 .
- MOSFET metal-oxide-semiconductor field-effect transistor
- FIG. 1 illustrates, a portion of the fin 110 that has the fat spacer 120 above it is separated from the fat spacer 120 by the epitaxial layer 130 .
- the epitaxial layer 130 may be comprised of silicon germanium (SiGe) doped with boron, for example.
- the inclusion of the epitaxial layer 130 configured in a step pattern as shown, under the fat spacer 120 facilitates a decoupling of the extension resistance and the parasitic capacitance. That is, extension resistance may be lowered without a penalty of increased parasitic capacitance.
- the epitaxial layer 130 is thicker in the extension region 117 than it is at the border of the channel region 115 .
- the extension resistance is determined based on the dimension 122
- the parasitic capacitance is determined based on the dimension 124 . As a result of the dimension 124 being greater than the dimension 122 , both parasitic capacitance and extension resistance may be kept low.
- FIG. 2 shows additional aspects of the device 100 shown in FIG. 1 .
- fins 110 are formed on a substrate formed of, for example, a buried oxide (BOX) 210 layer.
- the extension region 117 of the fin 110 extends to a raised source/drain.
- the dummy gate lines 150 are covered by the fat spacer 120 and a cap 125 .
- the epitaxial layer 130 is shown in a diamond shape around the fins 110 (in the raised source/drain region) in FIG. 2 .
- embodiments of the invention do not limit the epitaxial layer 130 to any particular shape.
- the epitaxial layer 130 extends under the fat spacer 120 (“within void”).
- FIG. 3 is a process flow of a method of forming a void for growth of the epitaxial layer 130 between the fin 110 and the fat spacer 120 according to one embodiment of the invention.
- the process includes beginning with a fin structure 400 ( FIG. 4 ).
- FIG. 4 illustrates the fin structure 400 used to form the device 100 ( FIGS. 1 and 2 ) according to embodiments of the invention.
- the fin structure 400 includes the BOX 210 with patterned silicon fins 110 .
- the process includes forming the dummy gate lines 150 .
- FIG. 5 illustrates the structure 500 resulting from forming the capped dummy gate lines 150 .
- the process at block 320 includes depositing a dummy gate dielectric 140 , depositing a dummy gate electrode layer, planarizing the dummy gate electrode layer, then depositing a cap layer 510 and patterning the cap layer 510 and dummy gate electrode layer to form the dummy gate lines 150 .
- the dummy gate dielectric 140 may be formed by depositing 30 nanometers (nm) of silicon dioxide (SiO 2 ), for example.
- the dummy gate electrode layer that is planarized and patterned to form the dummy gate lines 150 may be an amorphous silicon layer, and the cap layer 510 may be formed from silicon nitride (Si 3 N 4 ).
- the dummy gate lines 150 have self-aligned caps 510 , as shown in FIG. 5 .
- the process shown in FIG. 3 includes forming a spacer 610 and cap 615 layer ( FIG. 6 ) and clearing the sides of the fins 110 .
- FIG. 6 shows a structure 600 that results from forming the spacer 610 and cap 615 layer.
- the spacer 610 and cap 615 may be formed by depositing conformal a nitride (e.g., Si 3 N 4 ) and performing a reactive-ion etch (RIE).
- RIE reactive-ion etch
- the RIE process may be extended to clear the sides of the fins 110 , but, as shown in FIG. 6 , the fins 110 are still coated with the dummy gate dielectric 140 .
- FIG. 3 includes stripping exposed dummy gate dielectric 140 and then growing a dummy epitaxial layer 710 ( FIG. 7 ).
- FIG. 7 shows the structure 700 resulting from growing the dummy epitaxial layer 710 .
- the dummy epitaxial layer 710 may be a thin undoped high-germanium layer.
- the dummy epitaxial layer 710 may be comprised of any material that can be etched selectively with respect to the fin 110 material, the dummy gate dielectric 140 , the spacer 610 , and the cap 615 .
- FIG. 7 shows the structure 700 resulting from growing the dummy epitaxial layer 710 .
- the dummy epitaxial layer 710 may be a thin undoped high-germanium layer.
- the dummy epitaxial layer 710 may be comprised of any material that can be etched selectively with respect to the fin 110 material, the dummy gate dielectric 140 , the spacer 610 , and the cap 615 .
- forming the fat spacer 120 and cap 125 layer may include depositing an additional conformal nitride (Si 3 N 4 ) layer to fatten the spacer 610 and cap 615 ( FIGS. 6 and 7 ) and performing RIE.
- FIG. 8 illustrates the structure 800 that includes the fat spacer 120 and cap 125 .
- the dummy epitaxial layer 710 is between the fat spacer 120 and the fin 110 (labeled “A”).
- etching the dummy epitaxial layer 710 creates the void 910 in which the epitaxial layer 130 may be grown between the fat spacer 120 and the fin 110 (as shown in FIGS. 1 and 2 , for example).
- FIG. 9 depicts the structure 900 including the void 910 resulting from the embodiment described by the method shown in FIG. 3 at block 360 .
- FIG. 10 is a process flow of a method of forming a void for growth of the epitaxial layer 130 between the fin 110 and the fat spacer 120 according to another embodiment of the invention.
- a fin structure 400 such as the one shown in FIG. 4 indicates that the method shown in FIG. 10 begins with the same process as the method shown in FIG. 3 .
- the process shown in FIG. 10 includes depositing an etch stop 1110 ( FIG. 11 ) and spacing film 1120 ( FIG. 11 ).
- FIG. 11 shows the structure 1100 resulting from the deposition of the etch stop 1110 and spacing film 1120 on the fin structure 400 shown in FIG. 4 .
- the etch stop 1110 many be a high K dielectric (e.g., hafnium oxide, HfO 2 ) and the spacing film 1120 may be an oxide such as silicon dioxide (SiO 2 ), for example. Exemplary thicknesses for the bi-layer oxide may be 2.5 and 3.5 nano meters (nm).
- the process shown in FIG. 10 includes forming dummy gate lines 150 and gate caps 1210 ( FIG. 12 ).
- FIG. 12 illustrates the structure 1200 resulting from formation of the dummy gates lines 150 and gate caps 1210 .
- Amorphous silicon may be deposited and planarized to form the dummy gates lines 150
- silicon nitride (Si 3 N 4 ) may be deposited as the gate caps 1210 . Patterning the deposited films forms the dummy gates lines 150 and the gate caps 1210 .
- the process shown in FIG. 10 includes forming spacers 1310 ( FIG. 13 ). This includes depositing silicon nitride (Si 3 N 4 ) and performing RIE. The process also includes annealing the spacers 1310 or using high-temperatures films to control hydrofluoric acid (HF) etch rate.
- FIG. 13 shows the structure 1300 that results from forming the spacers 1310 .
- the process includes etching the spacing film 1120 exposes the etch stop 1110 .
- FIG. 14 shows the structure 1400 that results from etching the spacing film 1120 .
- FIG. 10 depicts the structure 1500 including the void 1510 according to the embodiment described by the method shown in FIG. 10 .
- Creating the void 1510 includes isotropically pulling back the spacing film 1120 using HF to a specified depth for the epitaxial extension (the growth of the epitaxial layer 130 under the spacer 1310 ) in the area marked “A” in FIG. 14 .
- Creating the void 1510 further includes isotropically etching the etch stop layer 1110 beneath the pulled back spacing film 1120 using Carina etch, for example. Removal of the spacing film 1120 and the etch stop layer 1110 also creates the volumes 1520 . Removal of etch stop layer 1110 enables growth of epitaxial layers on exposed portions of the fins 110 .
- the structures 900 and 1500 including respective voids 910 and 1510 are fabricated by the processes shown in FIG. 3 and FIG. 10 , respectively.
- a standard process may be used to complete fabrication of the device 100 .
- the standard process may include replacement metal gate processing, including post metal dielectric (e.g., SiO 2 ) deposition and planarization, and other processes to form the actual gate stack for the FinFET.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/879,159 US9496356B2 (en) | 2014-08-28 | 2015-10-09 | Under-spacer doping in fin-based semiconductor devices |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/471,573 US9455323B2 (en) | 2014-08-28 | 2014-08-28 | Under-spacer doping in fin-based semiconductor devices |
US14/879,159 US9496356B2 (en) | 2014-08-28 | 2015-10-09 | Under-spacer doping in fin-based semiconductor devices |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/471,573 Division US9455323B2 (en) | 2014-08-28 | 2014-08-28 | Under-spacer doping in fin-based semiconductor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
US20160064501A1 US20160064501A1 (en) | 2016-03-03 |
US9496356B2 true US9496356B2 (en) | 2016-11-15 |
Family
ID=55403472
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/471,573 Expired - Fee Related US9455323B2 (en) | 2014-08-28 | 2014-08-28 | Under-spacer doping in fin-based semiconductor devices |
US14/879,159 Active US9496356B2 (en) | 2014-08-28 | 2015-10-09 | Under-spacer doping in fin-based semiconductor devices |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/471,573 Expired - Fee Related US9455323B2 (en) | 2014-08-28 | 2014-08-28 | Under-spacer doping in fin-based semiconductor devices |
Country Status (1)
Country | Link |
---|---|
US (2) | US9455323B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10833175B2 (en) * | 2015-06-04 | 2020-11-10 | International Business Machines Corporation | Formation of dislocation-free SiGe finFET using porous silicon |
US9887269B2 (en) * | 2015-11-30 | 2018-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-gate device and method of fabrication thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080157208A1 (en) * | 2006-12-29 | 2008-07-03 | Fischer Kevin J | Stressed barrier plug slot contact structure for transistor performance enhancement |
US20130187228A1 (en) * | 2012-01-19 | 2013-07-25 | Globalfoundries Inc. | FinFET Semiconductor Devices with Improved Source/Drain Resistance and Methods of Making Same |
US20130330915A1 (en) * | 2012-06-12 | 2013-12-12 | Bing Hu | Method of making a thin crystalline semiconductor material |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7037818B2 (en) | 2004-08-20 | 2006-05-02 | International Business Machines Corporation | Apparatus and method for staircase raised source/drain structure |
US7018901B1 (en) | 2004-09-29 | 2006-03-28 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device having a strained channel and a heterojunction source/drain |
US7456471B2 (en) | 2006-09-15 | 2008-11-25 | International Business Machines Corporation | Field effect transistor with raised source/drain fin straps |
US7736957B2 (en) | 2007-05-31 | 2010-06-15 | Freescale Semiconductor, Inc. | Method of making a semiconductor device with embedded stressor |
CN101840920B (en) | 2009-12-15 | 2012-05-09 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
US8263451B2 (en) | 2010-02-26 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Epitaxy profile engineering for FinFETs |
US8574970B2 (en) | 2010-09-15 | 2013-11-05 | International Business Machines Corporation | Method of forming an extremely thin semiconductor insulator (ETSOI) FET having a stair-shaped raised source/drain |
US8637359B2 (en) | 2011-06-10 | 2014-01-28 | International Business Machines Corporation | Fin-last replacement metal gate FinFET process |
US8435846B2 (en) | 2011-10-03 | 2013-05-07 | International Business Machines Corporation | Semiconductor devices with raised extensions |
-
2014
- 2014-08-28 US US14/471,573 patent/US9455323B2/en not_active Expired - Fee Related
-
2015
- 2015-10-09 US US14/879,159 patent/US9496356B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080157208A1 (en) * | 2006-12-29 | 2008-07-03 | Fischer Kevin J | Stressed barrier plug slot contact structure for transistor performance enhancement |
US20130187228A1 (en) * | 2012-01-19 | 2013-07-25 | Globalfoundries Inc. | FinFET Semiconductor Devices with Improved Source/Drain Resistance and Methods of Making Same |
US20130330915A1 (en) * | 2012-06-12 | 2013-12-12 | Bing Hu | Method of making a thin crystalline semiconductor material |
Non-Patent Citations (2)
Title |
---|
List of IBM Patents or Patent Applications Treated as Related; (Appendix P), Filed Oct. 9, 2015; 2 pages. |
Veeraraghavan S. Basker et al., "Under-Spacer Doping in Fin-Based Semiconductor Devices", U.S. Appl. No. 14/471,573, filed Aug. 28, 2014. |
Also Published As
Publication number | Publication date |
---|---|
US20160064501A1 (en) | 2016-03-03 |
US9455323B2 (en) | 2016-09-27 |
US20160064527A1 (en) | 2016-03-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9941405B2 (en) | Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the same | |
US8722472B2 (en) | Hybrid CMOS nanowire mesh device and FINFET device | |
US8679902B1 (en) | Stacked nanowire field effect transistor | |
US9490129B2 (en) | Integrated circuits having improved gate structures and methods for fabricating same | |
US9024368B1 (en) | Fin-type transistor structures with extended embedded stress elements and fabrication methods | |
US8709888B2 (en) | Hybrid CMOS nanowire mesh device and PDSOI device | |
US8648330B2 (en) | Nanowire field effect transistors | |
US20150357468A1 (en) | Semiconductor device and method of manufacturing the same | |
US9105742B1 (en) | Dual epitaxial process including spacer adjustment | |
US8969145B2 (en) | Wire-last integration method and structure for III-V nanowire devices | |
WO2011157461A1 (en) | Fabrication of a vertical heterojunction tunnel-fet | |
US9728534B2 (en) | Densely spaced fins for semiconductor fin field effect transistors | |
US20100308409A1 (en) | Finfet structures with fins having stress-inducing caps and methods for fabricating the same | |
JP6173083B2 (en) | Method for manufacturing a field effect semiconductor device | |
US9865508B2 (en) | Method and structure to fabricate closely packed hybrid nanowires at scaled pitch | |
US9496356B2 (en) | Under-spacer doping in fin-based semiconductor devices | |
US20140087526A1 (en) | Multi-gate field effect transistor devices | |
US10243046B2 (en) | Fully depleted silicon-on-insulator device formation | |
US9230802B2 (en) | Transistor(s) with different source/drain channel junction characteristics, and methods of fabrication | |
US20160190302A1 (en) | Soi based finfet with strained source-drain regions | |
US9754969B2 (en) | Dual-material mandrel for epitaxial crystal growth on silicon | |
US20140299919A1 (en) | Semiconductor device and method for manufacturing the same | |
US20210134995A1 (en) | Vertical channel device | |
US20160181363A1 (en) | Mosfet structure and method for manufacturing same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BASKER, VEERARAGHAVAN S.;CHENG, KANGGUO;KHAKIFIROOZ, ALI;AND OTHERS;SIGNING DATES FROM 20140815 TO 20140825;REEL/FRAME:036763/0154 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |