CN102682854A - Storage with redundant circuit and method for providing redundant circuit for storage - Google Patents
Storage with redundant circuit and method for providing redundant circuit for storage Download PDFInfo
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- CN102682854A CN102682854A CN2012101429496A CN201210142949A CN102682854A CN 102682854 A CN102682854 A CN 102682854A CN 2012101429496 A CN2012101429496 A CN 2012101429496A CN 201210142949 A CN201210142949 A CN 201210142949A CN 102682854 A CN102682854 A CN 102682854A
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Abstract
The invention provides a storage with a redundant circuit and a method for providing the redundant circuit for the storage. The storage with the redundant circuit comprises a plurality of storage areas and the redundant circuit, wherein each of the plurality of storage areas is uniformly divided into a plurality of secondary storage areas, all storage units selected by a bit line are positioned in the same secondary storage area, and the redundant circuit is provided with a redundant replacement storage unit the size of which is equal to the size of the secondary storage areas, and the redundant replacement storage unit is used for replacing the secondary storage area where the storage units selected by the bit line are in when the failed bit line exists.
Description
Technical field
The present invention relates to semiconductor design and manufacturing field, more particularly, the present invention relates to a kind of method that has the storage arrangement of redundant circuit and redundant circuit is provided for storage arrangement.
Background technology
Nowadays, semiconductor memory system spare constantly develops towards the direction of high integration and high-capacity storage unit at present.In the storage arrangement design, adopt the method for the out of order storage unit of various replacements to improve chip yield usually as one of most important index of high integration storage arrangement spare.
By the single superfluous and single superfluous storage unit of forming of normal storage of slack storage, the available backup storage unit is replaced out of order storage unit when with convenient normal memory cell discovery fault being arranged as the superfluous redundancy of replacing technology of a kind of Trouble ticket.
That is to say that semiconductor memory system has the redundant circuit that is used to improve the finished product rate.In memory cell array, exist under the situation of defected memory cell, redundant circuit has the function that this defected memory cell is replaced with the redundant storage unit in the spare memory cell array.
In the prior art, general redundant circuit adopts the mode that defected memory cell is replaced with redundant storage unit with specific replacement unit.As shown in Figure 1, schematically show the structural representation of the storage arrangement with redundant circuit of prior art among the figure.Wherein, storage arrangement comprises a plurality of (under situation shown in Figure 1, being x) memory block.Like this; When detecting certain defective bit line; The whole memory block at the selected storage unit of this defective bit line place is by the whole replacement of a redundancy unit R1 in the redundant circuit, and this just requires the big or small m of each memory block to equate with the size of each redundant circuit.And in fact, more often do not have the storage unit of defective to be replaced yet; Therefore, there is serious waste in storage arrangement redundancy of the prior art.
So hope can propose a kind of effective redundancy that can eliminate said waste and improve the utilization factor of redundant circuit.
Summary of the invention
Technical matters to be solved by this invention is to having above-mentioned defective in the prior art, and a kind of storage arrangement that effectively has redundant circuit and method that redundant circuit is provided for storage arrangement of eliminating waste and improving the utilization factor of redundant circuit is provided.
According to a first aspect of the invention, a kind of storage arrangement with redundant circuit is provided, it comprises: a plurality of memory blocks and redundant circuit; Wherein, each of said a plurality of memory blocks all is divided into a plurality of secondary storage district equably, and wherein, selected all storage unit of single bit line are arranged in same secondary storage district; Wherein, said redundant circuit has the redundancy replacement storage unit that size equals the secondary storage district, and said redundancy replacement storage unit is used for the secondary storage district at the selected storage unit of replacement bit line place when defective bit line occurring.
According to a second aspect of the invention, a kind of storage arrangement with redundant circuit is provided, it comprises: a plurality of memory blocks and redundant circuit; Wherein, Each of said a plurality of memory blocks all is divided into a plurality of minimum memory district equably; And wherein, selected all storage unit of single bit line are arranged in same minimum memory district, and single minimum memory district only comprises selected all storage unit of single bit line; And wherein, said redundant circuit has the redundancy replacement storage unit that size equals the minimum memory district, and said redundancy replacement storage unit is used for the minimum memory district at the selected storage unit of replacement bit line place when defective bit line occurring.
According to a third aspect of the invention we; A kind of method that redundant circuit is provided for storage arrangement is provided; It comprises: each of a plurality of memory blocks of storage arrangement is divided into a plurality of secondary storage district equably; Wherein, selected all storage unit of single bit line are arranged in same secondary storage district; Make said redundant circuit have the redundancy replacement storage unit that size equals the secondary storage district; When defective bit line occurring, utilize the secondary storage district at the selected storage unit of said redundancy replacement storage unit replacement bit line place.
Preferably; In the above-mentioned method that redundant circuit is provided for storage arrangement; When the defective bit line that occurs appears at the edge between first level memory block and the second subprime memory block, utilize two redundancy replacement storage unit to come to replace respectively said first level memory block and said second subprime memory block.
According to a forth aspect of the invention; A kind of method that redundant circuit is provided for storage arrangement is provided; It comprises: each of a plurality of memory blocks of storage arrangement is divided into a plurality of minimum memory district equably; Wherein, selected all storage unit of single bit line are arranged in same minimum memory district, and single minimum memory district only comprises selected all storage unit of single bit line; Make said redundant circuit have the redundancy replacement storage unit that size equals the minimum memory district; When defective bit line occurring, utilize the minimum memory district at the selected storage unit of said redundancy replacement storage unit replacement bit line place.
Preferably; In the above-mentioned method that redundant circuit is provided for storage arrangement; When defective bit line occurring, utilize three redundancy replacement storage unit to come to replace respectively defective bit line selected minimum memory district and two minimized memories adjacent with the selected minimum memory of defective bit line district.
Description of drawings
In conjunction with accompanying drawing, and, will more easily more complete understanding be arranged and more easily understand its attendant advantages and characteristic the present invention through with reference to following detailed, wherein:
Fig. 1 schematically shows the structural representation according to the storage arrangement with redundant circuit of prior art.
Fig. 2 schematically shows the structural representation according to the storage arrangement with redundant circuit of the embodiment of the invention.
Fig. 3 schematically shows the structural representation according to the storage arrangement with redundant circuit of the embodiment of the invention.
Fig. 4 schematically shows the detailed structure synoptic diagram of the storage arrangement with redundant circuit according to a second embodiment of the present invention.
What Fig. 5 schematically showed a third embodiment in accordance with the invention provides the detailed structure synoptic diagram of the method for redundant circuit for storage arrangement.
What Fig. 6 schematically showed a fourth embodiment in accordance with the invention provides the detailed structure synoptic diagram of the method for redundant circuit for storage arrangement.
Need to prove that accompanying drawing is used to explain the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure possibly not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear more and understandable, content of the present invention is described in detail below in conjunction with specific embodiment and accompanying drawing.
< first embodiment >
Fig. 2 and Fig. 3 schematically show the structural representation according to the storage arrangement with redundant circuit of the embodiment of the invention.
As shown in Figure 2, different with prior art is that in embodiments of the present invention, size is the memory block 1,2,3 of first size m originally ... Each of x all is divided into size and is the secondary storage district of n.
Thus, the storage arrangement with redundant circuit according to first embodiment of the invention can comprise a plurality of memory blocks and redundant circuit; Wherein, each of said a plurality of memory blocks all is divided into a plurality of secondary storage district equably, and wherein, selected all storage unit of single bit line are arranged in same secondary storage district; Wherein, said redundant circuit has the redundancy replacement storage unit that size equals the secondary storage district, and said redundancy replacement storage unit is used for the secondary storage district at the selected storage unit of replacement bit line place when defective bit line occurring.
Like this, as shown in Figure 3, the size of each redundancy replacement storage unit R2 of redundant circuit is similarly the second size n.Like this, when detecting certain defective bit line, the whole secondary storage district at the selected storage unit of this defective bit line place is the whole replacement of a redundancy replacement storage unit R2 of the second size n by the size in the redundant circuit.
Thus, according to said method,, saved the storage space of (m-n) size for a defective bit line.
Wherein, first size m is the integer greater than 1 divided by the result of the second size n.
< second embodiment >
Fig. 4 schematically shows the detailed structure synoptic diagram of the storage arrangement with redundant circuit according to another embodiment of the present invention.
Storage arrangement for by original size being first size m is divided the secondary storage district that forms, and can also further divide it.Preferably, it is divided into has the selected storage arrangement size of single bit line the minimum memory district of (below be called minimum dimension k).That is, different minimum memory district is selected by corresponding lines not.
Thus, the storage arrangement with redundant circuit according to second embodiment of the invention can comprise a plurality of memory blocks and redundant circuit; Wherein, Each of said a plurality of memory blocks all is divided into a plurality of minimum memory district equably; And wherein, selected all storage unit of single bit line are arranged in same minimum memory district, and single minimum memory district only comprises selected all storage unit of single bit line; And wherein, said redundant circuit has the redundancy replacement storage unit that size equals the minimum memory district, and said redundancy replacement storage unit is used for the minimum memory district at the selected storage unit of replacement bit line place when defective bit line occurring.
Like this, when detecting certain defective bit line, the whole minimum memory district at the selected storage unit of this defective bit line place is the whole replacement of a redundancy replacement storage unit of minimum dimension k by the size in the redundant circuit.
Thus, according to said method,,, saved the storage space of (m-k) size for a defective bit line with respect to prior art.
Wherein, the second size n is the integer greater than 1 divided by the result of minimum dimension k.
< the 3rd embodiment >
At first, describe with reference to the 3rd embodiment shown in Figure 5 and the method for redundant circuit is provided for storage arrangement according to the first embodiment of the present invention.The storage arrangement with redundant circuit among the 4th embodiment is identical with first embodiment.
Providing for storage arrangement in the method for redundant circuit of the 3rd embodiment; Different with first embodiment is; When the bit line of defectiveness appears at two edges between the secondary storage district, utilize two redundancy replacement storage unit R2 to come to replace respectively this two secondary storage districts.
For example, as shown in Figure 5, when the bit line BL1 of defectiveness appears at the edge between first level memory block A1 and the second subprime memory block A2, utilize two redundancy replacement storage unit R2 to come to replace respectively first level memory block A1 and second subprime memory block A2.
Thus, the reliability of the storage arrangement after can guaranteeing reliably to replace.
< the 3rd embodiment >
At first, with reference to the 4th embodiment shown in Figure 6 describe according to a second embodiment of the present invention the method for redundant circuit is provided for storage arrangement.The storage arrangement with redundant circuit among the 4th embodiment is identical with first embodiment.
Providing for storage arrangement in the method for redundant circuit of the 4th embodiment; Different with first embodiment is; When the bit line of defectiveness appears in certain minimum memory district, utilize three redundancy replacement storage unit to come to replace respectively defective bit line selected minimum memory district and two minimized memories adjacent with the selected minimum memory of defective bit line district.
For example, as shown in Figure 6, when B1 place, the present first minimum memory district of the bit line BL2 of defectiveness, utilize three redundancy replacement storage unit to come to replace respectively the first minimum memory district B1, the second minimum memory district B2 and the 3rd minimum memory district B3.
Thus, the reliability of the storage arrangement after can guaranteeing reliably to replace.
It is understandable that though the present invention with the preferred embodiment disclosure as above, yet the foregoing description is not in order to limit the present invention.For any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the technology contents of above-mentioned announcement capable of using is made many possible changes and modification to technical scheme of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (6)
1. the storage arrangement with redundant circuit is characterized in that comprising: a plurality of memory blocks and redundant circuit; Wherein, each of said a plurality of memory blocks all is divided into a plurality of secondary storage district equably, and wherein, selected all storage unit of single bit line are arranged in same secondary storage district; Wherein, said redundant circuit has the redundancy replacement storage unit that size equals the secondary storage district, and said redundancy replacement storage unit is used for the secondary storage district at the selected storage unit of replacement bit line place when defective bit line occurring.
2. the storage arrangement with redundant circuit is characterized in that comprising: a plurality of memory blocks and redundant circuit; Wherein, Each of said a plurality of memory blocks all is divided into a plurality of minimum memory district equably; And wherein, selected all storage unit of single bit line are arranged in same minimum memory district, and single minimum memory district only comprises selected all storage unit of single bit line; And wherein, said redundant circuit has the redundancy replacement storage unit that size equals the minimum memory district, and said redundancy replacement storage unit is used for the minimum memory district at the selected storage unit of replacement bit line place when defective bit line occurring.
3. one kind for storage arrangement provides the method for redundant circuit, it is characterized in that comprising:
Each of a plurality of memory blocks of storage arrangement is divided into a plurality of secondary storage district equably, and wherein, selected all storage unit of single bit line are arranged in same secondary storage district;
Make said redundant circuit have the redundancy replacement storage unit that size equals the secondary storage district;
When defective bit line occurring, utilize the secondary storage district at the selected storage unit of said redundancy replacement storage unit replacement bit line place.
4. the method that redundant circuit is provided for storage arrangement according to claim 3; It is characterized in that; When the defective bit line that occurs appears at the edge between first level memory block and the second subprime memory block, utilize two redundancy replacement storage unit to come to replace respectively said first level memory block and said second subprime memory block.
5. one kind for storage arrangement provides the method for redundant circuit, it is characterized in that comprising:
Each of a plurality of memory blocks of storage arrangement is divided into a plurality of minimum memory district equably; Wherein, Selected all storage unit of single bit line are arranged in same minimum memory district, and single minimum memory district only comprises selected all storage unit of single bit line;
Make said redundant circuit have the redundancy replacement storage unit that size equals the minimum memory district;
When defective bit line occurring, utilize the minimum memory district at the selected storage unit of said redundancy replacement storage unit replacement bit line place.
6. the method that redundant circuit is provided for storage arrangement according to claim 5; It is characterized in that; When defective bit line occurring, utilize three redundancy replacement storage unit to come to replace respectively defective bit line selected minimum memory district and two minimized memories adjacent with the selected minimum memory of defective bit line district.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2012101429496A CN102682854A (en) | 2012-05-09 | 2012-05-09 | Storage with redundant circuit and method for providing redundant circuit for storage |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012101429496A CN102682854A (en) | 2012-05-09 | 2012-05-09 | Storage with redundant circuit and method for providing redundant circuit for storage |
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| CN102682854A true CN102682854A (en) | 2012-09-19 |
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| CN2012101429496A Pending CN102682854A (en) | 2012-05-09 | 2012-05-09 | Storage with redundant circuit and method for providing redundant circuit for storage |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021468A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | Error message recording method and redundancy substituting method for memory |
| CN103970629A (en) * | 2014-06-05 | 2014-08-06 | 俞泽生 | Cooperation method of equipment with redundant circuit |
| CN116612805A (en) * | 2023-07-19 | 2023-08-18 | 芯天下技术股份有限公司 | Redundancy replacement method and device for flash, register and memory chip |
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| US4908798A (en) * | 1987-07-20 | 1990-03-13 | Nec Corporation | Semiconductor memory device with memory cell arrays and a redundant memory cell array associated with a small number of write-in and sense amplifying circuits |
| JPH09231789A (en) * | 1996-02-21 | 1997-09-05 | Sony Corp | Semiconductor memory device |
| US20020126550A1 (en) * | 2001-03-09 | 2002-09-12 | Kenichiro Sugio | Redundant memory circuit for analog semiconductor memory |
| CN1823392A (en) * | 2003-07-15 | 2006-08-23 | 尔必达存储器株式会社 | Semiconductor storage device |
| CN102157206A (en) * | 2011-01-17 | 2011-08-17 | 上海宏力半导体制造有限公司 | Memory with redundant circuit and method for providing redundant circuit for memory |
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2012
- 2012-05-09 CN CN2012101429496A patent/CN102682854A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4908798A (en) * | 1987-07-20 | 1990-03-13 | Nec Corporation | Semiconductor memory device with memory cell arrays and a redundant memory cell array associated with a small number of write-in and sense amplifying circuits |
| JPH09231789A (en) * | 1996-02-21 | 1997-09-05 | Sony Corp | Semiconductor memory device |
| US20020126550A1 (en) * | 2001-03-09 | 2002-09-12 | Kenichiro Sugio | Redundant memory circuit for analog semiconductor memory |
| CN1823392A (en) * | 2003-07-15 | 2006-08-23 | 尔必达存储器株式会社 | Semiconductor storage device |
| CN102157206A (en) * | 2011-01-17 | 2011-08-17 | 上海宏力半导体制造有限公司 | Memory with redundant circuit and method for providing redundant circuit for memory |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021468A (en) * | 2012-12-21 | 2013-04-03 | 上海宏力半导体制造有限公司 | Error message recording method and redundancy substituting method for memory |
| CN103970629A (en) * | 2014-06-05 | 2014-08-06 | 俞泽生 | Cooperation method of equipment with redundant circuit |
| CN116612805A (en) * | 2023-07-19 | 2023-08-18 | 芯天下技术股份有限公司 | Redundancy replacement method and device for flash, register and memory chip |
| CN116612805B (en) * | 2023-07-19 | 2023-11-10 | 芯天下技术股份有限公司 | Redundancy replacement method and device for flash, register and memory chip |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140425 |
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Effective date of registration: 20140425 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120919 |
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