CN102682684B - Method for measuring quality of dynamic image of liquid crystal display - Google Patents

Abstract

The invention discloses a method for measuring the quality of a dynamic image of a liquid crystal display. The method comprises an upper machine control flow and a lower machine image generation and data acquisition operating flow, wherein the upper machine control flow is used for defining a display image format, selecting a clock updating scheme, setting graph driving configuration, determining a data acquisition mode and computing the quality parameters of the dynamic image; the lower machine image generation and data acquisition operating flow is used for receiving and converting operating data, generating and controlling a synchronizing signal, generating and configuring a test graph, selecting and setting display drive, and acquiring and transmitting characteristic data; and transmission of measuring data in an inter-integrated circuit (I2C) bus mode and transmission of transient response characteristic data through a universal serial bus (USB) interface are performed between the upper machine control flow and the lower machine image generation and data acquisition operating flow. The method provided by the invention is used for comprehensively identifying the dynamic characteristic of the liquid crystal display and can meet measuring requirements of different types of liquid crystal displays.

Description

The measuring method of LCD device dynamic image quality

Technical field

The present invention relates to the measuring method of liquid crystal display display quality, relate in particular to a kind of measuring method of LCD device dynamic image quality.

Background technology

Maintenance pattern based on liquid crystal display and the tracking characteristic of eye-observation, the measuring method of dynamic image quality has two kinds at present: (1) direct method of measurement; (2) indirect method of measurement.

The direct method of measurement comprises high speed camera method and follows the trail of camera method, although they can effectively be simulated human eye and smoothly follow the trail of dynamic image, build such measurement mechanism and often because of the highly difficult of the high precision of Machinery electricity matching, the high price of equipment configuration and tracking process, be difficult to realize.

The indirect method of measurement be the transient state luminosity response characteristics measuring be foundation, adopt the integral process in mathematical method simulation human eye smooth pursuit movement image and luminosity response one frame time, calculate dynamic image mass parameter.Although realize this measuring method without complicated optics utility appliance and high-precision Machinery electricity matching, it is measuring the aspects such as signal to noise ratio (S/N ratio), mathematical simulation precision, Automatic survey, assessment be comprehensive and can not meet the requirement of comprehensive checking dynamic image quality.

Summary of the invention

Goal of the invention: in order to overcome the deficiencies in the prior art, the invention provides a kind of measuring method of the LCD device dynamic image quality based on mathematical simulation method, it verifies the dynamic image quality of liquid crystal display comprehensively by Blurred edge time measurement procedure, Motion picture response time measurement procedure, dynamic modulation transfer function measurement procedure.

Technical scheme: for achieving the above object, the technical solution used in the present invention is:

The measuring method of LCD device dynamic image quality, comprises that PC control flow process and slave computer image occur and data acquisition operational scheme; Described PC control flow process is used for defining demonstration picture format, selection clock update scheme, sets graphics driver configuration, specified data drainage pattern, calculates dynamic image mass parameter; Described slave computer image occurs and data acquisition operational scheme is used for service data reception and conversion, synchronizing signal generation and control, test patterns generation and configuration, display driver selection and setting, performance data collection and transmission, and with digital visual interface DVI, low-voltage differential signal LVDS interface or Video Graphics Array VGA interface driver display screen.

Preferably, between described PC control flow process and the generation of slave computer image and data acquisition operational scheme, pass through I ²c bus mode transmission measurement data, USB interface transmission transient response characteristic data.

Specifically, described PC control flow process complete measuring process 1) clock scheme, 2) manual measurement, 3) automatically measure and 4) sequence measuring four parts, the execution step of each several part is as follows:

1) clock scheme

100). select display resolution: a). resolution edit box Resolution selects one to set resolution, and refresh rate Refresh Rate selects 50H _z, 60H _z, 75H _z, 100H _zor 120H _z, synthetic image format parameter in total pixel HTOT that is expert at, the synchronous pixel HSY of row, row back porch pixel HBP, row display pixel HAC, the total pixel VTOT of frame, frame synchronization pixel VSY, frame back porch pixel VBP, frame display pixel VAC edit box; B). while selecting other resolution, in HTOT, HSY, HBP, HAC, VTOT, VSY, VBP, VAC edit box, show blank, the picture format parameter that manually input display setting software generates;

101). select graphics proportion: a). in dimension of picture edit box Block Size, generate and meet block pattern ratio data Hsta, Hend, Vsta, the Vend that sets resolution; B). while selecting other resolution, in Block Size edit box, show blank, manually input Hsta, Hend, Vsta, Vend;

102). calculate list/bis-pixel clock frequency: a). as digital modeling edit box Pixel Mode, selecting at 0 o'clock is single pixel driver, and the data in HTOT edit box are constant, and it is two pixel drivers that Pixel Mode selects at 1 o'clock, and the data in HTOT edit box are except 2; B) .HTOT=HAC+HFP+HSY+HBP, HFP is row crop pixel, VTOT=VAC+VFP+VSY+VBP, VFP is frame crop pixel, clock frequency is f _cLK=HTOT * VTOT * F _re, F _reit is display refresh rates; C). at frequency edit box f _cLKmiddle generation output clock frequency;

103). calculate output frequency: by formula calculate output frequency, f _rEFfor reference frequency, N _ffor feedback division coefficient, N _rfor with reference to divide ratio, N _pfor secondary divide ratio, N _fspan is 1 ~ 2047, wherein can not value 10,11,12,13,14,15,19,20,21,22,23,28,29,30,31,37,38,39,46,47,55, and N _rspan is 1 ~ 255, N _pvalue is 1,2,3,4,5,6,8,9,10,12,15,16,18,20,25,50;

104). calculated rate error: by formula Δ f _err=| f _cLK-f ' _cLK| calculated rate error, Δ f _errfor frequency absolute error, computation process: interior loop is to set N _f, N _r, at N _pin span, calculate Δ f _err, middle level circulation is to set N _f, successively at N _p, N _rin span, calculate Δ f _err, outer circulation is successively at N _p, N _r, N _fin span, calculate Δ f _err, all Δ f after three layers of circulation _errbe less than 0.001 f ' _cLK, its divide ratio N _p, N _r, N _fall enter solution list;

105). generated clock data: an optional scheme in solution list, generates 16 byte clock datas that meet this scheme in clock data edit box CLK_Data;

106). start resolution update: a). with I ²c bus mode transmits 16 byte clock datas in CLK_Data edit box to the clock data buffer area Xdata[rnum of on-site programmable gate array FPGA in pictcure generator]; B). with I ²c bus mode transfer step 100) data that generate are to the global buffer register fullregbuf[I of FPGA ²cBit..0], data length is 89; C). with I ²c bus mode transfer step 101) data that generate are to the global buffer register fullregbuf[I of FPGA ²cBit..0], data length is 44;

2) manual measurement

200). data collecting card setting: a). create an analog acquisition passage Physical Channel and collection voltage range Maximum Value/Minimum Value is set; B). configuration sampling pattern Finite Samples, sampling rate Sample Rate and sampling number Samples per Time; C). configure trigger passage Start Trigger Source and triggering edge Start Edge, d). configuration stops trigger pip pattern Reference Trigger Source and trigger source Reference Edge;

201). screen drives and arranges: a). and select DVI, LVDS or VGA to drive interface; B). select red R, one of green G, blue B, or R, G, B select entirely;

202). transient state saltus step arranges: a). selected two saltus step grade Level1, Level2 in 0 ~ 255 GTG; B). take a frame 16.7ms as every grade of gray scale residence time T1 of unit setting, T2, T3;

203). measure setup: a). select to measure in real time Real-Time or average measurement Average; B). set average measurement number of times Average Times, Average Times=N is less than or equal to 40; C). select the storing path of the image data Excel file of generation automatically;

204). measure and start: a). with I ²c bus mode transmits respectively 2 type of drive data, 3 looks and selects data, 1 bit pattern categorical data, 48 bit pattern luma data, 24 GTG residence time data to the fullregbuf[I of FPGA ²cBit..0]; B). through USB interface, start analog acquisition data procedures Start Task and read the sampled data Read property Node of PC data buffer; C). in the oscillograph of interface, show one in real time or the transient response characteristic Y of multiple averaging ₀(t), Y ₀that voltage, t are the time;

205). calculation of parameter: a). use N average image data to measure noise to eliminate; B). 10% ~ 90% time of definition collection waveform rising edge is that 90% ~ 10% time of liquid crystal response rise time LCRT-rising time, negative edge is liquid crystal response LCRT-falling fall time time; C). according to at transient response curve Y ₀(t) the moving window integral result of previous frame time width, calculates moving image response curve MPRC, wherein τ=-x _pit _f/ v, x _piscreen coordinate, T _fthat frame period, v are block pattern movement velocitys; D). 10% ~ 90% time of definition MPRC rising edge is that 90% ~ 10% time of fuzzy edge rise time BET-rising time, negative edge is fuzzy edge BET-falling fall time time;

3) automatically measure

300). repeating step 200), step 201) in a) and b), step 202) in b), step 203) in b) and c);

301). setting grey exponent number Gray Numbers is 7 or 9;

302). according to Gray Numbers, at default GTG, set 7 or 9 regulation GTGs of automatic generation in form Default Gray Setting;

303). to measure and start: a). automatic sequence is selected two saltus step GTGs in Default Gray Setting; B). repeating step 204) in a), b) and c), in the oscillograph of interface, show that gang is average according to N time m=N _g(N _g+ 1) for GTG combination sum, in 0 ~ 255 gray-scale areas, be divided into N _ggreyscale level, is generally 7 or 9, and adjacent two level spacings are identical;

304). calculation of parameter: a). repeating step 205); B). according to the relational expression EBET=BET/ (0.9-0.1) between Blurred edge time BET and extend blurred edge time EBET, the mean value calculation under Motion picture response time MPRT combines according to different GTGs, i, j=1,2,3....N;

4) sequence measuring

400). repeating step 200), step 201) in a) and b), step 203) in c);

401). measure setup: a). set the space periodic T of the sinusoidal figure of test _s, T _scorresponding value 2,4,6,8,12,16,24,32,48,64 in 0 ~ 9 scope; B). setting the sinusoidal figure movement velocity v of test is 4 or 8; C). set sinusoidal figure offset pointer Index, when the value of v=4 or 8, Index is 0,1,2,3 or 0,1,2,3,4,5,6,7;

402). measure and start: a). with I ²c bus mode transmits 9 bit test sequence data block lengths, 4 bit pattern space periodic data, 3 bit pattern angular movement speed data, 3 bit pattern offset pointer data to the fullregbuf[I of FPGA ²cBit..0]; B) .3 bit pattern offset pointer data are in step 401) in c) automatically increase progressively in the scope set; C). repeating step 204) in b); D). in the oscillograph of interface, show v bar response family curve i=0,1 ..., v-1, that voltage, t are the time;

403). calculation of parameter: a). according to the voltage distribution curve that calculating perceives locus x be take the time in frame period as unit with the pixel cell unit of being of a size of, time t; B). according to step 401), when voltage distribution curve is Sine distribution pattern Y ^*(x), time, calculate dynamic modulation transfer function $\mathrm{DMTF}(v,f)=\frac{C^{\′}(v,f)}{C},$ $C=\frac{Y_{\max }-Y_{\min }}{Y_{\max }+Y_{\min }}$ Sine distribution pattern Y ^*(x) contrast, Y _maxmaximum voltage, Y _minbe minimum voltage, C ' is Sine distribution pattern Y ' contrast (x), y ^*(x) spatial frequency.

Specifically, described slave computer image occurs and data acquisition operational scheme complete measuring process 5) clock upgrades, 6) figure configuration, 7) synchro control and 8) data acquisition four parts, the execution step of each several part is as follows:

5) clock upgrades

500). data receiver buffer memory: a) .I ²c data reception module I ²c_expander serial received step 106) data that a) pass down in, and be converted to 8 bit parallel data; B) .I ²c_expander send the Xdata[rnum of parallel data to clock data receiver module R_FT245BM];

501). Data Update is prepared: a) .R_FT245BM puts reset terminal reset=" 0 ", and the reset terminal reset=" 0 " of clock data writing module W_FS6370 forbids that W_FS6370 starts; B). put the eeprom address of clock chip FS6370 to the address of devices output terminal raddr[7..0 of R_FT245BM]; C). put the register first address of FS6370 to register address output terminal addr[7..0];

502). Data Update starts: a) .R_FT245BM puts and writes control output end wr=" 1 ", and W_FS6370 writes control input end wr=" 1 ", W_FS6370 write operation; B) .R_FT245BM puts reset=" 1 ", the reset=of W_FS6370 " 1 ", and W_FS6370 starts; C) .R_FT245BM extracts Xdata[rnum successively] in clock data to data output end rdata[7..0]; D) .R_FT245BM increases progressively register address 00H ~ 0FH to addr[7..0 of FS6370];

503). data write transmission: a). according to step 501) in b) and c), step 502) in c) and d), the address of devices input end raddr[7..0 of W_FS6370] obtain eeprom address, the register address input end addr[7..0 of FS6370] obtain register address, the data input pin data[7..0 of FS6370] obtain rdata[7..0] data; B) .W_FS6370 puts pattern output terminal mode=" 0 ", and FS6370 is programming mode; C) .W_FS6370 puts power down control output end pd=" 1 ", the FS6370 write operation that powers on; D) the output terminal of clock scl=" 1 " of .W_FS6370, serial data output terminal sda=" 1 " become sda=" 0 ", the I of FS6370 ²byte data transmission time sequence of C bus starts; E) .W_FS6370 send raddr[7..0] address to sda, order send addr[7..0] address to sda, send data[7..0 successively] data to sda; F) scl=of .W_FS6370 " 1 ", sda=" 0 " become sda=" 1 ", the I of FS6370 ²byte data transmission time sequence of C bus finishes;

504). data write end: a) .16 byte clock data writes FS6370 and finish, and R_FT245BM puts the wr=" 0 " of wr=" 0 ", W_FS6370, and W_FS6370 puts mode=" 1 ", and FS6370 is operational mode; B) .W_FS6370 puts pd=" 0 ", puts pd=" 1 " again, after FS6370 power down, powers on again, and in the EEPROM of FS6370,16 byte clock datas are called in control register, the image source global clock that FS6370 output is upgraded;

6) figure configuration

600) .I ²c data receiver: a) .I ²c_expander serial received step 106) data that the b in) and c) pass down; B) .I ²c_expander serial received step 204) in a), step 402) in the data that a) pass down; C) .I ²c_expander changes serial data and is cached in the fullregbuf[I in image generation module fran_pg after into 8 bit parallel data ²cBit..0];

601). resolution definition: according to step 600) in a) and c), fran_pg makes picture format Parameter H AC[10..0]=HAC, VAC[10..0]=VAC, HSY[10..0]=HSY, VSY[10..0]=VSY, HBP[10..0]=HBP, VBP[10..0]=VBP, HTOT[11..0]=HTOT, VTOT[10..0]=VTOT;

602). type of drive is selected: a). according to step 600) in b) and c), fran_pg assignment three looks enable Renab/Genab/Benab and drive to select lvds_dvi_vga_sel[1..0]; B). according to Renab/Genab/Benab, fran_pg enables figure output Red_out[7..0]/Green_out[7..0]/Blue_out[7..0]; C). drive handover module L_D_V_converter from fran_pg, to obtain lvds_dvi_vga_sel[1..0] and Red_out[7..0]/Green_out[7..0]/Blue_out[7..0], conversion and selection meet the interface output output_r_pg[7..0 of LVDS, DVI or VGA type of drive]/output_g_pg[7..0]/output_b_pg[7..0];

603). block pattern size is set: a). according to step 600) in a) and c), the block pattern module varloadblocks in fran_pg establishes the screen position h_sta[10..0 on 4 limits of figure]=Hsta, h_end[10..0]=Hend, v_sta[10..0]=Vsta, v_end[10..0]=Vend; B) .varloadblocks order is at h_sta[10..0], h_end[10..0], v_sta[10..0], v_end[10..0] screen region in generation level, vertical output henable, venable;

604). block pattern transient state is set: a). according to step 600) in b) and c), fran_pg assignment transient state residence time time0, time1, time2, time3, wherein time0=6 is the default residence time, and time1, time2, time3 are the saltus step residence time; B). according to step 600) in b) and c), fran_pg assignment three look GTG red_in1/green_in1/blue_in1, red_in2/green_in2/blue_in2; C) the transient state saltus step module theserial_3L in .fran_pg obtains time0, time1, time2, time3, red_in1/green_in1/blue_in1, red_in2/green_in2/blue_in2 from fran_pg; D) .theserial_3L is set in the GTG output Red_3L_out[7..0 during time0, time1, time2, time3]/Green_3L_out[7..0]/Blue_3L_out[7..0] equal 0, red_in1/green_in1/blue_in1, red_in2/green_in2/blue_in2, red_in1/green_in1/blue_in1; E) .theserial_3L, at time1 initial time, produces and triggers output trigger_3L_out;

605). sinusoidal figure sequence loads: a). according to step 600) in b) and c), fran_pg assignment data block sequence length L=data_length[8..0], data block address Ts=main_addr[3..0], figure movement velocity v=Speed[4..0], map migration amount pointer Index=Index[4..0]; B) the sinusoidal figure module Sine_pattern in .fran_pg obtains data_length[8..0 from fran_pg], main_addr[3..0], Speed[4..0], Index[4..0]; C). according to L, T _s, v, Index, Sine_pattern reads the gray scale sequence data in sinusoidal figure ROM (read-only memory) sinewave_rom, produces sequence GTG output Red_sine_out[7..0]/Green_sine_out[7..0]/Blue_sine_out[7..0]; D) .sinewave_rom establishes every v gray scale sequence and repeats once, along with Index increases progressively automatically from 0 to v-1, loads the different gray scale sequences of v kind; E) .Sine_pattern establishes L and count down to data_length[8..0]-2 o'clock, produce and trigger output trlgger_sine_out;

606). test patterns generation: a). according to step 600) in b) and c), fran_pg obtains pattern classes data pattern, selects to generate square saltus step figure or sinusoidal sequence figure; B). according to step 603) in b), step 604) in d), fran_pg generates square saltus step figure, according to step 602) in b) mode export; C). according to step 603) in b), step 605) in c) and d), fran_pg generates sinusoidal sequence figure, according to step 602) and in b) mode export; D). according to step 604) in e), step 605) in e), fran_pg produces resolution chart and triggers output trigger_out;

7) synchro control

700). frame-synchronizing impulse generates: according to step 601), linage-counter in fran_pg is from h_counter.q[10..0]=HTOT-3 is to h_counter.q[10..0]=HSY-3, horizontal synchronizing pulse HSync_out generates, frame counter in fran_pg is from v_counter.q[10..0]=VTOT is to v_counter.q[10..0]=VSY, frame-synchronizing impulse VSync_out generates;

701). blanking pulse generates: a). according to step 601), h_counter.q[10..0]=HSY-3+HBP-4+HAC, horizontal blanking impulse nblankh_art starts, h_counter.q[10..0]=HSY-3+HBP-4, horizontal blanking impulse nblankh_art finishes; B). according to step 601), v_counter.q[10..0]=VSY+VBP+VAC, frame blanking impulse nblankv_art starts, v_counter.q[10..0]=VSY+VBP, frame blanking impulse nblankv_art finishes; C). according to nblankh_art, nblankv_art, generate composite blanking pulse nblank_art, after frequency division, produce composite blanking pulse output NBlank_out;

8) data acquisition

800). block pattern transient data gathers: a). data collecting card is according to step 200) in c) the digital I/O port receiving step 604 set) and in e), step 606) in d) the trigger collection signal that produces; B). according to trigger pip, data collecting card is according to step 200) in a) regulation analog input mouth start to gather transient data; C). according to step 200) in b), data collecting card completes the data acquisition in a sampling period automatically, and repeats the executing data sampling period; D). through USB interface, transmit image data;

801). sinusoidal figure transient data gathers: a). data collecting card is according to step 200) in c) the digital I/O port receiving step 605 set) and in e), step 606) in d) the trigger collection signal that produces; B). repeating step 800). in b); C). according to step 200) in b), data collecting card completes the data acquisition in a sampling period automatically; D). according to step 605) in d), data collecting card automatically performs the data acquisition in v kind sampling period; E). repeating step 800) in d).

Beneficial effect: the measuring method of LCD device dynamic image quality provided by the invention, be a kind of method of comprehensive checking liquid crystal display dynamic perfromance, it is from the dynamic perfromance of Blurred edge time, Motion picture response time, three aspect comprehensive evaluation liquid crystal display of dynamic modulation transfer function; The start trigger signal data acquisition producing while using image to generate, with the accurate timing of multi collect, realizes multiple averaging image data, eliminates and measures noise, has improved the precision of data acquisition and calculation of parameter; Realized the robotization of measure setup, clock renewal, image generation and data acquisition, whole measuring process is without human intervention; In multiple interfaces modes such as DVI, LVDS, VGA, drive liquid crystal display, meet the measurement demand of variety classes liquid crystal display.

Accompanying drawing explanation

Fig. 1 is PC control process flow diagram;

Fig. 2 is that slave computer image occurs and data acquisition operational flow diagram.

Embodiment

Below in conjunction with accompanying drawing, the present invention is further described.

A measuring method for LCD device dynamic image quality, comprises that PC control flow process and slave computer image occur and data acquisition operational scheme; Described PC control flow process is used for defining demonstration picture format, selection clock update scheme, sets graphics driver configuration, specified data drainage pattern, calculates dynamic image mass parameter; Described slave computer image occurs and data acquisition operational scheme is used for service data reception and conversion, synchronizing signal generation and control, test patterns generation and configuration, display driver selection and setting, performance data collection and transmission, and with digital visual interface DVI, low-voltage differential signal LVDS interface or Video Graphics Array VGA interface driver display screen; Between described PC control flow process and the generation of slave computer image and data acquisition operational scheme, pass through I ²c bus mode transmission measurement data, USB interface transmission transient response characteristic data.

Be that host computer (PC) control flow chart and slave computer image occur and data acquisition operational flow diagram as shown in Figure 1 and Figure 2, the I of Fig. 1 bottom host computer (PC) ²the I of C interface and Fig. 2 top slave computer ²c interface joins, and the USB interface of the USB interface of Fig. 1 bottom host computer (PC) and Fig. 2 top slave computer is joined.

As shown in Figure 1, PC control flow process complete measuring process 1) clock scheme, 2) manual measurement, 3) automatically measure and 4) sequence measuring four parts, the execution step of each several part is as follows:

1) clock scheme: belong to parameter and generate and account form (Para_G & C)

100). select display resolution: a). resolution edit box Resolution selects one to set resolution, refresh rate Refresh Rate selects 50HZ, 60HZ, 75HZ, 100HZ or 120HZ, synthetic image format parameter in total pixel HTOT that is expert at, the synchronous pixel HSY of row, row back porch pixel HBP, row display pixel HAC, the total pixel VTOT of frame, frame synchronization pixel VSY, frame back porch pixel VBP, frame display pixel VAC edit box; B). while selecting other resolution, in HTOT, HSY, HBP, HAC, VTOT, VSY, VBP, VAC edit box, show blank, the picture format parameter that manually input display setting software generates;

101). select graphics proportion: a). in dimension of picture edit box Block Size, generate and meet block pattern ratio data Hsta, Hend, Vsta, the Vend that sets resolution; B). while selecting other resolution, in Block Size edit box, show blank, manually input Hsta, Hend, Vsta, Vend;

102). calculate list/bis-pixel clock frequency: a). as digital modeling edit box Pixel Mode, selecting at 0 o'clock is single pixel driver, and the data in HTOT edit box are constant, and it is two pixel drivers that Pixel Mode selects at 1 o'clock, and the data in HTOT edit box are except 2; B) .HTOT=HAC+HFP+HSY+HBP, HFP is row crop pixel, VTOT=VAC+VFP+VSY+VBP, VFP is frame crop pixel, clock frequency is f _cLK=HTOT * VTOT * F _re, F _reit is display refresh rates; C). at frequency edit box f _cLKmiddle generation output clock frequency;

103). calculate output frequency: by formula calculate output frequency, f _rEFfor reference frequency, N _ffor feedback division coefficient, N _rfor with reference to divide ratio, N _pfor secondary divide ratio, N _fspan is 1 ~ 2047, wherein can not value 10,11,12,13,14,15,19,20,21,22,23,28,29,30,31,37,38,39,46,47,55, and N _rspan is 1 ~ 255, N _pvalue is 1,2,3,4,5,6,8,9,10,12,15,16,18,20,25,50;

104). calculated rate error: by formula Δ f _err=| f _cLK-f ' _cLK| calculated rate error, Δ f _errfor frequency absolute error, computation process: interior loop is to set N _f, N _r, at N _pin span, calculate Δ f _err, middle level circulation is to set N _f, successively at N _p, N _rin span, calculate Δ f _err, outer circulation is successively at N _p, N _r, N _fin span, calculate Δ f _err, all Δ f after three layers of circulation _errbe less than 0.001 f ' _cLK, its divide ratio N _p, N _r, N _fall enter solution list;

105). generated clock data: an optional scheme in solution list, generates 16 byte clock datas that meet this scheme in clock data edit box CLK_Data;

106). start resolution update: a). with I ²c bus mode transmits 16 byte clock datas in CLK_Data edit box to the clock data buffer area Xdata[rnum of on-site programmable gate array FPGA in pictcure generator]; B). with I ²c bus mode transfer step 100) data that generate are to the global buffer register fullregbuf[I of FPGA ²cBit..0], data length is 89; C). with I ²c bus mode transfer step 101) data that generate are to the global buffer register fullregbuf[I of FPGA ²cBit..0], data length is 44;

2) manual measurement: belong to single feature measurement and account form (Schara_M & C)

200). data collecting card setting: a). create an analog acquisition passage Physical Channel and collection voltage range Maximum Value/Minimum Value is set; B). configuration sampling pattern Finite Samples, sampling rate Sample Rate and sampling number Samples per Time; C). configure trigger passage Start Trigger Source and triggering edge Start Edge, d). configuration stops trigger pip pattern Reference Trigger Source and trigger source Reference Edge;

201). screen drives and arranges: a). and select DVI, LVDS or VGA to drive interface; B). select red R, one of green G, blue B, or R, G, B select entirely;

202). transient state saltus step arranges: a). selected two saltus step grade Level1, Level2 in 0 ~ 255 GTG; B). take a frame 16.7ms as every grade of gray scale residence time T1 of unit setting, T2, T3;

203). measure setup: a). select to measure in real time Real-Time or average measurement Average; B). set average measurement number of times Average Times, Average Times=N is less than or equal to 40; C). select the storing path of the image data Excel file of generation automatically;

204). measure and start: a). with I ²c bus mode transmits respectively 2 type of drive data, 3 looks and selects data, 1 bit pattern categorical data, 48 bit pattern luma data, 24 GTG residence time data to the fullregbuf[I of FPGA ²cBit..0]; B). through USB interface, start analog acquisition data procedures Start Task and read the sampled data Read property Node of PC data buffer; C). in the oscillograph of interface, show one in real time or the transient response characteristic Y of multiple averaging ₀(t), Y ₀that voltage, t are the time;

205). calculation of parameter: a). use N average image data to measure noise to eliminate; B). 10% ~ 90% time of definition collection waveform rising edge is that 90% ~ 10% time of liquid crystal response rise time LCRT-rising time, negative edge is liquid crystal response LCRT-falling fall time time; C). according to at transient response curve Y ₀(t) the moving window integral result of previous frame time width, calculates moving image response curve MPRC, wherein τ=-x _pit _f/ v, x _piscreen coordinate, T _fthat frame period, v are block pattern movement velocitys; D). 10% ~ 90% time of definition MPRC rising edge is that 90% ~ 10% time of fuzzy edge rise time BET-rising time, negative edge is fuzzy edge BET-falling fall time time;

3) automatically measure: belong to many feature measurements and account form (Mchara_M & C)

300). repeating step 200), step 201) in a) and b), step 202) in b), step 203) in b) and c);

301). setting grey exponent number Gray Numbers is 7 or 9;

302). according to Gray Numbers, at default GTG, set 7 or 9 regulation GTGs of automatic generation in form Default Gray Setting;

303). to measure and start: a). automatic sequence is selected two saltus step GTGs in Default Gray Setting; B). repeating step 204) in a), b) and c), in the oscillograph of interface, show that gang is average according to N time m=N _g(N _g+ 1) for GTG combination sum, in 0 ~ 255 gray-scale areas, be divided into N _ggreyscale level, is generally 7 or 9, and adjacent two level spacings are identical;

304). calculation of parameter: a). repeating step 205); B). according to the relational expression EBET=BET/ (0.9-0.1) between Blurred edge time BET and extend blurred edge time EBET, the mean value calculation under Motion picture response time MPRT combines according to different GTGs, i, j=1,2,3....N;

4) sequence measuring: belong to multiple measurement and account form (Mvari_M & C)

400). repeating step 200), step 201) in a) and b), step 203) in c);

401). measure setup: a). set the space periodic T of the sinusoidal figure of test _s, T _scorresponding value 2,4,6,8,12,16,24,32,48,64 in 0 ~ 9 scope; B). setting the sinusoidal figure movement velocity v of test is 4 or 8; C). set sinusoidal figure offset pointer Index, when the value of v=4 or 8, Index is 0,1,2,3 or 0,1,2,3,4,5,6,7;

402). measure and start: a). with I ²c bus mode transmits 9 bit test sequence data block lengths, 4 bit pattern space periodic data, 3 bit pattern angular movement speed data, 3 bit pattern offset pointer data to the fullregbuf[I of FPGA ²cBit..0]; B) .3 bit pattern offset pointer data are in step 401) in c) automatically increase progressively in the scope set; C). repeating step 204) in b); D). in the oscillograph of interface, show v bar response family curve i=0,1 ..., v-1, that voltage, t are the time;

403). calculation of parameter: a). according to the voltage distribution curve that calculating perceives locus x be take the time in frame period as unit with the pixel cell unit of being of a size of, time t; B). according to step 401), when voltage distribution curve is Sine distribution pattern Y ^*(x), time, calculate dynamic modulation transfer function $\mathrm{DMTF}(v,f)=\frac{C^{\′}(v,f)}{C},$ $C=\frac{Y_{\max }-Y_{\min }}{Y_{\max }+Y_{\min }}$ Sine distribution pattern Y ^*(x) contrast, Y _maxmaximum voltage, Y _minbe minimum voltage, C ' is Sine distribution pattern Y ' contrast (x), y ^*(x) spatial frequency.

As shown in Figure 2, slave computer image occurs and data acquisition operational scheme complete measuring process 5) clock upgrades, 6) figure configuration, 7) synchro control and 8) data acquisition four parts, the execution step of each several part is as follows:

5) clock upgrades: belong to data receiver and transmission mode (Da_R & T)

500). data receiver buffer memory: a) .I ²c data reception module I ²c_expander serial received step 106) data that a) pass down in, and be converted to 8 bit parallel data; B) .I ²c_expander send the Xdata[rnum of parallel data to clock data receiver module R_FT245BM];

501). Data Update is prepared: a) .R_FT245BM puts reset terminal reset=" 0 ", and the reset terminal reset=" 0 " of clock data writing module W_FS6370 forbids that W_FS6370 starts; B). put the eeprom address of clock chip FS6370 to the address of devices output terminal raddr[7..0 of R_FT245BM]; C). put the register first address of FS6370 to register address output terminal addr[7..0];

502). Data Update starts: a) .R_FT245BM puts and writes control output end wr=" 1 ", and W_FS6370 writes control input end wr=" 1 ", W_FS6370 write operation; B) .R_FT245BM puts reset=" 1 ", the reset=of W_FS6370 " 1 ", and W_FS6370 starts; C) .R_FT245BM extracts Xdata[rnum successively] in clock data to data output end rdata[7..0]; D) .R_FT245BM increases progressively register address 00H ~ 0FH to addr[7..0 of FS6370];

503). data write transmission: a). according to step 501) in b) and c), step 502) in c) and d), the address of devices input end raddr[7..0 of W_FS6370] obtain eeprom address, the register address input end addr[7..0 of FS6370] obtain register address, the data input pin data[7..0 of FS6370] obtain rdata[7..0] data; B) .W_FS6370 puts pattern output terminal mode=" 0 ", and FS6370 is programming mode; C) .W_FS6370 puts power down control output end pd=" 1 ", the FS6370 write operation that powers on; D) the output terminal of clock scl=" 1 " of .W_FS6370, serial data output terminal sda=" 1 " become sda=" 0 ", the I of FS6370 ²byte data transmission time sequence of C bus starts; E) .W_FS6370 send raddr[7..0] address to sda, order send addr[7..0] address to sda, send data[7..0 successively] data to sda; F) scl=of .W_FS6370 " 1 ", sda=" 0 " become sda=" 1 ", the I of FS6370 ²byte data transmission time sequence of C bus finishes;

504). data write end: a) .16 byte clock data writes FS6370 and finish, and R_FT245BM puts the wr=" 0 " of wr=" 0 ", W_FS6370, and W_FS6370 puts mode=" 1 ", and FS6370 is operational mode; B) .W_FS6370 puts pd=" 0 ", puts pd=" 1 " again, after FS6370 power down, powers on again, and in the EEPROM of FS6370,16 byte clock datas are called in control register, the image source global clock that FS6370 output is upgraded;

6) figure configuration: belong to figure and set and generating mode (Ima_S & G)

600) .I ²c data receiver: a) .I ²c_expander serial received step 106) data that the b in) and c) pass down; B) .I ²c_expander serial received step 204) in a), step 402) in the data that a) pass down; C) .I ²c_expander changes serial data and is cached in the fullregbuf[I in image generation module fran_pg after into 8 bit parallel data ²cBit..0];

601). resolution definition: according to step 600) in a) and c), fran_pg makes picture format Parameter H AC[10..0]=HAC, VAC[10..0]=VAC, HSY[10..0]=HSY, VSY[10..0]=VSY, HBP[10..0]=HBP, VBP[10..0]=VBP, HTOT[11..0]=HTOT, VTOT[10..0]=VTOT;

602). type of drive is selected: a). according to step 600) in b) and c), fran_pg assignment three looks enable Renab/Genab/Benab and drive to select lvds_dvi_vga_sel[1..0]; B). according to Renab/Genab/Benab, fran_pg enables figure output Red_out[7..0]/Green_out[7..0]/Blue_out[7..0]; C). drive handover module L_D_V_converter from fran_pg, to obtain lvds_dvi_vga_sel[1..0] and Red_out[7..0]/Green_out[7..0]/Blue_out[7..0], conversion and selection meet the interface output output_r_pg[7..0 of LVDS, DVI or VGA type of drive]/output_g_pg[7..0]/output_b_pg[7..0];

603). block pattern size is set: a). according to step 600) in a) and c), the block pattern module varloadblocks in fran_pg establishes the screen position h_sta[10..0 on 4 limits of figure]=Hsta, h_end[10..0]=Hend, v_sta[10..0]=Vsta, v_end[10..0]=Vend; B) .varloadblocks order is at h_sta[10..0], h_end[10..0], v_sta[10..0], v_end[10..0] screen region in generation level, vertical output henable, venable;

604). block pattern transient state is set: a). according to step 600) in b) and c), fran_pg assignment transient state residence time time0, time1, time2, time3, wherein time0=6 is the default residence time, and time1, time2, time3 are the saltus step residence time; B). according to step 600) in b) and c), fran_pg assignment three look GTG red_in1/green_in1/blue_in1, red_in2/green_in2/blue_in2; C) the transient state saltus step module theserial_3L in .fran_pg obtains time0, time1, time2, time3, red_in1/green_in1/blue_in1, red_in2/green_in2/blue_in2 from fran_pg; D) .theserial_3L is set in the GTG output Red_3L_out[7..0 during time0, time1, time2, time3]/Green_3L_out[7..0]/Blue_3L_out[7..0] equal 0, red_in1/green_in1/blue_in1, red_in2/green_in2/blue_in2, red_in1/green_in1/blue_in1; E) .theserial_3L, at time1 initial time, produces and triggers output trigger_3L_out;

605). sinusoidal figure sequence loads: a). according to step 600) in b) and c), fran_pg assignment data block sequence length L=data_length[8..0], data block address T _s=main_addr[3..0], figure movement velocity v=Speed[4..0], map migration amount pointer Index=Index[4..0]; B) the sinusoidal figure module Sine_pattern in .fran_pg obtains data_length[8..0 from fran_pg], main_addr[3..0], Speed[4..0], Index[4..0]; C). according to L, T _s, v, Index, Sine_pattern reads the gray scale sequence data in sinusoidal figure ROM (read-only memory) sinewave_rom, produces sequence GTG output Red_sine_out[7..0]/Green_sine_out[7..0]/Blue_sine_out[7..0]; D) .sinewave_rom establishes every v gray scale sequence and repeats once, along with Index increases progressively automatically from 0 to v-1, loads the different gray scale sequences of v kind; E) .Sine_pattern establishes L and count down to data_length[8..0]-2 o'clock, produce and trigger output trigger_sine_out;

606). test patterns generation: a). according to step 600) in b) and c), fran_pg obtains pattern classes data pattern, selects to generate square saltus step figure or sinusoidal sequence figure; B). according to step 603) in b), step 604) in d), fran_pg generates square saltus step figure, according to step 602) in b) mode export; C). according to step 603) in b), step 605) in c) and d), fran_pg generates sinusoidal sequence figure, according to step 602) and in b) mode export; D). according to step 604) in e), step 605) in e), fran_pg produces resolution chart and triggers output trigger_out;

7) synchro control: belong to pixel counts and pulse generate mode (Pix_C & Pul_G)

700). frame-synchronizing impulse generates: according to step 601), linage-counter in fran_pg is from h_counter.q[10..0]=HTOT-3 is to h_counter.q[10..0]=HSY-3, horizontal synchronizing pulse HSync_out generates, frame counter in fran_pg is from v_counter.q[10..0]=VTOT is to v_counter.q[10..0]=VSY, frame-synchronizing impulse VSync_out generates;

701). blanking pulse generates: a). according to step 601), h_counter.q[10..0]=HSY-3+HBP-4+HAC, horizontal blanking impulse nblankh_art starts, h_counter.q[10..0]=HSY-3+HBP-4, horizontal blanking impulse nblankh_art finishes; B). according to step 601), v_counter.q[10..0]=VSY+VBP+VAC, frame blanking impulse nblankv_art starts, v_counter.q[10..0]=VSY+VBP, frame blanking impulse nblankv_art finishes; C). according to nblankh_art, nblankv_art, generate composite blanking pulse nblank_art, after frequency division, produce composite blanking pulse output NBlank_out;

8) data acquisition: belong to data acquisition and transmission mode (DAQ_Tran)

800). block pattern transient data gathers: a). data collecting card is according to step 200) in c) the digital I/O port receiving step 604 set) and in e), step 606) in d) the trigger collection signal that produces; B). according to trigger pip, data collecting card is according to step 200) in a) regulation analog input mouth start to gather transient data; C). according to step 200) in b), data collecting card completes the data acquisition in a sampling period automatically, and repeats the executing data sampling period; D). through USB interface, transmit image data;

801). sinusoidal figure transient data gathers: a). data collecting card is according to step 200) in c) the digital I/O port receiving step 605 set) and in e), step 606) in d) the trigger collection signal that produces; B). repeating step 800). in b); C). according to step 200) in b), data collecting card completes the data acquisition in a sampling period automatically; D). according to step 605) in d), data collecting card automatically performs the data acquisition in v kind sampling period; E). repeating step 800) in d).

The above is only the preferred embodiment of the present invention; be noted that for those skilled in the art; under the premise without departing from the principles of the invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (1)

1. the measuring method of LCD device dynamic image quality, is characterized in that: the method comprises that PC control flow process and slave computer image occur and data acquisition operational scheme; Described PC control flow process is used for defining demonstration picture format, selection clock update scheme, sets graphics driver configuration, specified data drainage pattern, calculates dynamic image mass parameter; Described slave computer image occurs and data acquisition operational scheme is used for service data reception and conversion, synchronizing signal generation and control, test patterns generation and configuration, display driver selection and setting, performance data collection and transmission, and with digital visual interface DVI, low-voltage differential signal LVDS interface or Video Graphics Array VGA interface driver display screen;

Between described PC control flow process and the generation of slave computer image and data acquisition operational scheme, pass through I ²c bus mode transmission measurement data, USB interface transmission transient response characteristic data;

Described PC control flow process complete measuring process 1) clock scheme, 2) manual measurement, 3) automatically measure and 4) sequence measuring four parts, the execution step of each several part is as follows:

1) clock scheme

100). select display resolution: a). resolution edit box Resolution selects one to set resolution, and refresh rate Refresh Rate selects 50H _z, 60H _z, 75H _z, 100H _zor 120H _z, synthetic image format parameter in total pixel HTOT that is expert at, the synchronous pixel HSY of row, row back porch pixel HBP, row display pixel HAC, the total pixel VTOT of frame, frame synchronization pixel VSY, frame back porch pixel VBP, frame display pixel VAC edit box; B). while selecting other resolution, in HTOT, HSY, HBP, HAC, VTOT, VSY, VBP, VAC edit box, show blank, the picture format parameter that manually input display setting software generates;

101). select graphics proportion: a). in dimension of picture edit box Block Size, generate and meet block pattern ratio data Hsta, Hend, Vsta, the Vend that sets resolution; B). while selecting other resolution, in Block Size edit box, show blank, manually input Hsta, Hend, Vsta, Vend;

102). calculate list/bis-pixel clock frequency: a). as digital modeling edit box Pixel Mode, selecting at 0 o'clock is single pixel driver, and the data in HTOT edit box are constant, and it is two pixel drivers that Pixel Mode selects at 1 o'clock, and the data in HTOT edit box are except 2; B) .HTOT=HAC+HFP+HSY+HBP, HFP is row crop pixel, VTOT=VAC+VFP+VSY+VBP, VFP is frame crop pixel, clock frequency is f _cLK=HTOT * VTOT * F _re, F _reit is display refresh rates; C). at frequency edit box f _cLKmiddle generation output clock frequency;

103). calculate output frequency: by formula calculate output frequency, f _rEFfor reference frequency, N _ffor feedback division coefficient, N _rfor with reference to divide ratio, N _pfor secondary divide ratio, N _fspan is 1～2047, wherein can not value 10,11,12,13,14,15,19,20,21,22,23,28,29,30,31,37,38,39,46,47,55, and N _rspan is 1～255, N _pvalue is 1,2,3,4,5,6,8,9,10,12,15,16,18,20,25,50;

104). calculated rate error: by formula Δ f _err=| f _cLK-f ' _cLK| calculated rate error, Δ f _errfor frequency absolute error, computation process: interior loop is to set N _f, N _r, at N _pin span, calculate Δ f _err, middle level circulation is to set N _f, successively at N _p, N _rin span, calculate Δ f _err, outer circulation is successively at N _p, N _r, N _fin span, calculate Δ f _err, all Δ f after three layers of circulation _errbe less than 0.001 f ' _cLK, its divide ratio N _p, N _r, N _fall enter solution list;

105). generated clock data: an optional scheme in solution list, generates 16 byte clock datas that meet this scheme in clock data edit box CLK_Data;

106). start resolution update: a). with I ²c bus mode transmits 16 byte clock datas in CLK_Data edit box to the clock data buffer area Xdata[rnum of on-site programmable gate array FPGA in pictcure generator]; B). with I ²c bus mode transfer step 100) data that generate are to the global buffer register fullregbuf[I of FPGA ²cBit..0], data length is 89; C). with I ²c bus mode transfer step 101) data that generate are to the global buffer register fullregbuf[I of FPGA ²cBit..0], data length is 44;

2) manual measurement

200). data collecting card setting: a). create an analog acquisition passage Physical Channel and collection voltage range Maximum Value/Minimum Value is set; B). configuration sampling pattern Finite Samples, sampling rate Sample Rate and sampling number Samples per Time; C). configure trigger passage Start Trigger Source and triggering edge Start Edge, d). configuration stops trigger pip pattern Reference Trigger Source and trigger source Reference Edge;

201). screen drives and arranges: a). and select DVI, LVDS or VGA to drive interface; B). select red R, one of green G, blue B, or R, G, B select entirely;

202). transient state saltus step arranges: a). selected two saltus step grade Level1, Level2 in 0～255 GTG; B). take a frame 16.7ms as every grade of gray scale residence time T1 of unit setting, T2, T3;

203). measure setup: a). select to measure in real time Real-Time or average measurement Average; B). set average measurement number of times Average Times, Average Times=N is less than or equal to 40; C). select the storing path of the image data Excel file of generation automatically;

204). measure and start: a). with I ²c bus mode transmits respectively 2 type of drive data, 3 looks and selects data, 1 bit pattern categorical data, 48 bit pattern luma data, 24 GTG residence time data to the fullregbuf[I of FPGA ²cBit..0]; B). through USB interface, start analog acquisition data procedures Start Task and read the sampled data Read property Node of PC data buffer; C). in the oscillograph of interface, show one in real time or the transient response characteristic Y of multiple averaging ₀(t), Y ₀that voltage, t are the time;

205). calculation of parameter: a). use N average image data to measure noise to eliminate; B). 10%～90% time of definition collection waveform rising edge is that 90%～10% time of liquid crystal response rise time LCRT-rising time, negative edge is liquid crystal response LCRT-falling fall time time; C). according to at transient response curve Y ₀(t) the moving window integral result of previous frame time width, calculates moving image response curve MPRC, wherein τ=-x _pit _f/ v, x _piscreen coordinate, T _fthat frame period, v are block pattern movement velocitys; D). 10%～90% time of definition MPRC rising edge is that 90%～10% time of fuzzy edge rise time BET-rising time, negative edge is fuzzy edge BET-falling fall time time;

3) automatically measure

300). repeating step 200), step 201) in a) and b), step 202) in b), step 203) in b) and c);

301). setting grey exponent number Gray Numbers is 7 or 9;

302). according to Gray Numbers, at default GTG, set 7 or 9 regulation GTGs of automatic generation in form Default Gray Setting;

303). to measure and start: a). automatic sequence is selected two saltus step GTGs in Default Gray Setting; B). repeating step 204) in a), b) and c), in the oscillograph of interface, show that gang is average according to N time m=N _g(N _g+ 1) for GTG combination sum, in 0～255 gray-scale areas, be divided into N _ggreyscale level, is generally 7 or 9, and adjacent two level spacings are identical;

304). calculation of parameter: a). repeating step 205); B). according to the relational expression EBET=BET/ (0.9-0.1) between Blurred edge time BET and extend blurred edge time EBET, the mean value calculation under Motion picture response time MPRT combines according to different GTGs, $\mathrm{MPRT}=\frac{1}{M}\underset{i\≠j}{\mathrm{\Σ}}{\mathrm{EBET}}_{\mathrm{ij}},i,j-\mathrm{1,2,3}....N;$

4) sequence measuring

400). repeating step 200), step 201) in a) and b), step 203) in c);

401). measure setup: a). set the space periodic T of the sinusoidal figure of test _s, T _scorresponding value 2,4,6,8,12,16,24,32,48,64 in 0～9 scope; B). setting the sinusoidal figure movement velocity v of test is 4 or 8; C). set sinusoidal figure offset pointer Index, when the value of v=4 or 8, Index is 0,1,2,3 or 0,1,2,3,4,5,6,7;

402). measure and start: a). with I ²c bus mode transmits 9 bit test sequence data block lengths, 4 bit pattern space periodic data, 3 bit pattern angular movement speed data, 3 bit pattern offset pointer data to the fullregbuf[I of FPGA ²cBit..0]; B) .3 bit pattern offset pointer data are in step 401) in c) automatically increase progressively in the scope set; C). repeating step 204) in b); D). in the oscillograph of interface, show v bar response family curve i=0,1 ..., v-1, that voltage, t are the time;

403). calculation of parameter: a). according to the voltage distribution curve that calculating perceives locus x be take the time in frame period as unit with the pixel cell unit of being of a size of, time t; B). according to step 401), when voltage distribution curve is Sine distribution pattern Y ^*(x), time, calculate dynamic modulation transfer function $\mathrm{DMTF}(v,f)=\frac{C^{\′}(v,f)}{C},$ $C=\frac{Y_{\max }-Y_{\min }}{Y_{\max }+Y_{\min }}$ Sine distribution pattern Y ^*(x) contrast, Y _maxmaximum voltage, Y _minbe minimum voltage, C' is Sine distribution pattern Y'(x) contrast, y ^*(x) spatial frequency;

Described slave computer image occurs and data acquisition operational scheme complete measuring process 5) clock upgrades, 6) figure configuration, 7) synchro control and 8) data acquisition four parts, the execution step of each several part is as follows:

5) clock upgrades

500). data receiver buffer memory: a) .I ²c data reception module I ²c_expander serial received step 106) data that a) pass down in, and be converted to 8 bit parallel data; B) .I ²c_expander send the Xdata[rnum of parallel data to clock data receiver module R_FT245BM];

501). Data Update is prepared: a) .R_FT245BM puts reset terminal reset=" 0 ", and the reset terminal reset=" 0 " of clock data writing module W_FS6370 forbids that W_FS6370 starts; B). put the eeprom address of clock chip FS6370 to the address of devices output terminal raddr[7..0 of R_FT245BM]; C). put the register first address of FS6370 to register address output terminal addr[7..0];

502). Data Update starts: a) .R_FT245BM puts and writes control output end wr=" 1 ", and W_FS6370 writes control input end wr=" 1 ", W_FS6370 write operation; B) .R_FT245BM puts reset=" 1 ", the reset=of W_FS6370 " 1 ", and W_FS6370 starts; C) .R_FT245BM extracts Xdata[rnum successively] in clock data to data output end rdata[7..0]; D) .R_FT245BM increases progressively register address 00H～0FH to addr[7..0 of FS6370];

503). data write transmission: a). according to step 501) in b) and c), step 502) in c) and d), the address of devices input end raddr[7..0 of W_FS6370] obtain eeprom address, the register address input end addr[7..0 of FS6370] obtain register address, the data input pin data[7..0 of FS6370] obtain rdata[7..0] data; B) .W_FS6370 puts pattern output terminal mode=" 0 ", and FS6370 is programming mode; C) .W_FS6370 puts power down control output end pd=" 1 ", the FS6370 write operation that powers on; D) the output terminal of clock scl=" 1 " of .W_FS6370, serial data output terminal sda=" 1 " become sda=" 0 ", the I of FS6370 ²byte data transmission time sequence of C bus starts; E) .W_FS6370 send raddr[7..0] address to sda, order send addr[7..0] address to sda, send data[7..0 successively] data to sda; F) scl=of .W_FS6370 " 1 ", sda=" 0 " become sda=" 1 ", the I of FS6370 ²byte data transmission time sequence of C bus finishes;

504). data write end: a) .16 byte clock data writes FS6370 and finish, and R_FT245BM puts the wr=" 0 " of wr=" 0 ", W_FS6370, and W_FS6370 puts mode=" 1 ", and FS6370 is operational mode; B) .W_FS6370 puts pd=" 0 ", puts pd=" 1 " again, after FS6370 power down, powers on again, and in the EEPROM of FS6370,16 byte clock datas are called in control register, the image source global clock that FS6370 output is upgraded;

6) figure configuration

600) .I ²c data receiver: a) .I ²c_expander serial received step 106) data that the b in) and c) pass down; B) .I ²c_expander serial received step 204) in a), step 402) in the data that a) pass down; C) .I ²c_expander changes serial data and is cached in the fullregbuf[I in image generation module fran_pg after into 8 bit parallel data ²cBit..0];

601). resolution definition: according to step 600) in a) and c), fran_pg makes picture format Parameter H AC[10..0]=HAC, VAC[10..0]=VAC, HSY[10..0]=HSY, VSY[10..0]=VSY, HBP[10..0]=HBP, VBP[10..0]=VBP, HTOT[11..0]=HTOT, VTOT[10..0]=VTOT;

602). type of drive is selected: a). according to step 600) in b) and c), fran_pg assignment three looks enable Renab/Genab/Benab and drive to select lvds_dvi_vga_sel[1..0]; B). according to Renab/Genab/Benab, fran_pg enables figure output Red_out[7..0]/Green_out[7..0]/Blue_out[7..0]; C). drive handover module L_D_V_converter from fran_pg, to obtain lvds_dvi_vga_sel[1..0] and Red_out[7..0]/Green_out[7..0]/Blue_out[7..0], conversion and selection meet the interface output output_r_pg[7..0 of LVDS, DVI or VGA type of drive]/output_g_pg[7..0]/output_b_pg[7..0];

603). block pattern size is set: a). according to step 600) in a) and c), the block pattern module varloadblocks in fran_pg establishes the screen position h_sta[10..0 on 4 limits of figure]=Hsta, h_end[10..0]=Hend, v_sta[10..0]=Vsta, v_end[10..0]=Vend; B) .varloadblocks order is at h_sta[10..0], h_end[10..0], v_sta[10..0], v_end[10..0] screen region in generation level, vertical output henable, venable;

604). block pattern transient state is set: a). according to step 600) in b) and c), fran_pg assignment transient state residence time time0, time1, time2, time3, wherein time0=6 is the default residence time, and time1, time2, time3 are the saltus step residence time; B). according to step 600) in b) and c), fran_pg assignment three look GTG red_in1/green_in1/blue_in1, red_in2/green_in2/blue_in2; C) the transient state saltus step module theserial_3L in .fran_pg obtains time0, time1, time2, time3, red_in1/green_in1/blue_in1, red_in2/green_in2/blue_in2 from fran_pg; D) .theserial_3L is set in the GTG output Red_3L_out[7..0 during time0, time1, time2, time3]/Green_3L_out[7..0]/Blue_3L_out[7..0] equal 0, red_in1/green_in1/blue_in1, red_in2/green_in2/blue_in2, red_in1/green_in1/blue_in1; E) .theserial_3L, at time1 initial time, produces and triggers output trigger_3L_out;

605). sinusoidal figure sequence loads: a). according to step 600) in b) and c), fran_pg assignment data block sequence length L=data_length[8..0], data block address T _s=main_addr[3..0], figure movement velocity v=Speed[4..0], map migration amount pointer Index=Index[4..0]; B) the sinusoidal figure module Sine_pattern in .fran_pg obtains data_length[8..0 from fran_pg], main_addr[3..0], Speed[4..0], Index[4..0]; C). according to L, T _s, v, Index, Sine_pattern reads the gray scale sequence data in sinusoidal figure ROM (read-only memory) sinewave_rom, produces sequence GTG output Red_sine_out[7..0]/Green_sine_out[7..0]/Blue_sine_out[7..0]; D) .sinewave_rom establishes every v gray scale sequence and repeats once, along with Index increases progressively automatically from 0 to v-1, loads the different gray scale sequences of v kind; E) .Sine_pattern establishes L and count down to data_length[8..0]-2 o'clock, produce and trigger output trigger_sine_out;

606). test patterns generation: a). according to step 600) in b) and c), fran_pg obtains pattern classes data pattern, selects to generate square saltus step figure or sinusoidal sequence figure; B). according to step 603) in b), step 604) in d), fran_pg generates square saltus step figure, according to step 602) in b) mode export; C). according to step 603) in b), step 605) in c) and d), fran_pg generates sinusoidal sequence figure, according to step 602) and in b) mode export; D). according to step 604) in e), step 605) in e), fran_pg produces resolution chart and triggers output trigger_out;

7) synchro control

700). frame-synchronizing impulse generates: according to step 601), linage-counter in fran_pg is from h_counter.q[10..0]=HTOT-3 is to h_counter.q[10..0]=HSY-3, horizontal synchronizing pulse HSync_out generates, frame counter in fran_pg is from v_counter.q[10..0]=VTOT is to v_counter.q[10..0]=VSY, frame-synchronizing impulse VSync_out generates;

701). blanking pulse generates: a). according to step 601), h_counter.q[10..0]=HSY-3+HBP-4+HAC, horizontal blanking impulse nblankh_art starts, h_counter.q[10..0]=HSY-3+HBP-4, horizontal blanking impulse nblankh_art finishes; B). according to step 601), v_counter.q[10..0]=VSY+VBP+VAC, frame blanking impulse nblankv_art starts, v_counter.q[10..0]=VSY+VBP, frame blanking impulse nblankv_art finishes; C). according to nblankh_art, nblankv_art, generate composite blanking pulse nblank_art, after frequency division, produce composite blanking pulse output NBlank_out;

8) data acquisition

800). block pattern transient data gathers: a). data collecting card is according to step 200) in c) the digital I/O port receiving step 604 set) and in e), step 606) in d) the trigger collection signal that produces; B). according to trigger pip, data collecting card is according to step 200) in a) regulation analog input mouth start to gather transient data; C). according to step 200) in b), data collecting card completes the data acquisition in a sampling period automatically, and repeats the executing data sampling period; D). through USB interface, transmit image data;

801). sinusoidal figure transient data gathers: a). data collecting card is according to step 200) in c) the digital I/O port receiving step 605 set) and in e), step 606) in d) the trigger collection signal that produces; B). repeating step 800). in b); C). according to step 200) in b), data collecting card completes the data acquisition in a sampling period automatically; D). according to step 605) in d), data collecting card automatically performs the data acquisition in v kind sampling period; E). repeating step 800) in d).