CN102681941A - Extensible embedded simulation test system - Google Patents
Extensible embedded simulation test system Download PDFInfo
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- CN102681941A CN102681941A CN2012101509594A CN201210150959A CN102681941A CN 102681941 A CN102681941 A CN 102681941A CN 2012101509594 A CN2012101509594 A CN 2012101509594A CN 201210150959 A CN201210150959 A CN 201210150959A CN 102681941 A CN102681941 A CN 102681941A
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Abstract
The invention provides an extensible embedded simulation test system which is formed through minimizing coupling degree between an operation interface and an underlying virtual machine and defining an excellent module design and is used for overcoming the disadvantage of insufficiency of embedded software testing caused by overdependence on target hardware in an embedded software testing process. The system comprises a user interface layer and a virtual machine simulation layer, wherein the user interface layer is a user interaction layer which is completely independent of other layers, and is called to interact with the underlying virtual machine only through command lines, and the virtual machine simulation layer is used for realizing the simulation of the target hardware. The system is applicable to virtual machine frameworks of a plurality of processors, establishes abstract embedded processor models, and provides an interface so as to integrate an upper software testing function.
Description
Technical field
The invention belongs to the embedded emulation field tests, be specifically related to a kind of extendible embedded emulation test macro.
Background technology
The tradition embedded software test is based on simulation hardware; Be characterized in that the emulation degree is high; Speed is fast, but its shortcoming need to be the support of target hardware, can't not drop in the test job before the moulding in target hardware; This just becomes the bottleneck of embedded software test, and the testing progress that has delayed embedded software to a certain extent also might be because of insufficient stability that finally has influence on embedded device of software test.
In order to overcome in the embedded software test process; Because to the undue inadequate shortcoming of embedded software test that is caused that relies on of target hardware; Realization is to the strong guarantee of embedded software quality, and Embedded Software Engineer's breakaway hardware to a certain extent carries out the test of embedded software.Reach this target, effective and efficient manner is that target hardware is carried out software emulation, promptly sets up a virtual target hardware with pure software and substitutes real target hardware.After building based on the development environment of above virtual target hardware; The Embedded Software Engineer just can directly move the embedded software that develops to target hardware in this environment; And this embedded software carried out preliminary test, the slip-stick artist is placed into embedded software on the real target hardware operation and carries out more careful test again after the target hardware moulding by the time.Use virtual target hardware can improve the testing efficiency of embedded software greatly, and can before the target hardware moulding, fully carry out test analysis, find the defective in the software early embedded software.
Summary of the invention
In order to overcome in the embedded software test process; Because to the undue inadequate shortcoming of embedded software test that is caused that relies on of target hardware; The degree of coupling through reducing operation interface and bottom virtual machine to the full extent and define good modular design the invention provides a kind of extendible embedded emulation test macro, and this system is applicable to the virtual machine architectural framework of multiple processor; Set up abstract flush bonding processor model, and provide interface with integrated upper layer software (applications) test function.
A kind of extendible embedded emulation test macro, this system comprises user interface layer and virtual machine simulation layer;
The family contact bed is the user interactions layer that is totally independent of other layer; The virtual machine that only calls with bottom through order line carries out alternately; The mode of its realization is: user interface program generates a subprocess and is used to move virtual machine; Through iostream being redirected to virtual machine, at first send a querying command when user interface program is initialized to virtual machine, through inquiring about all emulation commands and the information that this virtual machine provides to communicate by letter between implementation process; Virtual machine should be ordered and information feedback is given user interface and with the whole initialization of its function, above process is in this emulation testing software startup, to accomplish automatically.
Wherein, user interface is that the order line information according to the bottom virtual machine dynamically generates, and has different user interfaces to offer the user corresponding to different bottom virtual machines and uses; After obtaining all orders of virtual machine and information, the visualized operation that the user just can provide through this layer carries out that the state of emulation execution, the virtual machine of dis-assembling, the program of the loading that comprise file destination, file destination is checked, the task of checking of virtual memory.
The virtual machine simulation layer adopts modular design, comprises memory management module, architectural definition module, file destination loading module, instruction decoding execution module, Simulation Control module.
Memory management module is responsible for the accumulator system of target hardware is carried out modeling; And the access interface to this memory model is provided; Realize storage address mapping and virtual address translation task through configuration parameter, wherein target hardware only limits to the processor type of accumulator system unified addressing.
The architectural definition module definition a series of data structures of target hardware run time behaviour are described; Comprise register model, programmable counter, program execution context structure, interrupt vector, also defined memory map registers in the register model wherein and reached operation register access.
The file destination loading module is responsible for the file destination load memory model that compiling link is good, and in the process that file destination is packed into, accomplishes the initialization to virtual machine.
Instruction decoding execution module is realized the mapping of order number to instruction manipulation, accomplishes the emulation to the target hardware instruction set; This module adopts a series of macrodefined modes to set up the processor instruction set demoder, reaches the instruction decoding to CISC/RISC type processor instruction set through the configuration-direct buffer memory; This module is accepted is input as an order number; Decoding rule according to this module definition is filtered the instruction prefix in the order number; Identify operational code and data; And find the concrete realization code segment with the corresponding command function of this operational code, and use data in the instruction to participate in calculating also and carry out this code segment, accomplish setting at last to processor state.
The Simulation Control module is accomplished the control that is loaded into the simulation flow of instruction execution from program, all must be through this Simulation Control module to the visit of other modules in the virtual machine structure.
Wherein, the call relation of each module and workflow are following:
After Simulation Control module service routine is loaded the load command calls; The file destination loading module carries out the work of program loading according to the parameter of Simulation Control module load order; Loading module is the memory model in the mode write store administration module of the write order of the content in the file destination through calling memory management module in the program loading process, and calls the init order register in the architecture module is carried out initialization.
The Simulation Control module will instruct the demoder initialization in the decoding execution module with calling init_decoder order before executive routine, the decoding execution module called memory management module and reads and writes data the state of modification architecture module when instruction was carried out.
In addition; The Simulation Control module can be directly and memory management module and architectural definition module communicate so that External Program Interface can conduct interviews to memory model in the memory management module and architectural definition model through the Simulation Control module.
Beneficial effect
1. the present invention through reducing operation interface and bottom virtual machine to the full extent the degree of coupling and define good modular design, a virtual machine architectural framework that is adapted to multiple processor is provided, set up abstract flush bonding processor model.Can carry out the operation of embedded software by breakaway hardware to a certain extent.
2. the control mode that proposes of the present invention based on Cmd Shell; Can clearly bottom virtual machine emulation logic and outside UI, steering logic be distinguished; Make the virtual machine of bottom can be in emulation testing software switch arbitrarily, and define complete virtual machine and can realize reusing.
Description of drawings
Fig. 1 is the overall design block diagram of extendible embedded emulation test macro;
Fig. 2 is the modularization block diagram of virtual machine simulation layer;
Embodiment
Below in conjunction with accompanying drawing the present invention is further specified.
A kind of extendible embedded emulation test macro, this system comprises user interface layer and virtual machine simulation layer; As shown in Figure 1.
The family contact bed is the user interactions layer that is totally independent of other layer; The virtual machine that only calls with bottom through order line carries out alternately; The mode of its realization is: user interface program generates a subprocess and is used to move virtual machine; Through iostream being redirected to virtual machine, at first send a querying command when user interface program is initialized to virtual machine, through inquiring about all emulation commands and the information that this virtual machine provides to communicate by letter between implementation process; Virtual machine should be ordered and information feedback is given user interface and with the whole initialization of its function, above process is in this emulation testing software startup, to accomplish automatically.
Wherein, user interface is that the order line information according to the bottom virtual machine dynamically generates, and has different user interfaces to offer the user corresponding to different bottom virtual machines and uses; After obtaining all orders of virtual machine and information, the visualized operation that the user just can provide through this layer carries out that the state of emulation execution, the virtual machine of dis-assembling, the program of the loading that comprise file destination, file destination is checked, the task of checking of virtual memory.
The virtual machine simulation layer adopts modular design, comprises memory management module, architectural definition module, file destination loading module, instruction decoding execution module, Simulation Control module; As shown in Figure 2.
Memory management module is responsible for the accumulator system of target hardware is carried out modeling; And the access interface to this memory model is provided; Realize storage address mapping and virtual address translation task through configuration parameter, wherein target hardware only limits to the processor type of accumulator system unified addressing.
The architectural definition module definition a series of data structures of target hardware run time behaviour are described; Comprise register model, programmable counter, program execution context structure, interrupt vector, also defined memory map registers in the register model wherein and reached operation register access.
The file destination loading module is responsible for the file destination load memory model that compiling link is good, and in the process that file destination is packed into, accomplishes the initialization to virtual machine.
Instruction decoding execution module is realized the mapping of order number to instruction manipulation, accomplishes the emulation to the target hardware instruction set; This module adopts a series of macrodefined modes to set up the processor instruction set demoder, reaches the instruction decoding to CISC/RISC type processor instruction set through the configuration-direct buffer memory; This module is accepted is input as an order number; Decoding rule according to this module definition is filtered the instruction prefix in the order number; Identify operational code and data; And find the concrete realization code segment with the corresponding command function of this operational code, and use data in the instruction to participate in calculating also and carry out this code segment, accomplish setting at last to processor state.
The Simulation Control module is accomplished the control that is loaded into the simulation flow of instruction execution from program, all must be through this Simulation Control module to the visit of other modules in the virtual machine structure.
Wherein, the call relation of each module and workflow are following:
After Simulation Control module service routine is loaded the load command calls; The file destination loading module carries out the work of program loading according to the parameter of Simulation Control module load order; Loading module is the memory model in the mode write store administration module of the write order of the content in the file destination through calling memory management module in the program loading process, and calls the init order register in the architecture module is carried out initialization.
The Simulation Control module will instruct the demoder initialization in the decoding execution module with calling init_decoder order before executive routine, the decoding execution module called memory management module and reads and writes data the state of modification architecture module when instruction was carried out.
In addition; The Simulation Control module can be directly and memory management module and architectural definition module communicate so that External Program Interface can conduct interviews to memory model in the memory management module and architectural definition model through the Simulation Control module.
Claims (1)
1. extendible embedded emulation test macro, it is characterized in that: this system comprises user interface layer and virtual machine simulation layer;
The family contact bed is the user interactions layer that is totally independent of other layer; The virtual machine that only calls with bottom through order line carries out alternately; The mode of its realization is: user interface program generates a subprocess and is used to move virtual machine; Through iostream being redirected to virtual machine, at first send a querying command when user interface program is initialized to virtual machine, through inquiring about all emulation commands and the information that this virtual machine provides to communicate by letter between implementation process; Virtual machine should be ordered and information feedback is given user interface and with the whole initialization of its function, above process is in this emulation testing software startup, to accomplish automatically;
Wherein, user interface is that the order line information according to the bottom virtual machine dynamically generates, and has different user interfaces to offer the user corresponding to different bottom virtual machines and uses; After obtaining all orders of virtual machine and information, the visualized operation that the user just can provide through this layer carries out that the state of emulation execution, the virtual machine of dis-assembling, the program of the loading that comprise file destination, file destination is checked, the task of checking of virtual memory;
The virtual machine simulation layer adopts modular design, comprises memory management module, architectural definition module, file destination loading module, instruction decoding execution module, Simulation Control module;
Memory management module is responsible for the accumulator system of target hardware is carried out modeling; And the access interface to this memory model is provided; Realize storage address mapping and virtual address translation task through configuration parameter, wherein target hardware only limits to the processor type of accumulator system unified addressing;
The architectural definition module definition a series of data structures of target hardware run time behaviour are described; Comprise register model, programmable counter, program execution context structure, interrupt vector, also defined memory map registers in the register model wherein and reached operation register access;
The file destination loading module is responsible for the file destination load memory model that compiling link is good, and in the process that file destination is packed into, accomplishes the initialization to virtual machine;
Instruction decoding execution module is realized the mapping of order number to instruction manipulation, accomplishes the emulation to the target hardware instruction set; This module adopts a series of macrodefined modes to set up the processor instruction set demoder, reaches the instruction decoding to CISC/RISC type processor instruction set through the configuration-direct buffer memory; This module is accepted is input as an order number; Decoding rule according to this module definition is filtered the instruction prefix in the order number; Identify operational code and data; And find the concrete realization code segment with the corresponding command function of this operational code, and use data in the instruction to participate in calculating also and carry out this code segment, accomplish setting at last to processor state;
The Simulation Control module is accomplished the control that is loaded into the simulation flow of instruction execution from program, all must be through this Simulation Control module to the visit of other modules in the virtual machine structure;
Wherein, the call relation of each module and workflow are following:
After Simulation Control module service routine is loaded the load command calls; The file destination loading module carries out the work of program loading according to the parameter of Simulation Control module load order; Loading module is the memory model in the mode write store administration module of the write order of the content in the file destination through calling memory management module in the program loading process, and calls the init order register in the architecture module is carried out initialization;
The Simulation Control module will instruct the demoder initialization in the decoding execution module with calling init_decoder order before executive routine, the decoding execution module called memory management module and reads and writes data the state of modification architecture module when instruction was carried out;
In addition; The Simulation Control module can be directly and memory management module and architectural definition module communicate so that External Program Interface can conduct interviews to memory model in the memory management module and architectural definition model through the Simulation Control module.
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Cited By (7)
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| CN102968377A (en) * | 2012-12-13 | 2013-03-13 | 中国航空无线电电子研究所 | Virtual machine technique based airborne software system testing general platform |
| CN103218250A (en) * | 2013-03-29 | 2013-07-24 | 北京控制工程研究所 | Processor simulating method |
| CN105808362A (en) * | 2016-03-08 | 2016-07-27 | 浙江工业大学 | General communication method for automatically docking any third-party program |
| CN105893234A (en) * | 2014-12-30 | 2016-08-24 | 伊姆西公司 | Method for software testing and computing device |
| CN107239400A (en) * | 2017-06-09 | 2017-10-10 | 山东超越数控电子有限公司 | A kind of NandFlash abrasion equilibriums emulation platform |
| CN108572892A (en) * | 2017-03-14 | 2018-09-25 | 大唐移动通信设备有限公司 | A kind of off-line test method and apparatus based on PowerPC multi-core processors |
| CN110515825A (en) * | 2018-05-22 | 2019-11-29 | 株洲中车时代电气股份有限公司 | A kind of test method and system for graphical programming language |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102968377A (en) * | 2012-12-13 | 2013-03-13 | 中国航空无线电电子研究所 | Virtual machine technique based airborne software system testing general platform |
| CN103218250A (en) * | 2013-03-29 | 2013-07-24 | 北京控制工程研究所 | Processor simulating method |
| CN103218250B (en) * | 2013-03-29 | 2016-01-13 | 北京控制工程研究所 | A kind of processor analogy method |
| CN105893234A (en) * | 2014-12-30 | 2016-08-24 | 伊姆西公司 | Method for software testing and computing device |
| CN105808362A (en) * | 2016-03-08 | 2016-07-27 | 浙江工业大学 | General communication method for automatically docking any third-party program |
| CN108572892A (en) * | 2017-03-14 | 2018-09-25 | 大唐移动通信设备有限公司 | A kind of off-line test method and apparatus based on PowerPC multi-core processors |
| CN108572892B (en) * | 2017-03-14 | 2020-10-27 | 大唐移动通信设备有限公司 | PowerPC multi-core processor-based offline test method and device |
| CN107239400A (en) * | 2017-06-09 | 2017-10-10 | 山东超越数控电子有限公司 | A kind of NandFlash abrasion equilibriums emulation platform |
| CN110515825A (en) * | 2018-05-22 | 2019-11-29 | 株洲中车时代电气股份有限公司 | A kind of test method and system for graphical programming language |
| CN110515825B (en) * | 2018-05-22 | 2021-08-20 | 株洲中车时代电气股份有限公司 | Testing method and system for graphical programming language |
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Application publication date: 20120919 |