CN102681583A - High-precision band-gap reference circuit - Google Patents

Abstract

The invention relates to the field of integrated circuits. In order to minimize the influence of the offset voltage, the technical solution adopted by the present invention is that the high-precision bandgap reference circuit is composed of PMOS transistors P1, P2, P3, P4, NMOS transistors N1, N2, and transistors Q1 and Q2. In addition, it also includes 10 coms switches, so that N1 and N2 are connected to points C and D in turn, and the two branches of N1 and N2 are connected to points A and B in turn; or, Q1 and Q2 are connected to P1 and P2 in turn. The invention is mainly applied to the design and manufacture of high-precision bandgap reference circuits.

Description

High precision bandgap reference circuit

technical field

The invention relates to the field of integrated circuits, in particular to the design of a high-precision, low-offset bandgap reference circuit, specifically, a high-precision bandgap reference circuit.

Background technique

为与温度系数无关的量，

设计得出 $\frac{{\&PartialD;V}_{\mathrm{ref}}}{\&PartialD;T}=\frac{{\&PartialD;V}_{\mathrm{BE}1}}{\&PartialD;T}+\frac{{2\mathrm{KR}}_s}{{\mathrm{qR}}_n}\ln n=0$ 即得到与温度无关的基准电压V_ref，V_ref≈V_BE1+17.2V_T≈1.23V。Figure 1 is a traditional bandgap reference circuit, in which an amplifier is inside the virtual frame. Since the Q2 tube is composed of 8 identical tubes connected in parallel, the current flowing through each tube is 1/8 of the total, then, ${\mathrm{\&Lambda;V}}_{\mathrm{BE}}=V_{\mathrm{BE}1}-{\mathrm{<figure-callout\; id="2"\; label="V\; BE"\; filenames="HDA00001692722300012.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{BE}}=V_T\ln \frac{I}{I_{S1}}-V_T\ln \frac{\mathrm{<figure-callout\; id="2"\; label="I\; n\; S"\; filenames="HDA00001692722300012.png"\; state="\{\{state\}\}">I</figure-callout>}}{n_S}=V_T\ln \mathrm{no}$ where n=8. Therefore, the reference voltage $V_{\mathrm{ref}}={\mathrm{<figure-callout\; id="2"\; label="V\; BE"\; filenames="HDA00001692722300012.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{BE}}+{2\mathrm{IR}}_{\mathrm{the\; s}}=V_{\mathrm{BE}1}+\frac{{2V}_T\ln \mathrm{no}}{R_{\mathrm{no}}}{R}_{\mathrm{the\; s}}.$ VBE1 has a negative temperature coefficient, $V_T=\frac{\mathrm{KT}}{q},$ has a positive temperature coefficient,

is a quantity independent of the temperature coefficient,

designed $\frac{{\&PartialD;V}_{\mathrm{ref}}}{\&PartialD;T}=\frac{{\&PartialD;V}_{\mathrm{BE}1}}{\&PartialD;T}+\frac{{2\mathrm{KR}}_{\mathrm{the\; s}}}{{\mathrm{QUR}}_{\mathrm{no}}}\ln \mathrm{no}=0$ That is, a temperature-independent reference voltage V _ref is obtained, V _ref ≈V _BE1 +17.2V _T ≈1.23V.

However, when the paired MOS transistors in the circuit are not well matched, an offset voltage will be generated, so a solution needs to be found to eliminate this offset voltage.

Contents of the invention

The present invention aims to overcome the deficiencies of the prior art and minimize the influence of the offset voltage. In order to achieve the above-mentioned purpose, the technical solution adopted by the present invention is that the high-precision bandgap reference circuit is composed of PMOS transistors P1, P2, P3, P4, NMOS transistors N1, N2, transistors Q1, Q2, characterized in that the gates of PMOS transistors P1 and P2 are connected, the sources of PMOS transistors P1 and P2 are connected to the power supply, and the drain of PMOS transistor P1 is connected to the input of two CMOS switches. The output terminals of the two CMOS switches connected to the drain of the PMOS transistor P1 are respectively connected to points C and D, and are connected to the drain of the PMOS transistor P1 and the output terminals are connected to the negative and positive clocks of the CMOS switch at point C. The positive and negative clock terminals of the CMOS switch connected to the drain of the PMOS transistor P1 and the output terminal connected to point D correspond to the connection of the pulse signal X2 and the inverse signal of the pulse signal X2 respectively. Phase signal; the output terminals of the two CMOS switches connected to the drain of PMOS transistor P2 are respectively connected to point C and point D, and are connected to the drain of PMOS transistor P2 and the output terminal is connected to the positive and negative terminals of the CMOS switch at point C. The clock terminal is respectively connected to the pulse signal X2 and the inverse signal of the pulse signal X2, and is connected to the drain of the PMOS transistor P2 and the output terminal is connected to the negative and positive clock terminals of the CMOS switch at point D, respectively corresponding to the connection of the pulse signal X2 and the pulse signal X2 Inverted signal; the bases of transistors Q1 and Q2 are connected and connected to point C, the emitter of transistor Q1 is connected to the emitter of transistor Q2 through resistor Rn, and the emitter of transistor Q1 is grounded through resistor Rs; the source of PMOS transistors P3 and P4 The poles are connected to the power supply, the gates of the PMOS transistors P3 and P4 are connected, the drains of the PMOS transistors P3 and P4 are respectively connected to the sources of the NMOS transistors N1 and N2, and the drains of the NMOS transistors N1 and N2 are connected and grounded through the resistor Rt;

The output ends of the two CMOS switches connected to the drain of the PMOS transistor P3 are connected to points A and B respectively, and the negative and positive clock ends of the CMOS switches connected to the drain of the PMOS transistor P3 and the output ends are connected to point A, respectively. The positive and negative clock terminals of the CMOS switch connected to the drain of the PMOS transistor P3 and the output terminal connected to point B correspond to the connection of the pulse signal X1 and the inversion signal of the pulse signal X1 respectively. ;

The output ends of the two CMOS switches connected to the drain of the PMOS transistor P4 are connected to points A and B respectively, and the positive and negative clock ends of the CMOS switches connected to the drain of the PMOS transistor P4 and the output ends are connected to point A, respectively. The negative and positive clock terminals of the CMOS switch connected to the drain of the PMOS transistor P3 and the output terminal connected to point B correspond to the connection of the pulse signal X1 and the inverting signal of the pulse signal X1 respectively. ;

The output ends of the two CMOS switches connected to the drain of the NMOS transistor N1 are respectively connected to points C and D, and the negative and positive clock ends of the CMOS switches connected to the drain of the NMOS transistor N1 and the output ends are connected to point C, respectively. The positive and negative clock terminals of the CMOS switch connected to the drain of the NMOS transistor N1 and the output terminal connected to point D correspond to the connection of the pulse signal X1 and the inverting signal of the pulse signal X1 respectively. ;

The output ends of the two CMOS switches connected to the drain of the NMOS transistor N2 are respectively connected to points C and D, and the positive and negative clock ends of the CMOS switches connected to the drain of the NMOS transistor N2 and the output ends are connected to point C, respectively. The negative and positive clock terminals of the CMOS switch connected to the drain of the NMOS transistor N2 and the output terminal connected to point D correspond to the connection of the pulse signal X1 and the inverting signal of the pulse signal X1 respectively. ;

Points A, B, C, and D are gates of PMOS transistors P1 and P3, and collectors of triodes Q1 and Q2, respectively.

The structure of the CMOS switch is: the source of a PMOS tube is connected to the source of an NMOS tube as an input terminal, the drain is connected and used as an output terminal, the gate of the PMOS tube is a negative clock terminal, and the gate of the NMOS tube is a positive clock terminal.

Technical characteristics and effects of the present invention:

The invention utilizes a clock divided by two to alternately connect each device, so that the offset voltages generated by each device are equal in magnitude, opposite in direction and same in duration within a certain period, and the purpose of eliminating the offset voltage can be achieved.

Description of drawings

Figure 1. Traditional bandgap reference circuit.

Figure 2. Optimized bandgap reference circuit.

Figure 3. Divide-by-two clock waveform.

Figure 4. Internal structure of a CMOS switch.

Figure 5. Inverter circuit.

Detailed ways

Figure 2 shows the optimized bandgap reference circuit structure. Among them, X1 and X2 are frequency-divided clocks by two, and their waveforms are shown in Figure 3. The period of X1 is 1us, and the period of X2 is 2us. Figure 4 shows the internal structure of a CMOS switch. Figure 5 shows the circuit structure of the inverter.

Thus, it can be seen from Fig. 2 that during the periodic change of X1, N1 and N2 are connected to points C and D in turn, and the two branches of N1 and N2 are connected to points A and B in turn. At the same time, during the cycle change process of X2, Q1 and Q2 are connected to P1 and P2 in turn.

With such a design, when there is a mismatch in the circuit, the impact on the output voltage is also a periodic high and low change, which can be regarded as a stable value after the subsequent filter circuit.

Table 1 shows the dimensions of each MOS device in the circuit shown in Figure 2.

Table 2 is the resistance value of each resistor in the circuit shown in Figure 2.

Table 3 shows the device dimensions for the circuit shown in Figure 4.

Table 4 shows the device dimensions for the circuit shown in Figure 5.

When the power supply voltage is 1.5V, the output voltage is stable at 1.232V. At this time, the Q1 and Q2 branch currents are both 14.33uA, the N1 branch current is 537.9nA, and the N2 branch current is 619.2nA.

When the power supply voltage is 3.3V, the output voltage is stable at 1.232V. At this time, the Q1 and Q2 branch currents are both 14.24uA, the N1 branch current is 579.3nA, and the N2 branch current is 638.9nA.

When P1 decreases by 10%, the output voltage value is 1.175V using the circuit structure in Figure 1, and the output voltage value is 1.232V using the circuit structure in Figure 2.

When P1 increases by 10%, the output voltage value is 1.287V using the circuit structure in Figure 1, and the output voltage value is 1.234V using the circuit structure in Figure 2.

It can be seen that the offset voltage can be significantly suppressed by using the circuit structure shown in the present invention.

.Table 1

name W L m name W L m P1 20u 0.4u 4 Q1 1u 1u 1 P2 20u 0.4u 4 Q2 1u 1u 8 P3 10u 1u 3 N1 5u 0.35u 2 P4 10u 1u 3 N2 5u 0.35u 2

Table 2

name Resistance value (unit: ohm) Rs 17500 Rn 3700 Rt 600000

table 3

name W L m P9 5u 0.35u 2 N9 5u 0.35u 2

Table 4

name W L m P10 1.6u 0.35u 1 N10 1u 0.35u 1

Claims (2)

1. A high-precision bandgap reference circuit is made up of PMOS transistors P1, P2, P3, P4, NMOS transistors N1, N2, transistors Q1, Q2, and is characterized in that the gates of PMOS transistors P1 and P2 are connected, and the gates of PMOS transistors P1 and P2 are connected. The sources of P1 and P2 are connected to the power supply, the drain of the PMOS transistor P1 is connected to the input terminals of the two CMOS switches, and the output terminals of the two CMOS switches connected to the drain of the PMOS transistor P1 are respectively connected to points C and D, and The drain of the PMOS transistor P1 is connected and the output end is connected to the negative and positive clock ends of the CMOS switch at point C. The positive and negative clock terminals of the CMOS switch at point D are respectively connected to the pulse signal X2 and the inverse signal of the pulse signal X2; the output terminals of the two CMOS switches connected to the drain of the PMOS transistor P2 are connected to points C and D respectively, The positive and negative clock terminals of the CMOS switch connected to the drain of the PMOS transistor P2 and the output end connected to point C are respectively connected to the pulse signal X2 and the inverting signal of the pulse signal X2, connected to the drain of the PMOS transistor P2 and connected to the output end The negative and positive clock terminals of the CMOS switch at point D are respectively connected to the pulse signal X2 and the inverting signal of the pulse signal X2; the bases of the transistors Q1 and Q2 are connected and connected to point C, and the emitter of the transistor Q1 is connected to the transistor through the resistor Rn The emitter of Q2 and the emitter of transistor Q1 are grounded through the resistor Rs; the sources of PMOS transistors P3 and P4 are connected to the power supply, the gates of PMOS transistors P3 and P4 are connected, and the drains of PMOS transistors P3 and P4 are respectively connected to NMOS transistor N1 , the source of N2, the drains of NMOS transistors N1 and N2 are connected and grounded through the resistor Rt; The output ends of the two CMOS switches connected to the drain of the PMOS transistor P3 are connected to points A and B respectively, and the negative and positive clock ends of the CMOS switches connected to the drain of the PMOS transistor P3 and the output ends are connected to point A, respectively. The positive and negative clock terminals of the CMOS switch connected to the drain of the PMOS transistor P3 and the output terminal connected to point B correspond to the connection of the pulse signal X1 and the inversion signal of the pulse signal X1 respectively. ; The output ends of the two CMOS switches connected to the drain of the PMOS transistor P4 are connected to points A and B respectively, and the positive and negative clock ends of the CMOS switches connected to the drain of the PMOS transistor P4 and the output ends are connected to point A, respectively. The negative and positive clock terminals of the CMOS switch connected to the drain of the PMOS transistor P3 and the output terminal connected to point B correspond to the connection of the pulse signal X1 and the inverting signal of the pulse signal X1 respectively. ; The output ends of the two CMOS switches connected to the drain of the NMOS transistor N1 are respectively connected to points C and D, and the negative and positive clock ends of the CMOS switches connected to the drain of the NMOS transistor N1 and the output ends are connected to point C, respectively. The positive and negative clock terminals of the CMOS switch connected to the drain of the NMOS transistor N1 and the output terminal connected to point D correspond to the connection of the pulse signal X1 and the inverting signal of the pulse signal X1 respectively. ; The output ends of the two CMOS switches connected to the drain of the NMOS transistor N2 are respectively connected to points C and D, and the positive and negative clock ends of the CMOS switches connected to the drain of the NMOS transistor N2 and the output ends are connected to point C, respectively. The negative and positive clock terminals of the CMOS switch connected to the drain of the NMOS transistor N2 and the output terminal connected to point D correspond to the connection of the pulse signal X1 and the inverting signal of the pulse signal X1 respectively. ; Points A, B, C, and D are gates of PMOS transistors P1 and P3, and collectors of triodes Q1 and Q2, respectively. 2. The high-precision bandgap reference circuit as claimed in claim 1, characterized in that, the structure of the CMOS switch is: a PMOS transistor source is connected to an NMOS transistor source and used as an input terminal, and the drain is connected and used as an output terminal , the gate of the PMOS transistor is a negative clock terminal, and the gate of the NMOS transistor is a positive clock terminal.

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