CN102662892A

CN102662892A - FlexRay communication controller

Info

Publication number: CN102662892A
Application number: CN2012100542699A
Authority: CN
Inventors: 康一梅; 马文豪
Original assignee: Beihang University
Current assignee: Beihang University
Priority date: 2012-03-02
Filing date: 2012-03-02
Publication date: 2012-09-12
Anticipated expiration: 2032-03-02
Also published as: CN102662892B

Abstract

The present invention relates to a FlexRay communication controller, mainly comprising protocol modules, an arbitration module and a memory. To better utilize the memory, all protocol modules related to the FlexRay protocol can not directly visit the memory; instead, an internal bus is designed, and all protocols related to the FlexRay protocol visit the memory through an arbitration mechanism in order. To ensure that a host can use the memory preferentially, a bus arbitration strategy of the host preferential visit is added. With the FlexRay communication controller, the problem of shared memory is solved through the arbitration module, and design of a communication controller becomes simpler and more effective.

Description

A kind of FlexRay communication controler

Technical field

The present invention relates to a kind of FlexRay communication controler, especially the design of internal bus arbitration.

Background technology

FlexRay is a kind of of C class In-vehicle networking standard agreement.It is the agreement of being formulated by FlexRay community (FlexRay Consortium).There are 7 core members in these communities: BMW GROUP, BOSCH, Daimler Chrysler, GM, Motorola/Freescale, PHILIPS and VW AG.The communication of FlexRay network has two-forty, determinacy, reliability, dirigibility, failure tolerance etc.; Can satisfy the needs of following advanced automobile high-speed control; FlexRay supports dcs simultaneously, can replenish main in-vehicle network agreement such as CAN, LIN.The FlexRay communication controler be with the FlexRay agreement be standard, communication device with comprehensive collaborative work ability, can be that complicated network provides at a high speed, security and fault-tolerance.

The key of design FlexRay communication controler is the communication issue that solves shared drive.First kind be main frame with the FlexRay communication controler between communicate by letter.The FlexRay communication controler needs the configuration information of main frame, and transmits data to main frame.These configuration informations and data storage are in the internal memory of FlexRay communication controler; Second kind is the communication between inner each module of FlexRay communication controler.Startup, clock synchronization, encoding and decoding etc. are controlled, are waken up in the function protocols having that the FlexRay communication controler provides.These functions are realized by different module that in FlexRay communication controler inside the mode with shared drive between the module is communicated by letter.So the internal bus referee method has directly determined the design of FlexRay communication controler.

Summary of the invention

The objective of the invention is to solve the problem of FlexRay communication controler internal module and main frame shared drive.FlexRay communication controler of the present invention mainly comprises 3 generic modules (Fig. 1, system architecture diagram): protocol module, arbitration modules, internal memory.

Arbitration modules is the core of whole invention, has determined bus arbitration mechanism.It comprises 3 bus selectors (Fig. 4, bus arbitration mechanism figure): address selector (Address_Mux), write data selector switch (Wdata_Mux), write control signal selector switch (Wren_Mux).The input end of each selector switch, control end, output terminal are described below:

The address wire of each protocol module output, write data line, write control signal are respectively as the input end of each selector switch.Each protocol module comprises a commencing signal (start), end signal (end).Wherein the effect of commencing signal is the right to use of application bus, and the effect of end signal is the right to use of abandoning bus, lets other modules use.These commencing signals and end signal are as the control end of each selector switch.When the commencing signal of certain module was 1, this module began to obtain the bus right to use, began internal memory is initiated read-write operation.When its end signal is 1 and commencing signal when being 0, show that this module abandons the bus right to use, make other modules can obtain the bus right to use.Simultaneously, the present invention is in order to make main frame have the right of preferential use internal memory, and the control end of each selector switch has added by the sheet of host computer control selects signal (cs).When it was 1, no matter whether the commencing signal of each internal module was 1, the right to use of bus return main frame all; When it was 0, main frame was abandoned the right to use of bus, and this moment, each module could begin to obtain successively the bus right to use.The output terminal of these buses is the signals after each selector switch is selected, and sends slave unit to.

According to above analysis, president's strategy of the present invention is example with the address selector, and other selector switchs are the same.(Fig. 5 bus strategic process figure) as follows:

1. at first, address selector judge its select signal (CS) if whether be 1. it be 1, show that main frame will preferentially use bus, to obtain the use of slave unit.

2. when the selection signal (CS) of address selector switch was 0, if address selector is not received the commencing signal of main equipment, its acquiescence selected a main equipment to obtain the bus right to use.

When the selection signal (CS) of address selector switch be 0 and the commencing signal of main equipment when being 0, address selector will select corresponding master device (main equipment be meant will access slave module or main frame.Fig. 2 for example) make it obtain the bus right to use.When it used bus, it sent end signal automatically, and slave unit is abandoned in expression, and (slave unit refers to the module of being visited, for example internal memory.Fig. 2 has explained these notions) use.

Public address line (addr), public write data bus (data) and public write control signal (wr) are the output terminals of address selector (Address_Mux), write data selector switch (Wdata_Mux), the corresponding bus selector of write control signal selector switch (Wren_Mux).The output terminal of these selector switchs (is that public address line (addr), public write data bus (data) and public write control signal (wr) are the input signals of internal memory as the input signal of internal memory.Because memory modules must have input signal), the read-write operation of control internal memory.

Internal memory is the storer of FlexRay communication controler, also is the slave unit (Slave) (Fig. 2 is based on the method for attachment of bus) of internal bus.Main equipment can carry out read-write operation to it through the arbitration (Fig. 4, bus arbitration mechanism figure) of bus.Because read data line (rdata) has only a source, so it directly is connected to each sub-module from internal storage location, the module use of confession duty.

The main equipment of internal bus (Master) (Fig. 2 is based on the method for attachment of bus) mainly is each protocol module of FlexRay protocol communication controller the inside.They can initiate operation requests to internal memory.These requests make at a time can only drive the bus access main equipment by a main equipment through the arbitration of bus module, so just are unlikely to take place access conflict.

According to the FlexRay agreement, each main equipment is enjoyed the bus right to use successively.When main frame is abandoned the bus right to use, and remove other internal modules that the agreement control module thinks and do not send commencing signal, at this moment, the agreement control module has the bus right to use.Before the agreement control module got into wakeup process (wakeup process), coding/decoding module sent commencing signal, to obtain the bus right to use.After the agreement control module got into start-up course (startup process), the clock processing module was used bus earlier, and the clock generating module obtains the bus right to use then, is medium Access Control module (Fig. 3, agreement control module schematic diagram) at last.

Description of drawings

Fig. 1 is the system Organization Chart;

Fig. 2 is the method for attachment based on bus;

Fig. 3 is an agreement control module schematic diagram;

Fig. 4 is bus arbitration mechanism figure;

Fig. 5 is bus strategic process figure;

Fig. 6 preferentially uses bus for CPU;

Fig. 7 at first uses bus for module 1.

Embodiment

The embodiment of bus arbiter is as follows.Here only provided the implementation method of write address selector switch (addr_mux), other 2 bus selectors similar (write data selector switch (Wdata_Mux), write control signal selector switch (Wren_Mux)).Address selector is according to the commencing signal and the end signal of each internal module, and selection signal (cs) selects the address wire of one of them module to link to each other with the public address line.

Fig. 6 is that CPU preferentially uses bus.In first clock period, CPU, module 1 are 0 all with the commencing signal of module 2, have only CPU to send address signal (CPU_Addr).But,, rather than preserve the address signal of CPU so the public address signal (Addr) of this moment is 0 because the chip selection signal (CS) of CPU is 0.This just representes not have this moment equipment to use bus.Since second clock period one-period to the last, the chip selection signal of CPU (CS) be 1. at this moment the value of public address signal selected the address signal of CPU, also just show and have only this moment CPU to obtain the bus right to use.To the 3rd clock period, the commencing signal of module 1 (Start_1) is 1, shows that module 1 also hopes to obtain the right to use of bus.But this moment, the chip selection signal (CS) of CPU was 1, and the public address signal is preserved the address signal of CPU always.So can not making, the commencing signal of module 1 oneself obtains the bus right to use.Just realized that so also CPU preferentially uses internal memory through bus.

Fig. 7 is that module 1 is at first used bus, abandons bus then and makes module 2 obtain the bus right to use.In the whole clock period, the chip selection signal of CPU is 0 to show that CPU can not obtain the bus right to use.In first clock period, module 1 all is 0 with the commencing signal of module 2, shows that they do not apply for using bus.At this moment, the address signal of first module has value, but because its commencing signal is 0, so the value of public address signal (Addr) is 0, expression does not have equipment to obtain the bus right to use.Second period began to the 3rd cycle, and the commencing signal of module 1 (Start_1) becomes 1, represented this module application use bus.In this time, the public address signal has selected the address value of module 1 to show that module 1 has obtained the bus right to use.During module 1 obtained the bus right to use, CPU attempted to send address signal (Aaddr) to grab the bus right to use through changing.But the chip selection signal of CPU (CS) is 0, so the preservation of the value of public address signal is the address value of module 1 rather than the address value of CPU.Finally, the right to use of bus is module 1 rather than CPU always.

The 4th cycle, the end signal of module 1 (End_1) become 1 and its commencing signal become 0 from 1, this representation module 1 uses bus to finish, and begins to abandon the bus right to use.At this moment, the commencing signal of module 2 (Start_2) becomes 1 from 0, shows the module 2 beginning application bus rights to use.But the address signal of module 2 (Mod_2_Addr) does not change, thus this moment the public address signal value still preserve the value of last time, but this does not represent to have equipment to use bus because these data are junk data at this moment.The 5th cycle, the address signal of module 2 begins (Mod_2_Addr) value of sending, and is reflected on the public address signal (Addr), because the bus user of this moment is a module 2 at once.

Claims

1. FlexRay communication controler, it is characterized in that: this communication controler comprises three generic modules: protocol module, arbitration modules, internal memory;

Said arbitration modules comprises 3 bus selectors: address selector, write data selector switch, write control signal selector switch, and the input end of each selector switch, control end, output terminal are described below:

The address wire of each protocol module output as the write data line of the input end of address selector, each protocol module output as the write control signal of the input end of write data selector switch, each protocol module output input end as the write control signal selector switch; Each protocol module comprises a commencing signal, end signal, and wherein the effect of commencing signal is the right to use of application bus, and the effect of end signal is the right to use of abandoning bus; Said commencing signal and end signal are as the control end of each selector switch;

The annexation of arbitration modules and internal memory is: the output terminal of address selector as the output terminal of the public address signal of internal memory, write data selector switch as the output terminal of the public write data signal of internal memory, write control signal selector switch public write control signal as internal memory; And the reading data signal of internal memory is as the data input signal of each protocol module;

The annexation of arbitration modules and main frame is: the chip selection signal of main frame is as the part that enables control end of arbitration modules; Come the control bus arbitration with the commencing signal and the end signal acting in conjunction of protocol module; The address signal of main frame is represented the address of main frame as the input of address selector; On behalf of main frame, the write data signal of main frame will write the data of internal memory as the input signal of write data selector switch, and the read-write control signal of main frame shows that as the input of write control signal selector switch main frame is to read or writing internal memory; And the reading data signal of internal memory is equally as the data input signal of main frame.

2. FlexRay communication controler according to claim 1 is characterized in that: simultaneously a main equipment access memory can only be arranged; When the commencing signal of certain module was 1, this module began to obtain the bus right to use, began internal memory is initiated read-write operation; When its end signal is 1 and commencing signal when being 0, show that this module abandons the bus right to use, make other modules can obtain the bus right to use; Simultaneously, in order to make main frame have the right of preferential use internal memory, the control end of each selector switch has added by the sheet of host computer control selects signal; When this sheet selected signal to be 1, no matter whether the commencing signal of each internal module was 1, the right to use of bus return main frame all; When this sheet selected signal to be 0, main frame was abandoned the right to use of bus, and this moment, each module could begin to obtain successively the bus right to use; The output terminal of these buses is the signals after each selector switch is selected, and sends slave unit to.

3. FlexRay communication controler according to claim 1 is characterized in that: when the chip selection signal CS of arbitration modules was 1, arbitration modules was selected the user of main frame as slave unit, and (CS) becomes 0 up to this chip selection signal; On the contrary, if chip selection signal CS be 0 and the commencing signal of protocol module also be 0, the main equipment that arbitration modules will be selected to give tacit consent to uses slave unit; When the commencing signal of protocol module is 1 and chip selection signal (CS) when also being 0, arbitration modules will be selected the user of corresponding protocols module as slave unit; After this protocol module was finished using, it initiatively sent end signal and makes the right to use of abandoning bus itself.