CN101228743A

CN101228743A - Flexray communication module, flexray communication controller and a method for transmitting messages between a flexray communication connection and a flexray subscriber

Info

Publication number: CN101228743A
Application number: CNA2006800264291A
Authority: CN
Inventors: J·尼沃尔德; M·伊哈勒
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2005-07-21
Filing date: 2006-07-20
Publication date: 2008-07-23

Abstract

The invention relates to a flexray communication module (100) for coupling a flexray message transmitting communication (101) to a subscriber (102) to which said flexray communication module (100) is associated by means of the subscriber interface (107). The aim of the invention is to design the flexray communication module (100), which optimally supports the communications in the flexray network. For this purpose, the flexray communication module (100) comprises a device (105) for storing messages transmitted or transmissible between the subscriber (102) and the flexray transmitting communication (101) and a state machine, which, in order to control the transmission of messages, predefines and/or calls for sequences concerning information related to the storage of messages in the device (105), the extraction of messages contained in the device (105) and to the transmission thereof.

Description

FlexRay communications component, FlexRay communication controler and be used for FlexRay communicate to connect and FlexRay user between the method for message transfer

Prior art

The present invention relates to be used for FlexRay is communicated to connect the FlexRay communications component that is coupled with the user who distributes to the FlexRay communications component by user interface, wherein communicate to connect message transfer via described FlexRay.

The invention still further relates to the method that is used for message transfer between FlexRay user and FlexRay communicate to connect, wherein FlexRay communications component and described communicating to connect connect and described user is connected on the described communications component via user interface.

At last, the present invention relates to have the FlexRay communication controler of the described type FlexRay communications component that is used to realize described type method.

By means of communication system and bus system, also promptly communicate to connect the networking that makes control appliance, transducer and executive component recent years during at the modernized motor vehicle of structure or also in machine-building, particularly sharply increase in machine tool field and in automation.Can realize by function being assigned to the cooperative effect on a plurality of control appliances at this.In the case, mention distributed system.Communication between each station more and more by bus system, be that communication system takes place.Message volume on bus system, visit and reception mechanism and Error processing are regulated by agreement.To this known agreement is the FlexRay agreement, wherein at present based on FlexRay protocol specification v2.0 or v2.1.FlexRay be particularly useful in the motor vehicle fast, deterministic and fault-tolerant bus system.The FlexRay agreement is according to time division multiple access (Time DivisionMultiple Access, TDMA) method work, wherein giving parts, be user or the fixing time slot of distribution of messages waiting for transmission, wherein said parts, is that user or message waiting for transmission have the exclusiveness visit to communicating to connect.At this, described time slot repeats with the circulation of determining, making to calculate to a nicety transmits described message on described bus the moment and certainty ground carry out bus access.In order to be used for the bandwidth of message transfer on bus system best, FlexRay is divided into static and dynamic part with described circulation.At this, the static part that fixing time slot is positioned at bus cycle when beginning.In dynamic part, time slot is dynamically allocated.Wherein now respectively only for the of short duration time, be that so-called mini-slot is realized the exclusiveness bus access.Only when in mini-slot, carrying out bus access, prolong the required time just for described time slot.Therefore, thus only when needing bandwidth really, bandwidth consumed.At this, FlexRay via the physical route of two separation to be the data rate communications of 10MBit/s to the maximum.At this, two channels are corresponding to the physical layer of OSI (Open System Interconnection Reference Model (Open SystemsInterconnection Refference Model)) layer model particularly.Described two channels are mainly used in redundant and therefore fault-tolerant transmission of messages now, yet also can transmit different message, so data rate is doubled.But also can be with lower data rate operation FlexRay.

In order to realize synchronous function and, the distributed elements in communication network, be that the user needs base when public, so-called length of a game by the closely-spaced bandwidth of optimizing between two message.For asynchronous, synchronization message is transmitted in the static part of circulation, wherein so corrects the local zone time of parts by special algorithm according to the FlexRay standard, makes all local clocks and global clock synchronous operation.

FlexRay network node or FlexRay user or main frame comprise user processor, be host-processor, FlexRay controller or communication controler and under the monitoring bus situation bus escort.At this, host-processor, be that user processor provides and handle the data of being transmitted via the FlexRay communication controler.For the communication in the FlexRay network, message or message object can be for example to dispose until 254 data bytes.

Now task is, FlexRay is provided communications component, and described FlexRay communications component is supported communication in the FlexRay network in the mode of the best.

Advantage of the present invention

The FlexRay communications component of all features by having claim 1, by advantageously solving described task according to the FlexRay communication controler of claim 6 and by method according to claim 7.Communications component according to the present invention is characterised in that, for message transfer the user and between communicating to connect, be provided for the device of storing message, wherein pass through state machine control transmission in this wise, make and predesignate or call by state machine with the information-related sequence of predesignating that is used to store with message transfer.

Advantageously, in communications component, connect up to state machine and or connect up to described sequence with hardware mode regularly with hardware mode regularly.

Alternately, in the FlexRay communications component, state machine also can freely be programmed by the user via user interface.

Particularly advantageously be that described information comprises access type and/or access mode and/or reference address and/or size of data and/or to the control information of data and/or the information that at least one is used for protected data.

Described advantage equally also is applicable to the FlexRay device that has the FlexRay communications component, wherein said FlexRay communications component be used for coupled transfer message via FlexRay communicate to connect, wherein said device is connected the user via user interface with communications component, it is characterized in that, for message transfer between user and communications component, be provided for the device of storing message, wherein pass through state machine control transmission in this wise, make and predesignate or call by this state machine with the information-related sequence of predesignating that is used to store with message transfer.

Described advantage is equally applicable to the method in order to message transfer, wherein Flexray communications component and FlexRay communicate to connect and are coupled, wherein communicate to connect message transfer by described FlexRay, wherein said device is connected the user via user interface with communications component, it is characterized in that, for message transfer between user and communications component, described message stores can be used for the device of storing message, wherein pass through state machine control transmission in this wise, make and predesignate or call by state machine with the information-related sequence of predesignating that is used to store with message transfer.

Advantageously, the FlexRay communications component that the FlexRay as physical layer of being used for being coupled communicates to connect is illustrated with the user who distributes to the FlexRay communications component at the FlexRay network, wherein via described FlexRay Network Transmission message.At this, the FlexRay communications component advantageously comprises first device that is used to store the message that at least a portion transmits with second device that is used to be connected first device and described user and be used to be connected FlexRay and communicate to connect, be the physical layer and first the 3rd device that installs.

At this, first device advantageously comprises message manager, is message processor and message memory that wherein message manager is in the control of bearing the data path of first and second devices aspect the data access of message memory.At this, the message memory of first device reasonably is divided into head section and data segment.

Advantageously, in order to be tied to main frame, to be FlexRay user or host-processor, second device comprises input buffer storage and output port buffer memory, wherein or input buffer storage or output port buffer memory or best two memories in preferred form of implementation, be divided composition buffer storage and shadow memory (Schattenspeicher) respectively, described minute buffer storage and shadow memory are read-only and/or write in the mode that replaces respectively, guarantee data integrity thus.The alternative expression of corresponding minute buffer storage and affiliated shadow memory is read or write can be advantageously by exchanging corresponding visit or realizing by the swapping memory content.

At this, if each branch buffer storage and each shadow memory design like this, make and can store each data field and/or the header field of two FlexRay message, then be favourable.

In order to be complementary with different user or main frame more without a doubt, second device comprises interface module, described interface module is formed by the specific subassembly of user with the subelement that the user has nothing to do, and makes only must change the specific subelement of user and so flexibility of always improving the FlexRay communications component for user's coupling.At this, subassembly also can be in interface module inside respectively with form of software, be that each subelement is realized as software function.

According to the redundant transmission paths under the FlexRay situation, the 3rd device advantageously comprises first interface module and second interface module and is divided into two data paths that have two data directions respectively in its side.Reasonably, the 3rd device also comprises first and second buffer storage, so that consider two data paths and two data directions of difference.At this, also so design first and second buffer storage here, make and can store each data field at least of two FlexRay message.Advantageously, each interface module of the 3rd device comprises shift register and FlexRay protocol state machine.

By FlexRay communications component according to the present invention, can support FlexRay protocol specification, particularly v2.0 or v2.1 and thereby for example configurable fully until 128 message or message object.But, be used for the message object of coming storing different numbers according to the size of the respective data field of message or data field at this message memory that obtains flexible configuration.So therefore can dispose message or message object in an advantageous manner with different length data field.At this, in an advantageous manner message memory is configured to FIFO (first in first out (first in-firstout)), obtain configurable reception FIFO.Every message in memory or each message object can be configured to reception memorizer object (reception buffer), transmission memory object (transmission buffer) or be the part of configurable reception FIFO.Similarly, it is possible in the FlexRay network acceptance of frame ID, channel id and cycle counter being filtered.Therefore, reasonably also network enabled management.In addition, being advantageously provided the maskable module interrupts.

The feature that other advantage and favourable expansion scheme accessory rights require and from specification, drawing.

Description of drawings

Figure according to ensuing accompanying drawing further explains orally the present invention.Wherein:

Fig. 1 illustrates communications component and its binding to physical layer (Anbindung), promptly communicates to connect and communicates by letter or the host subscriber in the mode of schematic diagram;

Fig. 2 at length illustrates the particular implementation form and the binding thereof of the communications component of Fig. 1;

Fig. 3 illustrates the structure according to the message memory of the communications component of Fig. 1 or 2;

Fig. 4 to 6 is illustrated in the structural system of data access on the direction of the message memory from user to the communications component and the schematic views of process;

The structural system of data access and the schematic views of process on Fig. 7 to 9 is illustrated in from the message memory of communications component to user's direction;

Figure 10 illustrates the message manager of communications component and the finite state machine that is comprised therein that is schematically shown;

The respective data path that Figure 11 schematically illustrates the element of communications component and user once more and controlled by message manager;

Figure 12 illustrates the visit that relates to the data path in Figure 11 and distributes;

The simplification that Figure 13 illustrates the user interface between communications component and user realizes;

The state machine of the present invention that Figure 14 is illustrated in the flow chart to be described; And

Figure 15 illustrates state according to the state machine of Figure 14 at concrete buffer access.

Embodiment

Fig. 1 schematically illustrates FlexRay communications component 100, is used for that user or main frame 102 are tied to FlexRay and communicates to connect 101, is the physical layer of FlexRay.For this reason, FlexRay communications component 100 via connect 107 be connected with user or user processor 102 with via be connected 106 with communicate to connect 101 and be connected.In order to bind without a doubt aspect the data integrity aspect the transmission time He on the other hand on the one hand, in the FlexRay communications component, schematically distinguish three kinds of devices basically.At this, first device 105 is used for storage, especially at least a portion of clipbook (Zwischenablage), message waiting for transmission.Second device 104 is access between the user 102 and first device 105 via connecting 107 and 108.Similarly, the 3rd device 103 is access between the user 101 and first device 105 via connecting 106 and 109, can realize neatly data being input to first device 105 as message, the particularly part of FlexRay message thus or from its output when guaranteeing data integrity under the optimum speed situation.

In Fig. 2, with the form of preferred implementing form described communications component 100 is shown in more detail once more.Similarly, corresponding connection 106 to 109 is shown in further detail.At this, the interface module that second device 104 comprises input buffer storage or input buffer storage 201 (input buffer IBF), output port buffer memory or output buffer storage 202 (output buffer OBF) and is made up of two

parts

203 and 204, wherein subassembly 203 is that the user has nothing to do and second subassembly 204 is that the user is specific.The specific subassembly 204 of user (client CPU interface (Customer CPU Interface), CIF) host CPU 102 that the user is specific, be that the specific user of client is connected with FlexRay communications component 100.For this reason, bidirectional data line 216, address wire 217 and control input 218 are set.Similarly, with 219 interruption output is set.Subassembly 203 (the universal cpu interface that subassembly 204 that the user is specific and user have nothing to do, GIF) connect, that is to say, that the FlexRay communications component that is also referred to as FlexRay IP module has is general, be public cpu i/f, on described interface via the specific subassembly of corresponding user, be that client CPU interface CIF can connect a large amount of different specific host CPUs of client.Thus, must only change subassembly 204 according to the user, this just means obviously lower expending.

Input buffer storage or input buffer storage 201 can be constructed in a memory assembly or in the memory assembly that is separating with output port buffer memory or output buffer storage 202.At this, input buffer storage 201 is used for intermediate storage message and is used to be transferred to message memory 200.At this, preferably so construct the input buffering assembly, make this input buffering assembly can store two complete message, described message is made up of the head section (Header Segment) that especially has configuration data and data segment or payload section respectively.At this, input buffer storage is configured in the mode of two parts (branch buffer storage and shadow memory), two parts that thus can be by alternately writing input buffer storage or replace the transmission of quickening between user CPU 102 and message memory 200 by visit.Similarly, output buffer storage or output port buffer memory (output buffer (Output-Buffer) OBF) are used for 30 intermediate storage message and are used for being transferred to user CPU102 from message memory 200.At this, also so design output buffer 202, make and can store two full message, described full message by head section that especially has configuration data and data segment, be that the payload section is formed.Here, output buffer storage 202 also is divided into two parts, i.e. branch buffer storage and shadow memory, thus here also can be by alternately reading two parts or replacing the transmission of quickening between user or host CPU 102 and message memory 200 by visit.Second device of being made up of piece 201 to 204 104 is connected as shown with second device 105.

Device 105 is made up of message manager 200 (message processor (Message Handler) MHD) and message memory 300 (message RAM).The data passes between input buffer storage 201 and output buffer storage 202 and the message memory 300 is checked or be controlled to message manager.This message manager is checked just the samely or is controlled on the other direction transfer of data via the 3rd device 103.Message memory preferably is implemented as single port RAM.This RAM memory with configuration data and status data storing message or message object, be real data.The accurate structure of message memory 300 further illustrates in Fig. 3.

The 3rd device 103 is made up of piece 205 to 208.Corresponding to two channels of FlexRay physical layer, device 103 is divided into two data paths with each two data direction.This represents by connecting 213 and 214, wherein two data directions is shown, is used for receiving the RxA of (RxA) and transmission (TxA) and TxA and for channel B RxB and TxB is shown for channel A.Represent optional two-way control input end with connecting 215.The binding of the 3rd device 103 realizes via second buffer storage 206 via first buffer storage 205 with for channel A for channel B.These two buffer storage (instantaneous buffer RAM:RAM A and RAMB) are with acting on from the intermediate store of (or to) first device 105 transmission data.Corresponding to two channels, these two buffer storage 205 are connected with 208 with interface module 207 respectively with 206, and described interface module comprises FlexRay protocol controller or the bus protocol controller of being made up of transmission/reception shift register and FlexRay protocol finite state machine.Therefore, two

buffer storage

205 and 206 as intermediate store be used for the shift register of interface module or FlexRay

protocol controller

207 and 208 and message memory 300 between transmit data.Here advantageously also by each

buffer storage

205 or 206 storage data fields, i.e. the payload section or the data segment of two FlexRay message.

Represent length of a game unit (Global Time UnitGTU) with 209 in this external communications component 100, described length of a game is responsible for being presented in the unit length of a game's grating (Zeitraster) among the FlexRay, is Mikrotick (little beat) μ T and Makrotick (grand beat) MT.Similarly, the fault tolerant clock of regulating cycle counter via length of a game unit 209 is synchronously with in the check of the time flow of the static state of FlexRay and dynamic segment.Represent general-purpose system control (system's universal controller (System Universal Control) SUC) with piece 210, by described operational mode by system control device check and control FlexRay communication controler.Wake (Wakeup) up, start (Startup), integrated or integrated, normal operation (normaloperation) and passive operation (passive operation) belong to this again.

Piece 211 illustrates network and mismanage (Network and Error ManagementMEM), as described in FlexRay protocol specification v2.0.At last, piece 212 illustrates interruption controls device (Interrupt Control INT), and the interruption output 219 of user CPU 102 is led in described interruption controls device management state and wrong interrupt identification (status and error interrupt flags) and check or control.In addition, piece 212 bags are used for absolute and relative timer or the timer that generation time interrupts or timer interrupts.

For the communication in the FlexRay network, message object or message (message buffer) can be used until 254 data bytes and dispose.Message memory 300 is message RAM memory (message RAM) especially, and described message RAM memory for example can be stored until maximum 128 message object.The all functions that relate to processing or administrative messag self all are achieved at message manager or message processor 200.This for example be accept to filter, in two FlexRay

protocol controller pieces

207 and 208 and message manager 300, be pass-along message and check sending order and provide configuration data or status data between the message RAM.

Outer CPU, be that the ppu of user processor 102 can be via the direct register of visit FlexRay communications components of the specific part 204 of user interface and user.At this, use a plurality of registers.Use these registers, in order to configuration and control FlexRay protocol controller, be

interface module

207 and 208, message manager (message processor MHD) 200, length of a game unit (Global Time Unit GTU) 209, general-purpose system controller (the general purpose controller SUC of system) 210, network and mismanage unit (Network and ErrorManagement Unit NEM) 211, interrupt control unit (Interrupt Controller INT) 212 and to message RAM, be the visit of message memory 300 and show corresponding state.In Fig. 4 to 6 and 7 to 9, at least also further inquire into these portions of registers.This described FlexRay communications component of the present invention can be realized the simple conversion of FlexRay standard v2.0 or v2.1, can produce simply thus to have functional ASIC of corresponding FlexRay or microcontroller.

In Fig. 3, describe division in detail to message memory 300.Desired functional according to the FlexRay protocol specification for the FlexRay communication controler needs the message (reception buffer) of message memory in order to message (transmission buffer) to be sent to be provided and to store errorless reception.The FlexRay agreement allows to have data field, is that payload field is the message of 0 to 254 byte.Just as shown in FIG. 2, message memory is the part of FlexRay communications component 100.Next the method for Miao Shuing and corresponding message memory have been described particularly under the situation of using random access memory (RAM) to sent the storage of message and received message, wherein by mechanism according to the present invention possible be, predesignate the size message memory in the storage variable number message.At this, the quantity of storable message depends on the size of the data field of each message, can minimize on the one hand the size of needed memory thus and the size of the data field of restriction of message not, and realizes the optimum utilization to memory on the other hand.Next, should further describe especially based on the variable division of the message memory of RAM for the FlexRay communication controler now.

In order to implement, exemplarily predesignate the storage depth of predesignating (m, n are natural number) that message memory has wide and m the word of the word of determining of n bit (for example 8,16,32 or the like) now.At this, message memory 300 is divided into two sections, i.e. head section (HeaderSegment) HS and data segment DS (payload portions, payload section).Therefore, every message is carried out header field HB and data field DB.Therefore, be

message

0,1 to k (k is a natural number) header field HB0, HB1 to HBk and data field DB0, DB1 to DBk in addition.Therefore in message, between first and second data, distinguish, wherein first data corresponding to about the configuration data of FlexRay message and/or status data and be stored respectively header field HB (HB0, HB1 ... HBk).Corresponding to second data of the authentic data that should be transmitted correspondingly be stored data field (DB0, DB1 ... DBk).Therefore, produce first data area (measuring with bit, byte or memory word) and produce second data area (similarly measuring with bit, word or memory word) for second data of message for first data of every message, wherein second data area of every message may be different.Division between head section HS and data segment DS is variable in message memory 300 now, that is to say not have the boundary of predesignating between described territory.According to the present invention, the division between head section HS and data segment DS is depended on second data area that the quantity k of message and message or all k message amounts to, is the scope of authentic data.According to the present invention, directly distribute pointer element or data pointer DP0, DP1 to DPk respectively for now configuration data KD0, the KD1 to KDk of corresponding message.In specific expansion scheme, distribute the memory word of fixed qty, be two for each header field HB0, HB1 to HBk here, make configuration data KD (KD0, KD1, ... KDk) and pointer element DP (DP0, DP1 ... DPk) always be stored together in header field HB.Head section HS with header field HB is right after the data segment DS that is used to store real message data D0, D1 to Dk, the quantity k that the size of wherein said head section HS or first data area depend on message to be stored.Described data segment (perhaps data division) DS depends on the corresponding data scope of stored message data in its data area, at these six words in DB0 for example, among the DB1 word and in DBk 30 two words.Therefore, respective pointer element DP0, DP1 to DPk always point to beginning, promptly point to the initial address of corresponding data territory DB0, DB1 to DBk, deposit

corresponding message

0,1 data D0, D1 to Dk to k in described data field.Therefore, the division of message memory between head section HS and data segment DS is variable, and depends on the corresponding data scope of the quantity of message itself and message and therefore depend on the second total data area.If dispose less message, head section is less so, and becomes idle territory can be used as the replenishing of data segment DS that is used to store data used in message memory.Can guarantee that by this changeability best memory makes full use of, thereby to use less memory also be possible.Idle data segment FDS, particularly its size similarly depends on the combination of quantity k of the message of being stored and corresponding second data area of message, thereby is minimum and even may is 0.

Except using the pointer element, also may be with first and second data, be configuration data KD (KD0, KD1, ... KDk) with real data D (D0, D1, ... Dk) deposit, make the order of header field HB0 to HBk in head section HS identical respectively with the order of data field DB0 to DBk in data segment DS with the order that can predesignate.So in some cases even can abandon the pointer element.

In special expansion scheme, give message memory assignment error identification generator, particularly parity generator element and wrong identification checker, particularly parity bit verification element, in order to can be exactly by every memory word or every territory (HB and/or DB) especially as check digit deposit together verification and, guarantee the correctness of the data of in HS and DS, being stored.Other check identification, for example CRC (cyclic redundancy check (CRC) (Cyclic Redundancy Check)) or also have more powerful identification, be to imagine as ECC (error code is proofreaied and correct (Error CodeCorrection)).Therefore determine to be allocated to out following advantage at message memory:

The user can be in when programming decision, and whether he wants to use the message with small data field of greater number or him whether to want to use the message with big data field of lesser amt.When configuration has the message of the big or small data field of difference, fully use the existing memory space best.The user might be used for different message jointly with data storage areas.

Under the situation of realization communication controler on the integrated circuit, can the size of message memory and demands of applications be complementary, and not change other function of communication controler.

In addition, now according to Fig. 4 to 6 and 7 to 9 further describe the host CPU visit, promptly via the write and read of buffer memory means 201 and the 202 pairs of configuration datas or status data and authentic data.In this purpose be, set up de in this wise, make to guarantee data integrity and guarantee high transmission speed simultaneously about transfer of data.Control to these processes is undertaken by message manager 200, and this will also will further specify in Figure 10,11 and 12 subsequently.

In Fig. 4,5 and 6, at first further the write access of the host CPU of user CPU 102 via 201 pairs of message memories 300 of input buffering end memory passed through in explanation.For this reason, Fig. 4 illustrates communications component 100 again, wherein for open-and-shut reason, only illustrate communications component 100 in this relevant part.This is message manager 200 and two

control registers

403 and 404 of being responsible for flow process control on the one hand, described control register can be arranged at outside the message manager 200 in the communications component 100 as shown, but also can be included among the message manager 200 itself.403 at this expression input request register (input buffering command request register (Input Buffer Command Request Register)) and 404 expression input mask registers (input buffering order mask register (Input Buffer Command MaskRegister)).Therefore, the write access of 102 pairs of message memories 300 of host CPU (message RAM) carries out via the input buffer storage 201 (input buffer (InputBuffer)) that the centre connects.This input buffer storage 201 designs in the mode of dividing or at double mode now, and as minute buffer storage 400 with belong to the shadow memory 401 of branch buffer storage.Therefore can realize the connected reference of message or the message object or the data of 102 pairs of message memories 300 of host CPU as described in the following like that, thereby and guarantee data integrity and quicken transmission.Control to visit is carried out via input request register 403 with via input mask register 404.In register 403, exemplarily be that the width of 32 bits illustrates the corresponding bits position (Bitstelle) in 403 at this with numeral 0 to 31.Be equally applicable to the bit position 0 to 31 in

register

404 and 404.

According to the present invention, now exemplarily, the bit position 0 to 5,15,16 to 21 of

register

403 and 31 obtains special function aspect flow process control.Therefore, but in the bit position 0 to 5 of register 403 typing sign IBRH (input buffering requesting host (InputBuffer Request Host)) as message identifier.Similarly, but in the bit position 16 to 21 of register 403 typing sign IBRS (input buffering request shadow (Input BufferRequest Shaddow)).Similarly, in 403 register position 15 typing IBSYH and in 403 register position 31 typing IBSYS as access identities.Also mark the position 0 to 2 of register 404, wherein in 0 and 1 with other sign of LHSH (payload header part main frame (LoadHeader Section Host)) and LDSH (load data part main frame (Load Data SectionHost)) typing as Data Identification.Described Data Identification at this with the simplest form, promptly constitute as a bit respectively.In the bit position 2 of register 404, write and begin sign with STXRH (be provided with transmission X requesting host (Set Transmission X Request Host)).In addition, describe via the flow process of input buffer now the write access of message memory.

Host CPU 102 writes the data of message to be passed in the input buffer storage 201.At this, host CPU 102 is only write a configuration and a data KD of message for the head section HS of message memory or is only write the authentic data D waiting for transmission of message or write both for the data segment DS of message memory.Which part that should message transfer, be configuration data and/or authentic data, determine by sign LHSH of the particular data in input mask register 404 and LDSH.At this, determine whether a transmission data, be configuration data KD by LHSH (payload header part main frame), determine whether transmit data D by LDSH (load data part main frame).Constitute with the part of buffer storage 400 and the shadow memory 401 that belongs to it in two-part mode and should visit mutually by input buffer storage 201, two other Data Identification zones are set as the homologue (Gegenst ü ck) of LHSH and LDSH, described two other Data Identification zones are now relevant with shadow memory 401.Described Data Identification in the

bit position

16 and 17 of register 404 is represented with LHSS (payload header part shadow) and LDSS (load data part shadow).Thereby, control the transmission course relevant by these with shadow memory 401.

If the beginning bit is set in the bit position 2 of input mask register 404 now or begins to identify STXRH (transmission X requesting host is set), after the difference configuration data waiting for transmission and/or authentic data in successfully having transmitted message memory 300, for corresponding message object the request of transmission (transmission request (TransmissionRequest)) is set automatically so.That is to say, begin to identify STXRH by this and control, particularly begin automatic transmission message object waiting for transmission.

Be to begin to identify STXRS (transmission X request shadow is set) correspondingly for this reason, be included in to its example in the bit position 18 of input mask register 404 and under the simplest situation, also just construct here as a bit for the homologue of shadow memory.The function class of STXRS is similar to the function of STXRH, only relates to shadow memory 1.

If the bit to 0 that host CPU 102 writes input request register 403 with the number of the message object in message identifier, the particularly message memory 300 is in 5, also promptly write according to IBRF-I, exchange the branch buffer storage 400 of input buffer storage 201 and affiliated shadow memory 401 so, perhaps exchange the corresponding visit of 300 pairs of two branch memories 400 of host CPU 102 and message memory and 401, as representing by semicircle arrow.At this, for example also begin data passes, promptly to the transfer of data of message memory 300.Transfer of data itself to message memory 300 is carried out from shadow memory 401.While exchange register area I BRH and IBRS.Similarly, for LHSS and LDSS exchange LHSH and LDSH.Similarly exchange STXRH and STXRS.Thereby, the sign of IBRS Indication message, promptly for this message object number that once transmits, be ongoing transmission or which message object from shadow memory 401, be which zone the message memory has obtained data (KD and/or D) from shadow memory 401 at last.By the sign in the bit location 31 of input request register 403 (at this 1 bit for example again) IBSYS (input buffering have much to do shadow (Input Buffer Busy Shadow)) show just whether carried out the transmission that has shadow memory 401 to participate in.Therefore, for example under the situation of IBSYS=1 just in time under shadow memory 401 transmission and situation just be not at IBSYS=0.This bit IBSYS is for example by writing IBRH, being that bit to 0 in the register 403 is set to 5, in order to show that the transmission between shadow memory 401 and message memory 300 is underway.Finishing after this transfer of data of message memory 300, IBSYS is reset again.

When the data passes of shadow memory 401 is just carried out, host CPU 102 can the message that next is to be passed write in input buffer storage or the branch buffer storage 400.By means of for example another access identities IBSYH in the bit 15 of register 403 (input buffering have much to do main frame), sign can also be by further perfect.If during the transmission between shadow memory 401 and message memory 300 is carried out, when being IBSYS=1, host CPU 102 is just write IBRH, is the bit position 0 to 5 of register 403 that the IBSYH in input request register 403 is set so.In case ongoing transmission, be the ongoing end of transmission, just begin the transmission (by the request of STXRH, referring to top) of being asked and bit IBSYH is resetted.Bit IBSYS keeps set at whole time durations, in order to show that data are passed to message memory.At this, the bit that all of all embodiment are used also can be constituted as the sign that has more than a bit.For storage and processing economic cause, a bit (Ein-bit) solution is favourable.

So the mechanism of describing allows, host CPU 102 continuously with data passes to the message object of forming by header field HB and data field DB that is arranged in message memory, its prerequisite is that the access speed of 102 pairs of input buffer storage of host PC U is less than or equal to the FlexRay-IP module, is the internal data transfer rate of communications component 100.

In Fig. 7,8 and 9, further explain orally now the read access via output port buffer memory or 202 pairs of message memories 300 of output buffer storage by host CPU or user CPU 102.To this, Fig. 7 illustrates communications component 100 again, wherein for for the purpose of coming into plain view, at this relevant portion of communications component 100 only is shown also.This is message manager 200 and two control registers 703 and 704 of being responsible for flow process control on the one hand, that works is arranged at outside the message manager 300 in the communications component 100 as described for described control register, but also can be included within the message manager 200 itself.At this, 703 expression output request registers (output buffers command request register (Output Buffer Command RequestRegister)) and 704 expression output mask registers (output buffers command mask register (Output Buffer Command Mask Register)).Therefore, the read access of 102 pairs of message memories 300 of host CPU is carried out via the output port buffer memory 202 (output buffer (Output Buffer)) that the centre connects.This output port buffer memory 202 similarly designs in the mode of dividing or at double mode now, and as minute buffer storage 701 with belong to the shadow memory 700 of branch buffer storage.Therefore, also can realize the connected reference of the message of 102 pairs of message memories 300 of host CPU or message object or data just as described in the following like that and therefore guarantee data integrity and the transmission of the acceleration on the rightabout from the message memory to the main frame now at this.Control to visit is carried out via output request register 703 with via input mask register 704.In register 703, also exemplarily corresponding bits position in 703 is shown here for the width of 32 bits with numeral 0 to 31.Be equally applicable to the bit position 0 to 31 in register 704 and 704.

According to the present invention, now exemplarily, the bit position 0 to 5,8 of register 703 and 9,15 and 16 to 31 obtains special function aspect the flow process control of read access.Therefore, but in the bit position 0 to 5 of register 703 typing sign OBRS (output buffer requests shadow (Output Buffer Request Shadow)) as message identifier.Similarly, but in the bit position 16 to 21 of register 703 typing sign OBRH (output buffer requests main frame (Output Buffer Request Host)).But typing sign OBSYS in the bit position 15 of register 703 (the busy shadow (Output Buffer Busy Shadow) of output buffering) is as access identities.Also mark the position 0 and 1 of output mask register 704, wherein in bit position 0 and 1 with other sign of RDSS (read data part shadow (Read Data Section Shadow)) and RHSS (read head part shadow (Read Header Section Shadow)) typing as Data Identification.For example 16 and 17 usefulness RDSH (read data part main frame (Read Data Section Host)) and RHSH (read head part main frame (Read HeaderSection Host)) are provided with other Data Identification in the bit position.Described Data Identification at this also exemplarily with the simplest form, promptly constitute as a bit respectively.Typing begins to identify REQ in the bit position 9 of register 703.In addition, be provided with and switch sign VIEW, this switches sign exemplarily by in the bit position 8 of typing register 703.

Host CPU 102 requests are from the data of the message object of message memory 300, its mode is, described host C UP 102 with the sign of desirable message, promptly particularly the number of desirable message object according to OBRS, also promptly write in the bit position 0 to 5 of register 703.In this case, host CPU can be as in the opposite direction or read-only condition of information or configuration and a data KD, is promptly read or the authentic data D waiting for transmission of read-only message, promptly read or also can read both from data field from header field.Should transmit which part of data, promptly from header field and/or data field, compare by RHSS and RDSS with rightabout at this and to determine.That is to say, RHSS explanation whether should the read head data and the RDSS explanation whether should read real data.

Begin to identify and be used to begin from the transmission of message memory to shadow memory 700.That is to say, if as under the simplest situation, using a bit, so by the bit REQ set in the bit position 0 in the output request register 703 is begun from the transmission of message memory 300 to shadow memory 700 as sign.Ongoing transmission is not only by access identities, show by the bit OBSYS in the register 703 here but also under the simplest situation.For fear of conflict, be not set, when promptly just ongoing transmission not taking place, can then be favourable just yet bit REQ set if having only as OBSYS.So also be implemented in message transmission between message memory 300 and the shadow memory 700 at this.Real flow process now on the one hand with rightabout comparably as following described in Fig. 4,5 and 6 Be Controlled (complementary register takies) and carry out or in flexible program by additional sign, be that switching in the bit position 8 of register 703 identifies VIEW.That is to say, after finishing transmission, bit OBSYS is resetted and can read the message object of asking from message memory now from minute buffer storage 701, be corresponding message its visit and host CPU 102 by the bit VIEW set in the output request register 703 being exchanged branch buffer storage 701 and affiliated shadow memory 700 or exchange.This with opposite transmission direction in Fig. 4 to 6 comparably, also exchange register unit OBRS and OBRH here.Similarly, for RHSH and RDSH exchange RHSS and RDSS.As protection mechanism, can also stipulate here, have only when OBSYS be not set, in when, promptly ongoing transmission not taking place, just can be to bit VIEW set.

Therefore the read access of 102 pairs of message memories 300 of host CPU is carried out via the output port buffer memory 202 that the centre connects.This output port buffer memory and input buffer storage design at double mode or in two-part mode in the same manner, in order to guarantee the connected reference of 102 pairs of stored message object in message memory 300 of host CPU.Here the advantage that also obtains the data integrity of height and quicken to transmit.

By using described input and output port buffer device to guarantee, message memory is not conducted interviews although still can have interruptedly between the wait of host CPU inside modules.

In order to guarantee described data integrity, in communications component 100, carry out transfer of data, particularly transmit by message manager 200 (message processor MHD).Figure 10 illustrates message manager 200 for this reason.Message manager can be by a plurality of state machines or state automata from its functional aspect, be that finite automata, so-called finite state machine (FSM (Finite-State-Machine)) are represented.At this, at least three state machines are set and four finite state machines in special form of implementation.First finite state machine is IOBF-FSM and represents with 501 (I/O buffer status machine (Input/Output Buffer State Mahine)).This IOBF-FSM also can be divided into two finite state machines about each transmission direction of input buffer storage or output port buffer memory, be IBF-FSM (input buffer (Input Buffer) FSM) and OBF-FSM (output buffering (Output Buffer) FSM), maximum thus five state automata (IBF-FSM, OBF-FSM, TBF1-FSM, TBF2-FSM AFSM) can imagine.But, a public IOBF-FSM preferably can be set.At least the second finite state machine be divided in a preferred embodiment here two pieces 502 and 503 and operation about two the channel A and the B of memory 205 and 206, as described to Fig. 2.At this, finite state machine can be set, in order to operate two channel A and B or as in a preferred form with the 502 finite state machine TBF1-FSM that represent (instantaneous buffer 1 (206, RAM A) state machine) is used for channel A and be used for channel B with 503 TBF2-FSM that represent (instantaneous buffer 2 (205, RAM B) state machine).

With the 500 arbitration finite state machines of representing (Arbiter-Finite-State-Machine), be the visit that so-called AFSM is used for controlling in a preferred embodiment three finite state machine 501-503.Data (KD and/or D) are with quartzy or the like that produced or be transmitted communications component from the clock that it was mated by clock apparatus, for example VCO (voltage controlled oscillator (Voltage Controlled Oszillator)), vibration.At this, clock T can produce in assembly or from the outside, for example predesignated as bus clock.Described arbitration finite state machine AFSM 500 alternately gives especially one section clock cycle T of one of three finite state machine 501-503 difference the visit to message memory.That is to say that the operational time is divided on the solicited status automaton according to the access request of each state automata 501,502,503.If carry out the only access request of a finite state machine, so this finite state machine obtain the access time 100%, i.e. all clock T.If carry out the access request of two state automatas, each finite state machine obtains 50% of the access time so.If carry out the access request of three state automatas at last, each finite state machine obtains 1/3 of the access time so.Operational respectively bandwidth is used best.

With 501 first finite state machines of representing, be that IOBF-FSM carries out following action when needed:

-from the data passes of the selected message object of input buffer storage 201 to message memory 300.

-selected message object from message memory 300 is to the data passes of output port buffer memory 202.

The state machine 502 of channel A, be that TBF1FSM carries out following action:

-selected message object from message memory 300 is to the data passes of the buffer storage 206 of channel A.

-from cushioning the data passes of the selected message object of memory 206 to message memory 300.

-to the search of the suitable message object in the message memory, wherein search is used to be stored in the message object (reception buffer (Receive Buffer)) of message received on the channel A and searches for next message object (transmission buffer (Transmit Buffer)) to be sent on channel A under the situation of transmission in the scope of accepting under the situation of reception to filter.

TBF2-FSM, the i.e. action of the finite state machine of channel B in piece 503 similarly.The selected message object of this finite state machine execution from message memory 300 is to the data passes of the buffer storage 205 of channel B with from cushioning the data passes of the selected message object of memory 205 to message memory 300.Function of search also is similar to TBF1-FSM, search suitable message object in message memory, wherein search in the scope of accepting under the situation about receiving to filter be used to be stored in the message object (reception buffer) of message received on the channel B and situation about sending under search next message or message object (transmission buffer) to be sent on channel B.

Flow process and transmission channel are shown in Figure 11 now once more.Three state machine 501-503 are controlled at the respective data transfer between the various piece.At this, represent host CPU with 102 again, represent the input buffer storage and represent the output port buffer memory with 201 with 202.Represent message memory and with 206 and 205 two buffer storage representing channel A and channel B with 300.Interface element 207 and 208 similarly is expressed.With the 501 first state automata IOBF-FSM control datas represented transmit Z1A and Z1B, promptly from input buffer storage 201 to message memory 300 and from message memory 300 to output port buffer memory 202.At this, transfer of data for example is that the data/address bus of 32 bits carries out via having word wide, and wherein every kind of other bit number also is possible.Be equally applicable to the transmission Z2 between message memory and buffering memory 206.This transfer of data by TBF1-FSM, be state machine 502 control of channel A.Transmission Z3 between message memory 300 and buffering memory 205 is by state automata TBF2-FSM, i.e. 503 controls.Here also have the data passes on the data/address bus that example bandwidth is 32 bits, wherein every kind of other bit number also is possible here.Generally, complete message object need a plurality of clock cycle T via the transmission of described transmission channel.Therefore, by moderator, be that AFSM 500 carries out the division to the transmission time about clock cycle T.Therefore figure 11 illustrates the data path between the memory assembly of being checked by message processor 200.The data integrity of the message object of storing in order to guarantee in message memory, should be advantageously at one time only shown in the path, be swap data simultaneously on Z1A and Z1B and one of Z2 and Z3.

In Figure 12, exemplarily illustrate, operational system clock T how by moderator, be that AFSM 500 divides on three solicited status automatons.In the phase I 1, carry out the access request of state automata 501 and state automata 502, that is to say that total time is divided respectively on a fifty-fifty basis on two solicited status automatons.Clock cycle about in the stage 1 this means, state automata 501 obtains visit in clock cycle T1 and T3 and state automata 502 obtains visit in clock cycle T2 and T4.In second stage 2, only carry out visit by state automata 501, make all three clock cycle, promptly share IOBF-FSM from 100% of access time of T5 to T7.In the phase III, carry out the access request of all three state automatas 501 to 503, the feasible trisection that realizes total access time.So moderator AFSM assigns access time for example like this, make that finite state machine 501 obtains visit in clock cycle T8 and T11, finite state machine 502 obtains visit and finite state machine 503 acquisition visits in clock cycle T10 and T13 in clock cycle T9 and T12.At last in the quadravalence section, carry out visit by two the channel A and the B of two state automatas 502 and 503 pairs of described communications components, make realize clock cycle T14 and T16 to finite state machine 502 and in clock cycle T15 and T17 the visit to finite state machine 503 distribute.

Therefore, arbitrate state automaton AFSM 500 is responsible for, and for the situation that proposes to be used for the request of access message memory 300 in three state machines more than one state machine, will visit by clock and alternately distributes on request state machine.This execution mode guarantee stored message object in message memory integrality, be data integrity.If for example host CPU 102 will read message object via output port buffer memory 202, and just received message is written in this message object, ask to read or old state or new state according to which has at first begun so, and the visit in the message object in the message memory itself does not conflict.

Described method makes host CPU in each message object arbitrarily that can read or write in the message memory in service of carrying out, and selected message object is by to the participation of the exchanges data on two channels of FlexRay bus and in the access duration time of host CPU locked (buffer locking (Buffer Locking)).Simultaneously, by change by clock accent (Verschachtelen) visit guarantee stored data in message memory integrality and by abundant use completely bandwidth improve transmission speed.

FlexRay ASC protocol level 2

Relate to the method and apparatus that is used for transmission data between microprocessor (main frame) and ancillary equipment in the scope that preferred the present invention formerly describes now, it for example is used for described ancillary equipment particularly communicating by letter with FlexRay, the so outer controlling combustion engine that is used for.For this transfer of data, only Limited resources is available, that is to say, bandwidth is limited.This is exactly like this under the situation of using serial line interface typically.The interface asynchronous and/or synchronous, particularly serial (ASC) 107 of FlexRay controller makes device 104 or corresponding subassembly 204 be connected with main frame 102 via the cpu i/f 107 as peripheral cell.The implication of institute's information transmitted by agreement, just as described preferably (but being not uniquely) determine by the FlexRay agreement.Usually, this agreement comprises following part:

1) be used for the sign of access mode (read/write),

2) be used for the address of access locations,

3a) be used for the counter of the quantity of data word waiting for transmission, or

3b) sign, its determine whether described address is increased after visit and so when next is visited, be ready to automatically and

4) size of address increment alternatively.

Have part 1) to 4) protocol instructions can be known as simple command.If data waiting for transmission are stored in order or should be stored in order, so this order can be used well and is proved to be effective.Yet if visit can not be carried out with in-order order, these simple commands produce expense (Overhead) so, and the processing of its described expense needs the storage and the computational resource of host CPU.In transfer of data, at first do not belong to valid data but be considered to expense as the data that are used to transmit or store needed additional information.

Now, if must to directly in succession or its conduct interviews irregular address at interval, must always transmit new address information once more with simple command so.

If when transmission individual bit distorted, utilize simple command so or the place of mistake conducted interviews or even exchange read and write.

In order to obtain the higher data throughput, the additional information of visit in being used to transmit the scope of the present invention of data, as for example:

^*Inner state information (for example being ready to/busy condition/bit),

^*About the information on bit field (for example border),

^*The value of predesignating (reducing redundant),

^*The order of predesignating of simple command (reducing redundant),

^*The result of CRC check is in order to guarantee the infallibility of order and address.

In order to improve efficient visit and that also be useful on the write access of mixing outside ranks, with the form of the flow control device (hardwired sequencer (hardwiredsequencer)) of permanent wiring or utilize flow control device able to programme (sequencer able to programme) to set up agreement.The flow control device of permanent wiring consumes less resource (for example memory location) and lower-cost.In addition, the flow control device of permanent wiring has advantage and simpler in application aspect the reliability.In contrast, flow control device able to programme more effective and more flexible than permanent wiring.

Actual analysis by means of the transfer of data of FlexRay communications component is helped, and identification is the sequence and the corresponding simple command of frequent use.Described sequence and corresponding simple command (in mode of permanent wiring or programming) in flow control device are implemented and can be called in the simplest mode.So therefore a plurality of simple commands are combined at least one complex command, wherein each complex command can be called than the simple command utilization instruction still less that is comprised therein.In addition, carry out complex command than carrying out the less resource of single simple command needs that is comprised therein.

Complex command can comprise for example following simple command according to described agreement:

According to example complex command a)

^*The data of transmission (defined in the bit field of order) some make address increment in the address field of predesignating of register,

^*Transmission is fixedly predesignated quantity data in another address field of predesignating of register, makes address increment,

^*Write several bits in the address of register, wherein bit value extracts from the bit field of predesignating by order, and remaining bit is filled with the value of predesignating,

^*Write several bits in the address of another register, wherein bit value extracts from the bit field of predesignating by order, and remaining bit is filled with the value of predesignating,

^*Wait for the end (hardware can be locked) of last sequence.

According to example b) complex command

^*By inquiring that one or more bit waits for the end of last sequence (hardware can be locked),

^*Duplicate internal data in the transmission buffer,

^*Transmission is fixedly predesignated quantity data in another address field of predesignating of register, makes address increment.

When observing from higher level's viewpoint when of the present invention, by the complex command configuration state machine and by the execution of state machine triggers to the simple command that comprised therein.Model for the complex command programmer for example is " reading buffer storage " (read buffer (read buffer)) or " writing buffer storage and configuration " (write buffer and configuration (write buffer andconfiguration)).The example of complicated " reading buffer storage and state " order is a following Example, wherein desirable functional in order to realize, 16 simple command FlxrEray_Read that need be in first or FlxrEray_Write, but unique complex command FlxrEray_AscReadOutputBuffer that only need be in second.

#if(FLXR_INTERFACE_TYPE＝＝Block1)

// distribute data to be used to read from buffer

// request buffer and a data (management)

while(0ul！＝(FlxrEray_Read(0x0714)& 0x00008000ul))

{

；

}

FlxrEray_Write(0x0710，mask_value)；

FlxrEray_Write(0x0714，cmd_value)；

while(((wait_obsys！＝0ul)||(view＝＝1ul))&&

((FlxrEray_Read(0x0714)& 0x00008000ul)！＝0ul))

{

；

}

// make buffer visual

while(0ul！＝(FlxrEray_Read(0x0714)& 0x00008000ul))

{

；

}

FlxrEray_Write(0x0710，mask_valuel)；

FlxrEray_Write(0x0714，cmd_valuel)；

while(((wait_obsys！＝0ul)||(view＝＝1ul))&&

((FlxrEray_Read(0x0714)& 0x00008000ul)！＝0ul))

{

；

}

FlxrEray_ReceivedFrames[msgBudIdx_u32].headerSection.

headerSectionl.valHDR1＝FlxrEray_Read(RDHS1)；

FlxrEray_ReceivedFrames[msgBudIdx_u32].headerSection.

headerSection2.valHDR2＝FlxrEray_Read(RDHS2)；

FlxrEray_ReceivedFrames[msgBudIdx_u32].headerSection.

headerSection3.valHDR3＝FlxrEray_Read(RDHS3)；

FlxrEray_ReceivedFrames[msgBudIdx_u32].reg_MBS.MBS_u32

＝FlxrEray_Read(MBS)；

If // LOF or wrong, then copy data not

// valid data:

FlxrEray_ReceivedFrames[msgBudIdx_u32].Data[0]

＝FlxrEray_Read(RDDS1)；

FlxrEray_ReceivedFrames[msgBudIdx_u32].Data[1]

＝FlxrEray_Read(RDDS2)；

FlxrEray_ReceivedFrames[msgBudIdx_u32].Data[2]

＝FlxrEray_Read(RDDS3)；

FlxrEray_ReceivedFrames[msgBudIdx_u32].Data[3]

＝FlxrEray_Read(RDDS4)；

#elif(FLXR_INTERFACE_TYPE＝＝Block2)

FlxrEray_AscReadOutputBuffer(messageTable[msgBudIdx_u32].

index_u8，& FlxrEray_ReceivedFrames[msgBudIdx_u32].Data[0]，4ul)；

#endif

Need 16 visits altogether in order to carry out single simple command, and only need once to visit in order to carry out complex command.Complex command wherein is not to carry out all single simple commands simply successively in the scope of this function to a certain extent corresponding to a kind of function.Or rather, deposit as complex command considering so to optimize to the execution of single simple command and with the text of optimizing under (in fact determined or theoretic) is about the situation of the knowledge of sequence, make to complex command call and carry out all single simple commands of comparison calling and order is carried out less resource (computational efficiency and memory location) and the less time that needs host CPU.

The example that complex command " is write buffer storage and state " is a following Example, wherein desirable functional in order to realize, 12 simple command FlxrEray_Read that need be in first or FlxrEray_Write, but unique complex command FlxrEray_AscWriteInputBuffer that only need be in second.

#if(FLXR_INTERFACE_TYPE＝＝MLI)

// transmission input buffer storage is to message memory

FlxrEray_Write(WRHS1，FlxrE-

ray_TransmitFrames[i_u32].headerSecrion.headerSection1.valH

DR1)；

FlxrEray_Write(WRHS2，FlxrE-

ray_TransmitFrames[i_u32].headerSecrion.headerSection2.valH

DR2)；

FlxrEray_Write(WRHS3，FlxrE-

ray_TransmitFrames[i_u32].headerSection.headerSection3.valH

DR3)；

// only be used to transmit illusory valid data

if (1ul＝＝cfg)

{

// write the dummy data territory

FlxrEray_Write(WRDS1，FlxrE-

ray_TransmitFrames[i_u32].Data[0])；

FlxrEray_Write(WRDS2，FlxrE-

ray_TransmitFrames[i_u32].Data[1])；

FlxrEray_Write(WRDS3，FlxrE-

ray_TransmitFrames[i_u32].Data[2])；

FlxrEray_Write(WRDS4，FlxrE-

ray_TransmitFrames[i_u32].Data[3])；

}

// wait for until IBSYH (host buffer)=' 0 ' always, because so long as 1, IBCR then

Just can not accept newer command

while(0ul！＝(FlxrEray_Read(IBCR)& 0x00008000ul))

{

；

}

// to command mask set

FlxrEray_Write(IBCM，value)；

// to the target message memory programme and begin the transmission

FlxrEray_Write(IBCR，ibrh & Ox3Ful)；

// in case of necessity, wait for IBSYH (main frame)

while((wait_ibsyh！＝0ul)&&((FlxrEray_Read(IBCR)&

0x00000000ul)！＝0ul))

{

；

}

// in case of necessity, wait for IBSYS (shadow memory)

while((wait_ibsys！＝0ul)&&((FlxrEray_Read(IBCR)&

0x80000000ul)！＝0ul))

{

；

}

#elif (FLXR_INTERFACE_TYPE＝＝ASC)

FlxrEray_AacWriteInputBuffer(bufferIndex，

& FlxrEray_TransmitFrames[i_u32].Data[0]，4ul)；

#endif

Need 12 visits altogether in order to carry out single simple command, in contrast, only need once to visit in order to carry out complex command.Also so optimize execution in this example, make and call and carry out complex command than calling with carrying out all single simple commands needs less resource of host CPU (computational efficiency and memory location) and less time in proper order to single simple command.

By the agreement that is provided with for certain application cases FlexRay, can conduct interviews to transmission and the reception buffer relevant very effectively with host interface 102-107-104.Just as mentioned, form by

part

203 and 204 at this set interface module.At this, so use the result of the transaction analysis of describing in detail, make the most frequent compound action is mapped to the simple command of being made up of a small amount of several components.

In addition, by CRC or so guarded command of parity check, made also before fill order and to find the distortion of write access or address with big probability and therefore to stop to contain wrong execution or mistake spreads.

Draw various advantage now at this:

On the one hand, visit becomes faster, because this agreement has the knowledge about the appropriate address of another state automata form of data placement, access mode and permanent wiring, making to provide data placement, access mode and/or appropriate address automatically, thereby makes these no longer must be provided and no longer must be via interface 107 or at length via connecting 216 to 218 transmission by main frame.

In addition, access mode (read/write) also can be fixedly embedded in this device, so equally no longer must be transmitted just as mentioned.

Instead, the described sequence of fixedly predesignating about described information (data placement, access mode and/or address) only still is called and is equipped with added value.

Now in order to call this sequence of predesignating, utilize following part to expand described agreement according to the present invention: the value of for this reason introducing the type of the sequence of being called, this value exemplarily is known as " access type mark (Access Type Marker); ATM " and describes access type, and next described access type also will be described.

In addition; this agreement is used for information, for example CRC or the parity check of protected data; wherein said protection information constitutes via command component (3 for example initial bytes) at least, does not cause the change of address distortion or access mode (read/write) in order to guarantee possible error of transmission.Distortion in the address field can be discerned by retaking of a year or grade where necessary; This is impossible for address or access mode or " access type mark ".In addition, for example can also realize via the first of described sequence, i.e. order (for example 6 bit CRC) as this protection of CRC or parity check.

Sequence example partly with exemplary illustration of amount of bits:

	ATM	R/W	Addr	Cnt	Reserve	STRXH	CRC
	ATM	R/W	Addr	Cnt	Reserve	STRXH	CRC	Amount of bits	2	1	6	6	2	1	6

	ATM	R/W	Addr	Cnt	CRC
	ATM	R/W	Addr	Cnt	CRC	Amount of bits	2	1	9	6	6

Following properties for the agreement of described interface, to be called client CPU interface (agreement) be exemplary:

^*The operation of half-duplex 8 bit synchronous

^*(9.38MBaud million bauds), synchronously, no parity

^*Bus Clock Rate (BCLK) 32MHz

^*Interrupt request line

^*CRC about command word

^*To byte synchronous verification

^*By main frame to synchronous recovery

^*Asynchronous reset

For example can be in this described agreement for serial line interface convert transmitting and receive data of serial to 32 bit write access, described write access is handled (Transaktion) at the RAM of the internal register of client CPU interface (CIF), communications component nuclear (so-called Core) and for example read on its registers of 11 or 12 bit address space or write by synchronized transaction.

Figure 13 illustrates the simplified structure of ASC client CPU interface 204, described ASC client CPU interface be used to send and receive definite order of predesignating in order to be implemented in communicate to connect 101 and user 102 between transfer of data.Be received in the receiving element 800 by shift register 802 and carry out when the TXD rising edge of clock signal.After the circulation of 8 clocks, the result is received register rx_ and keeps in 806 and the rdy signal is set, in order to notify status machine 808: keep including new message in the register 806 at rx_.Byte of sync in functional block 818 detects (byte of sync verification (byte sync check)) and similarly carries out constantly at this.

As long as transmitting element 810 activates, transmitting element 810 bit ' 0 ' that will come from its shift register 811 places on the RXD line 814 so.Along with each trailing edge of TXD clock signal 804, the reception data are received in the shift register 812 and with the data in the register 812 and continue a displacement field (carrying out so-called displacement).After 8 clocks, the rdy signal is set and state machine 808 can keep register 816 to be loaded into the shift register 812 from tx new data.

Address decoder in the functional block 820 is distinguished between the external memory storage of inner CIF register 822 and communications component 100.State machine 808 before it begins to analyze order, 3 of read command bytes at first.The bit of CRC in piece 826 by verification.Write or read procedure, address visit or simple buffer access according to this command triggers.An end of the visit of identification communication assembly nuclear and the last byte of filling up is provided back then in functional block " end stuff " 824!=0x00, the visit blocking-up ASC order of wherein said communications component nuclear.Under failure condition (CRC 826 or byte of sync 818), state machine 808 enters reset mode (synchronous (resync) again) 828, triggers interrupt requests (IRQ) 830 alternatively and waits for new (synchronous again) 828 synchronously that passes through host CPU 102.

State diagram among Figure 14 illustrates possible transition simplifiedly:

State machine 808 is in IDLE (free time) state after resetting.Send wrong (byte of sync mistake (Byte Sync Error) or crc error (CRC Error)) if identify, state machine 808 is forced to be in the PRE_RESYNC state so.

Simplification action in the corresponding state is:

^*IDLE starts receiver, finishes the ongoing visit of communications component nuclear, removes all counters or the like.

^*PRE_RESYNC closes receiver and transmitter, local signal and state are removed or is resetted.

^*RESYNC_GAP waits for the new synchronous end by main frame.

^*CMD1 waits for the reception to first byte of command word.

^*CMD2 waits for the reception to second byte of command word.

^*CMD3 waits for the reception to the last byte of command word.Check (CRC).

Analyze atm, rw, Buffer_id, addr, Word_cnt and valid data (payload).According to atm and rW, reset mode (return state) set and startup are filled up bit or read first word from communications component nuclear.

^*STUFF sends 0x00 to main frame, as long as eray obusy is high, then to its repetition.(note: E-Ray is the inside address of applicant to communications component 100).

^*LOAD finishes from the ongoing read access of communications component nuclear.Activate transmitter 810.

^*The DAV data are available, duplicate first byte and keep in the register 816 to tx_.Increase addr.

^*READ1 duplicates second byte and keeps in the register 816 to tx_.

^*READ2 duplicates the 3rd byte and keeps in the register 816 to tx_.

^*READ3 duplicates last byte and keeps in the register 816 to tx_.

^*If READ4＞0 then reduces Word_cnt.

^*SBAR reads single buffer (single buffer read access).Address (addr) is changed to 0x700 (head).

^*WRITE1 finishes ongoing write access to communications component nuclear.Duplicate first byte from register rx_ maintenance _ yy.

^*WRITE2 duplicates second byte from rx_ maintenance _ yy.

^*WRITE3 duplicates the 3rd byte from rx_ maintenance _ yy.

^*WRITE4 duplicates last byte from rx_ maintenance _ yy.This word is write in the communications component nuclear.If＞0, then strengthen address (addr), reduce word counter (word_cnt) or activate the IBCM/IBCR visit and connection receiver 800.

^*SBAW finishes ongoing write access to communications component nuclear.Address (addr) is changed to 0x0500 (head).

If realize buffer read access (single buffer read access (Single Buffer Access Read)), during being sent to main frame, byte (F ü llbyte) (' 0 ') must carry out the visit of three communications components nuclear filling up so to single buffer.To the buffer write access (single buffer write access (Single Buffer Access Write)) of single buffer afterwards, the ASC interface must be carried out twice nuclear visit.

Figure 15 illustrates the state machine 808 that is used for communications component nuclear visit (single buffer read and write access).

In order to check the validity of order, come the check command word by means of 6 bit CRC (cyclic redundancy check (CRC)).Order word length 24 bits and form by 18 bits command and 6 bit CRC,

^*D[17:0] data of command word

^*CRC[5:0] CRC of command word

For example use following with 0 initialized multinomial: x for CRC ⁶+ x ⁵+ x ⁴+ x+1.

Adopt the parallel following equation of implementing and derive:

CRC0：＝D17^D15^D14^D13^D9^D8^D5^D4^D3^D1^D0；

CRC1：＝D17^D16^D13^D10^D8^D6^D3^D2^D0；

CRC2：＝D17^D14^D11^D9^D7^D4^D3^D1；

CRC3：＝D15^D12^D10^D8^D5^D4^D2 ；

CRC4：＝D17^D16^D15^D14^D11^D8^D6^D4^D1^D0；

CRC5：＝D16^D14^D13^D12^D8^D7^D4^D3^D2^D0；

The address visit

^*Atm[1:0] access type (access type mark) " 00 "

^*Rw read access (' l ') or write access (' 0 ')

^*Addr[8:0] start address, start from 32 bit words borders (Wortgrenze), 2 kilobytes address spaces

^*Word_cnt[5:0] quantity-1 of word to be passed

^*CRC[5:0] about the CRC of command word

If rw=' 0 ', agreement is waited for 4* (word_cnt+1) byte so, in order to it is write the communications component nuclear as 32 bit words from this address (addr) beginning.If rw=' 1 ', (addr) reads the one 32 bit words from communications component nuclear to the ASC interface from the address so.It is longer that this normal delay with transmission between two bytes circulation is compared the duration.Therefore, main frame must be with at least 2 TxD circulations of direction transfer lag of RXD line (from sending to reception).All ensuing bytes fully normally are transmitted.The ASC interface sends 4 to host CPU ^*(word_cnt+1) byte.After finishing transmission, the ASC interface is waited for next order.

As above-mentioned, access type is described exemplarily now:

Single buffer access (Single Buffer Access)

If host CPU will read from the ASC interface via agreement, the ASC interface must be asked the respective buffer of communications component nuclear so.Replying of this request continued some times and do not finish in the moment of determining.This depends on the present load of communications component nuclear constantly.In order to show to main frame: data are not ready for transmission yet, and the ASC interface sends the last byte (0x00) of filling up during its pending data such as grade.In case DSR, ASC interface just send the last byte of filling up!=0x00.So next byte has been the minimum byte of first data word waiting for transmission.

Only (Header)

^*Atm[1:0] access type (access type mark) " 10 "

^*Rw read access (' l ') or write access (' 0 ')

^*Buffer_ID[5:0] start address of 32 bit words boundaries, 2 kilobytes address spaces

^*If the stxrh buffer is write, transmission requesting host (STXRH) is set in IBCM then

^*Rsv is reserved, institute promising ' 0 '

^*CRC[5:0] about the CRC of command word

If rw=' 0 ', the agreement of ASC interface is waited for 4*4 (head) byte so, it is write communications component examines as 32 bit words in order to beginning from address 0x0500 (input buffer).After last write access, carry out following action by agreement:

1. write atm (LHSH) and stxrh and go up (IBCM) to address 0x0510,

2. write Buffer_ID and go up (IBCR) to address 0x0514.

If rw=' 1 ', the agreement of ASC interface begins to fill up byte (0x00) to the main frame transmission so.The ASC interface needs the described time, in order to ask corresponding head from communications component nuclear.During this is filled up byte and is sent out, carry out following action by agreement:

1. write atm (head) and go up (OBCM) to address 0x0710.

2. write Buffer_ID and REQ and go up (OBCR) to address 0x0714.

3. waiting for becomes low until eray_obusy once more.

During eray_obusy was height, communications component nuclear duplicated corresponding head in the input buffer.

4. write VIEW and go up (OBCR) to address 0x0714.

Now, corresponding in the input buffer is available.Filling up after byte is sent out, the agreement of ASC interface sends 4*4 (head) byte to main frame.After this order was finished, the agreement of ASC interface was waited for next order.

Valid data only

^*Atm[1:0] access type (access type mark) " 01 "

^*Rw read access (' l ') or write access (' 0 ')

^*Quantity+1 of valid data [5:0] 32 bit words

^*Rsv is reserved, institute promising ' 0 '

^*CRC[5:0] about the CRC of command word

If rw=' 0 ', the ASC interface is waited for 4* (valid data+1) byte so, in order to it is write the communications component nuclear as 32 bit words from address 0x0400 (input buffer) beginning.After last write access, carry out following action by the agreement of ASC interface:

1. write atm (LDSH) and stxrh and go up (IBCM) to address 0x0510,

2. write Buffer_ID and go up (IBCR) to address 0x0514.

If rw=' l ', ASC interface send to main frame and fill up byte (0x00).The agreement of ASC interface needs the described time, in order to ask corresponding valid data from communications component nuclear.During filling up byte and being sent out, carry out following action by the agreement of ASC interface:

1. write atm (valid data) and go up (OBCM) to address 0x0710.

2. write Buffer_ID and REQ and go up (OBCR) to address 0x0714.

3. waiting for becomes low until eray_obusy once more.

During eray obusy was height, communications component nuclear duplicated corresponding valid data in the output port buffer device.

4. write VIEW and go up (OBCR) to address 0x0714.

Now, the corresponding valid data in the output port buffer device can be used.Filling up after byte is sent out, agreement sends 4* (valid data+1) byte to main frame.After this order was finished, the agreement of ASC interface was waited for next order.

Valid data and head

^*Atm[l:0] access type (access type mark) " 11 "

^*Rw read access (' l ') or write access (' 0 ')

^*Quantity+1 of valid data [5:0] 32 bit words

^*If the stxrh buffer is write, transmission requesting host (STXRH) is set in ICBM

^*Rsv is reserved, institute promising " 0 "

^*CRC[5:0] about the CRC of command word

If rw=' 0 ', the agreement of ASC interface is waited for 4* (valid data+1) byte so, in order to as 32 bit words it is write the communications component nuclear from address 0x0400 (input buffer) beginning, and wait for 4*4 (head) byte, in order to as 32 bit words it is write the communications component nuclear from address 0x0500 (head) beginning.After last write access, carry out following action by agreement:

1. (LHSH LDSH) goes up (IBCM) with stxrh to address 0x0510 to write atm.

2. write Buffer_ID and go up (IBCR) to address 0x0514.

If rw=' 1 ', the agreement of ASC interface sends to main frame and fills up byte (0x00) so.Agreement needs the described time, in order to ask corresponding valid data and head from communications component nuclear.During filling up byte and being sent out, carry out following action by agreement:

1. write atm (valid data and head) and go up (OBCM) to address 0x0710.

2. write Buffer_ID and REQ and go up (OBCR) to address 0x0714.

3. waiting for becomes low until eray_obusy once more.

During eray_obusy was height, communications component nuclear duplicated corresponding valid data and head in the output port buffer device.

4. write VIEW and go up (OBCR) to address 0x0714.

Now, the corresponding valid data in the output port buffer device and available.Filling up after byte is sent out, the agreement of ASC interface sends 4* (valid data+1+4 (head)) byte to main frame.After this order was finished, the ASC interface was waited for next order.

Again synchronous (synchronous again)

This is not the order that the command word determined is distributed to.By making at least 29 TxD circulations of RxD line for low, host CPU can force the ASC interface to be in synchronous regime again, and needn't control the TxD line actually.Under normal operation (host CPU transmission), if each byte is sent out, then the RxD line will become height.

The ASC interface will stop ongoing operation, remove internal signal and state and wait for next order that will be transmitted by host CPU.

Claims

1. be used for FlexRay communicated to connect the FlexRay communications component (100) that (101) and the user (102) who distributes to FlexRay communications component (100) via user interface (107) are coupled, wherein communicate to connect message transfer via described FlexRay, it is characterized in that, described FlexRay communications component (100) has and is used to be stored in user (102) and FlexRay communicates to connect device that transmitted or message waiting for transmission (105) and state machine between (101), and described state machine is predesignated and/or called and is used at device (105) storing message, be used for from installing (105) message call and being used for of the transmission of the information-related sequence of message transfer in order to control messages.

2. according to the FlexRay communications component (100) of claim 1, it is characterized in that, state machine is connected up with hardware mode regularly.

3. according to the FlexRay communications component (100) of claim 1 or 2, it is characterized in that, described sequence is connected up with hardware mode regularly.

4. according to the FlexRay communications component (100) of claim 1, it is characterized in that state machine can freely be programmed by user (102) via user interface (107).

5. according to the FlexRay communications component (100) of one of claim 1 to 4; it is characterized in that described information comprises access type and/or access mode and/or reference address and/or size of data and/or to the control information of data and/or be used at least one information of protected data.

6. be used for FlexRay communicated to connect the FlexRay communication controler that (101) and the user (102) who distributes to the FlexRay communication controler via user interface (107) are coupled, wherein communicate to connect message transfer via described FlexRay, it is characterized in that: described FlexRay communication controler has the FlexRay communications component (100) according to one of claim 1 to 5.

7. the method that is used for message transfer between FlexRay user (102) and FlexRay communicate to connect, wherein FlexRay communications component (100) is connected with described communicating to connect (101) and described user (102) is connected on the described communications component (100) via user interface (107), it is characterized in that: described user (102) and FlexRay communicate to connect transmitted between (101) and message waiting for transmission by the device (105) of intermediate storage in FlexRay communications component (100) in, wherein predesignate and/or call and be used at device (105) storing message by the state machine of communications component (100), be used for from installing (105) message call and being used for of the transmission of the information-related sequence of message transfer in order to control messages.

8. according to the method for claim 7, it is characterized in that, the definition simple command is used for configuration, is used for triggering or is used to be controlled at user (102) and FlexRay and communicates to connect transfer of data between (101) in FlexRay communications component (100), and wherein each described sequence is carried out the functional of a plurality of simple commands.

9. according to the method for claim 8, it is characterized in that, keeping the functional following of sequence, in view of reducing needed call number, needed user (102) resource (memory and rated output) and/or needed processings duration, in consideration about the order of optimization of getting off of the anticipatory knowledge of transfer of data, the particularly situation of the details of FlexRay communications component (100).

10. according to the method for claim 9, it is characterized in that the order of optimization in real transfer of data or before carrying out sequence.

11. the method according to claim 9 or 10 is characterized in that, based on applied host-host protocol or based on out of Memory, determines anticipatory knowledge in theory in real transfer of data or before carrying out sequence.

12. the method according to claim 9 or 10 is characterized in that, in real transfer of data or before carrying out sequence, determines anticipatory knowledge by analyzing corresponding transfer of data practically.

13. the method according to one of claim 7 to 12 is characterized in that, sequence is connected up regularly or programmes in the FlexRay communications component in real transfer of data or before carrying out sequence.

14. the method according to one of claim 7 to 13 is characterized in that simple command has respectively

-be used for the sign (one or more bit) of access mode (piece read/write, management data and/or valid data);

-be used for the address (a plurality of bit) of access locations;

-be used for the counter of the quantity of data word waiting for transmission; Perhaps

-sign, described sign determine, whether should be after visit via FlexRay communicate to connect (101) transmission data and

-alternatively, Cyclic Redundancy Check or verification and.