CN102655127B - Chip protecting structure and forming method - Google Patents
Chip protecting structure and forming method Download PDFInfo
- Publication number
- CN102655127B CN102655127B CN201110049531.6A CN201110049531A CN102655127B CN 102655127 B CN102655127 B CN 102655127B CN 201110049531 A CN201110049531 A CN 201110049531A CN 102655127 B CN102655127 B CN 102655127B
- Authority
- CN
- China
- Prior art keywords
- layer
- metal wiring
- interlayer dielectric
- protective layer
- sealant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a chip protecting structure comprising an edge sealing structure and a crack arresting structure, wherein the crack arresting structure is adjacent to the edge sealing structure; the crack arresting structure comprises an interlayer dielectric layer, a discrete metal wiring layer which is located in the interlayer dielectric layer and is on the same plane with the surface of the interlayer dielectric layer, a protective layer covering the interlayer dielectric layer and the metal wiring layer, a sealing layer located on the protective layer and a buffering groove located in the protective layer and the sealing layer; and the side wall of the buttering groove is provided with an aluminum side wall located on the protective layer, and the position of the aluminum side wall is opposite to the part of the corresponding metal wiring layer, which is not covered by the sealing layer. In addition, the invention provides a method for manufacturing the chip protecting structure. According to the invention, the inner side wall of the traditional buffering groove is provided with the aluminum side wall for protecting the metal wiring layer, thus, metal copper in the metal wiring layer cannot exposed when the sealing layer is etched to ensure that the adverse effect of the metal copper to a semiconductor device is avoided and the yield of a final chip is increased.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of chip operator guards and formation method.
Background technology
In semiconductor fabrication process, the semiconductor chip of the interconnection structure comprised on semiconductor device and described device can be formed on a semiconductor substrate by techniques such as photoetching, etching and depositions.Usually, multiple chip can be formed on a wafer, finally again these chips be cut down from wafer, carry out packaging technology, form integrated circuit block.
In the process of diced chip, the stress that cutter produce can cause damage to the edge of chip, even can cause chip generation avalanche.Existing in order to prevent chip from sustaining damage when cutting; also there is protection zone in the functional area periphery of chip; the semiconductor device of operator guards in order to defencive function region is provided with in described protection zone; make the functional area of chip from the damage from extraneous factors such as (such as) stress, moisture, pollutions.
Particularly, be 200480021522.4 disclose a kind of chip operator guards with reference to Chinese Patent Application No., chip operator guards comprises edge seal structure and crack stop structures.This patent essentially describes wherein crack stop structures and forms the method for described crack stop structures.
With reference to the semiconductor chip structure schematic diagram in the prior art shown in figure 1 with described operator guards.In the periphery of chip functions device area 1, there is chip cutting region 3; between described chip functions region 1 and described chip cutting region 3; whole described chip functions device area 1 is provided with chip protection zone 2; described chip protection zone 2 has operator guards (not shown), and described chip operator guards effectively can protect described chip functions device area 1 not sustain damage in diced chip process.Further, shown in figure 2, the Semiconductor substrate of usual described chip operator guards comprises edge seal district and crack stop district.Described edge seal district and described crack stop district comprise the stepped construction 21 of more metal layers, and every one deck of wherein said stepped construction 21 to comprise in interlayer dielectric layer 211 and described interlayer dielectric layer 211 and the discrete metal wiring layer 212 flushed with interlayer dielectric layer 211 surface.Be connected by conductive plunger 213 between neighbouring metal wiring layer.Further, in edge seal district, described stepped construction 21 forms protective layer 22, in described protective layer 22, there is the opening exposing metal wiring layer 212, protective layer 22 is formed aluminum metal layer 23, and aluminum metal layer 23 fills full gate mouth, and form sealant 24 on aluminum metal layer 23 and protective layer 22; In crack stop district; described stepped construction 21 is formed on protective layer 22, described protective layer and form sealant 24; buffering groove 25 is also formed, the stress that described buffering groove 25 produces for discharging diced chip, protect IC active circuit district in described protective layer 22 and described sealant 24.
The existing phenomenon easily producing copper metal exposed in metal wiring layer 212 in crack stop district, makes copper metal produce and pollutes, affect the yield of product.At present, good solution is not also had for this problem in prior art.
Summary of the invention
The problem that the present invention solves is to provide a kind of chip operator guards and formation method, prevents copper metal exposed.
For solving the problem, the technical program provides a kind of chip operator guards, comprising: edge seal structure and crack stop structures, and described crack stop structures is adjacent with described edge seal structure; Described crack stop structures comprises interlayer dielectric layer, is positioned at interlayer dielectric layer and the discrete metal wiring layer flushed with interlayer dielectric layer surface; Cover the protective layer of interlayer dielectric layer and metal wiring layer; Be positioned at the sealant on protective layer; Be positioned at the buffering groove of protective layer and sealant, described buffering trenched side-wall has aluminium side wall, and aluminium side wall is positioned on protective layer, and described aluminium side wall position is corresponding with the part that respective metal wiring layer is not covered by sealant.
Alternatively, described aluminium lateral wall width is more than or equal to the width of the part that respective metal wiring layer is not covered by sealant.
Alternatively, the material of described metal wiring layer is copper.
Alternatively; described edge seal structure comprises interlayer dielectric layer, is positioned at interlayer dielectric layer and the discrete metal wiring layer flushed with interlayer dielectric layer surface, covers the protective layer of interlayer dielectric layer and metal wiring layer; be positioned at the aluminum metal layer on protective layer, be positioned at the sealant on aluminum metal layer.
Alternatively, the material of described protective layer is silicon nitride or silica.
Alternatively, the material of described sealant is silica or silicon nitride.
The technical program additionally provides a kind of method forming described chip operator guards, comprises the steps: to provide Semiconductor substrate, and described Semiconductor substrate comprises edge seal district and crack stop district; Form interlayer dielectric layer on a semiconductor substrate, there is in described interlayer dielectric layer the discrete metal wiring layer flushed with interlayer dielectric layer surface; Interlayer dielectric layer and metal wiring layer form protective layer; Form aluminum metal layer on the protection layer; Etching aluminum metal layer, the aluminum metal layer in preserving edge seal area, makes the position of residual Al metal level in crack stop district corresponding with the partial width of each metal wiring layer; Aluminum metal layer and protective layer form sealant; The sealant in etching crack stop district, form buffering groove, described residual Al metal level is positioned at the two side of buffering groove.
Alternatively, the material of described protective layer is silicon nitride or silica, and the method forming described protective layer is chemical vapour deposition technique.
Alternatively, the material of described sealant is silica or silicon nitride, and the method forming described sealant is chemical vapour deposition technique.
Alternatively, the method etching described aluminum metal layer is dry etching.
Alternatively, the method etching described protective layer and described sealant is wet etching.
Alternatively, described step: also comprise the steps: form protective layer on interlayer dielectric layer and metal wiring layer after that partial protection layer in etched edge seal area is to exposing metal wiring layer, forms opening in described protective layer.
Compared with prior art; embodiments of the invention have the following advantages: formed in the described process for the protection of the semiconductor structure of chip; by forming aluminium side wall in crack stop district; at etching sealant and protective layer; when forming buffering groove, the protective layer above protection metal wiring layer, not by over etching, effectively prevent the copper metal exposed in metal wiring layer; avoid the pollution of copper metal pair semiconductor device, improve yield and the performance of final products.
Accompanying drawing explanation
Fig. 1 is the semiconductor chip structure schematic diagram in prior art with protection zone;
Fig. 2 is the longitudinal profile structure chart of operator guards in protection zone in Fig. 1;
Fig. 3 is the embodiment schematic flow sheet of the chip operator guards that the present invention is formed;
Fig. 4 to Fig. 8 is the embodiment process schematic that the present invention forms chip operator guards.
Embodiment
Inventor finds in existing semiconductor structure, is that the metal line layer material in chip functions district or chip protection zone interconnection structure all adopts copper metal usually.And when making the crack stop district of chip protection zone; etching sealant and protective layer; formed in buffering groove process; usually can there is over etching phenomenon; thus make the copper metal exposed in metal wiring layer; and copper metallic pollution will have an impact to the performance of semiconductor device in chip functions region, thus reduce the yield of final products.
For the problems referred to above, inventor studies by analysis, proposes technical scheme of the present invention, particularly, with reference to shown in figure 3 being the embodiment schematic flow sheet that the present invention forms chip operator guards:
Step S1: provide Semiconductor substrate, described Semiconductor substrate comprises edge seal district and crack stop district.
Step S2: form interlayer dielectric layer on a semiconductor substrate, has the discrete metal wiring layer flushed with interlayer dielectric layer surface in described interlayer dielectric layer.
Step S3: form protective layer on interlayer dielectric layer and metal wiring layer.
Step S4: the partial protection layer in etched edge seal area, to exposing metal wiring layer, forms opening in described protective layer.
Step S5: form aluminum metal layer on the protection layer.
Step S6: etching aluminum metal layer, the aluminum metal layer in preserving edge seal area, makes the position of residual Al metal level in crack stop district corresponding with the partial width of each metal wiring layer.
Step S7: form sealant on aluminum metal layer and protective layer.
Step S8: the sealant in etching crack stop district, form buffering groove, described residual Al metal level is positioned at the two side of buffering groove.
Based on the chip operator guards that above-mentioned execution mode is formed, comprising: edge seal structure and crack stop structures, described crack stop structures is adjacent with described edge seal structure; Described crack stop structures comprises interlayer dielectric layer; Be positioned at interlayer dielectric layer and the discrete metal wiring layer flushed with interlayer dielectric layer surface; Cover the protective layer of interlayer dielectric layer and metal wiring layer; Be positioned at the sealant on protective layer; Be positioned at the buffering groove of protective layer and sealant, described buffering trenched side-wall has aluminium side wall, and described aluminium side wall position is corresponding with the part that respective metal wiring layer is not covered by sealant.
The technical scheme that inventor provides is being formed in the described process for the protection of the semiconductor structure of chip; by forming aluminium side wall in crack stop district; at etching sealant and protective layer, when forming buffering groove, the protective layer above protection metal wiring layer is not crossed and is carved.Effectively prevent the copper metal exposed in metal wiring layer, avoid the pollution of copper metal pair semiconductor device, improve yield and the performance of final products.
The formation method of described chip operator guards is described below in conjunction with specific embodiment.
Embodiment one: with reference to the forming process schematic diagram of the chip operator guards of the present invention shown in figure 4 to Fig. 8.
Particularly, first as shown in Figure 4, Semiconductor substrate (not shown in Fig. 4) is provided, described Semiconductor substrate has interconnection structure, described interconnection structure comprises metal level and conductive plunger, described metal level and conductive plunger are all positioned at interlayer dielectric layer, and each layer metal level is electrically connected by described conductive plunger; Described Semiconductor substrate comprises edge seal district and crack stop district.The described Semiconductor substrate with interconnection structure forms interlayer dielectric layer 101, have discrete metal wiring layer 102a, 102b of flushing with interlayer dielectric layer 101 surface in described interlayer dielectric layer 101, described metal wiring layer 102 is connected with interconnection structure by conductive plunger equally.
In the present embodiment, the material of described metal wiring layer 102a, 102b is copper.The formation method of described interlayer dielectric layer 101 and described metal wiring layer 102a, 102b is prior art, does not repeat them here.
Continue with reference to figure 4, described interlayer dielectric layer 101 and described metal wiring layer 102a, 102b form protective layer 103.Particularly, the method forming described protective layer 103 can be chemical vapour deposition (CVD) (CVD), low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or physical vapour deposition (PVD) (PVD).Alternatively, the material of described protective layer 103 is silica or silicon nitride.
Further, as shown in Figure 5, in the described protective layer 103 in edge seal district, form opening 1031, described opening 1031 exposes a wherein metal wiring layer surface.Concrete technology is as follows: prior to described protective layer 103 covering photoresist layer (not shown in Fig. 5), after exposure imaging, go out opening figure at crack stop area definition; Again with described photoresist layer for mask, along described opening figure, described protective layer 103 is etched to the part metals wiring layer 101 exposed in described edge seal district, formed opening; Remove photoresist layer.
Then, as shown in Figure 6, described protective layer 103 forms aluminum metal layer 104, and described aluminum metal layer 104 fills full gate mouth.Particularly, the method forming described aluminum metal layer 104 can be chemical vapour deposition (CVD) (CVD), low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or physical vapour deposition (PVD) (PVD).
Further, as shown in Figure 7, described aluminum metal layer is etched, the aluminum metal layer in preserving edge seal area, as aluminum pad 1041; And in crack stop district, the position of residual Al metal level is corresponding with the partial width of each metal wiring layer 102a, as the aluminium side wall 1042 in follow-up buffering groove.Concrete technology is as follows: on described aluminum metal layer, cover photoresist layer (not shown in Fig. 7), define land pattern and side wall figure after exposure imaging; Again with described photoresist layer for mask, described aluminum metal layer 104 is etched to and exposes described protective layer 103, form aluminum pad 1041 in edge seal district, form aluminium side wall 1042 in crack stop district; Then photoresist layer is removed.Then, as shown in Figure 8, aluminum pad 1041, aluminium side wall 1042 and protective layer 103 form sealant 105.Particularly, the method forming described sealant 105 can be chemical vapour deposition (CVD) (CVD), low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or physical vapour deposition (PVD) (PVD).Alternatively, the material of described sealant 105 is silica or silicon nitride.
Continue with reference to figure 8, the sealant 105 in etching crack stop district and protective layer 103, form buffering groove 106, described aluminium side wall 1042 lays respectively at the two side of described buffering groove 106, and described aluminium side wall 1042 is positioned on protective layer 103.Alternatively, the width of described aluminium side wall 1042 is more than or equal to the width of the part that respective metal wiring layer 102a is not covered by sealant 105.Concrete formation buffering trench process is as follows: on described sealant 105, cover photoresist layer (not shown in Fig. 8), define buffering figure after exposure imaging; Again with described photoresist layer for mask, along buffering groove figure described sealant 105 and protective layer 103 are etched; Finally remove described photoresist layer, thus form the stress that there is release diced chip and produce, the chip operator guards of the buffering groove 106 in protect IC active circuit district.
As another example; described protective layer 103 may be crossed to be carved to exposing interlayer dielectric layer 101; but owing to being formed with aluminium side wall 1042 on the metal wiring layer 102a do not covered by sealant 105; described aluminium side wall 1042 is positioned on protective layer 103; therefore the protective layer 103 under described aluminium side wall 1042 can not be etched, and also can not expose described metal wiring layer 102a.
It should be noted that, when etching described sealant 105, the etch rate due to aluminum metal is less than the etch rate of silica and silicon nitride, and therefore the etch rate of described aluminium side wall 1042 is less than the etch rate of described sealant 105.Even if like this when over etching occurs described sealant 105; described aluminium side wall 1042 is not also all etched; therefore described aluminium side wall 1042 can play the effect of metal wiring layer 102a described in protection crack stop district; make the copper metal in described metal wiring layer 102 can not be exposed and affect the performance of chip, thus improve the yield of final products.
After forming chip operator guards as shown in Figure 8, alternatively, technical staff can also increase by a step process flow process, that is: remove the aluminium side wall 1042 being positioned at described buffering groove 106 two side.Because described aluminium side wall 1042 just plays a protective role to metal wiring layer 102a when etching described sealant 105; can not copper metal in exposing metal wiring layer 102a when making described sealant 105 that over etching occur; so after the described chip operator guards that completes, described aluminium side wall 1042 can be removed.Further, if retain the effect that described aluminium side wall 1042 also can not have influence on chip operator guards described in the present embodiment, do not repeat them here.
Based on the chip operator guards that above-described embodiment is formed; comprise: Semiconductor substrate (not shown); described Semiconductor substrate is formed with interconnection structure; and described Semiconductor substrate comprises edge seal district and crack stop district; wherein said edge seal district is positioned at the outward flange of chip functions district (not shown), and described crack stop district is positioned at described edge seal district outward flange.Described edge seal district and described crack stop district are formed with in interlayer dielectric layer 101, described interlayer dielectric layer 101 the discrete metal wiring layer 102 having and flush with interlayer dielectric layer 101 surface, and described metal wiring layer 102 is electrically connected with interconnection structure by conductive plunger.Interlayer dielectric layer 101 and metal wiring layer 102 form protective layer 103.
Described edge seal district also comprises: opening, is positioned at protective layer 103, and exposes a metal wiring layer 102b; Aluminum pad 1041, is formed on protective layer 103, and fills full gate mouth; Sealant 105, is positioned on protective layer 103 and aluminum pad 1041.
Described crack stop district also comprises: aluminium side wall 1042, is positioned on protective layer 103; Sealant 105, to be positioned on protective layer 103 and next-door neighbour's aluminium side wall 1042; Buffering groove 106, is positioned at sealant 105 and protective layer 103, and aluminium side wall 1042 is positioned on buffering groove 106 two side.
The embodiment of the present invention protects metal wiring layer by arranging aluminium side wall at the madial wall of existing buffering groove; make when etching sealant; also can not copper metal in exposing metal wiring layer even if there is over etching phenomenon; thus avoid the performance generation harmful effect of copper metallic pollution to chip, thus improve the yield of final chip.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (11)
1. a chip operator guards, comprising: edge seal structure and crack stop structures, and described crack stop structures is adjacent with described edge seal structure; Described crack stop structures comprises interlayer dielectric layer, be positioned at interlayer dielectric layer and the discrete metal wiring layer flushed with interlayer dielectric layer surface, cover the protective layer of interlayer dielectric layer and metal wiring layer, be positioned at the sealant on protective layer, be positioned at the buffering groove of protective layer and sealant; It is characterized in that, when etching described sealant, described buffering trenched side-wall has aluminium side wall, and aluminium side wall is positioned on protective layer, described aluminium side wall position is corresponding with the part that respective metal wiring layer is not covered by sealant, and described aluminium lateral wall width is more than or equal to the width of the part that respective metal wiring layer is not covered by sealant; Protective layer under described aluminium side wall can not be etched; The part of described buffering groove in described aluminium side wall is positioned at above described interlayer dielectric layer and is not positioned at above described metal wiring layer.
2. chip operator guards according to claim 1, is characterized in that, the material of described metal wiring layer is copper.
3. chip operator guards according to claim 1, is characterized in that, described edge seal structure comprises interlayer dielectric layer; Be positioned at interlayer dielectric layer and the discrete metal wiring layer flushed with interlayer dielectric layer surface; Cover the protective layer of interlayer dielectric layer and metal wiring layer, there is in described protective layer the opening exposing metal wiring layer; To be positioned on protective layer and to fill the aluminum pad of full gate mouth, being positioned at the sealant on aluminum pad.
4. the chip operator guards according to claim 1 or 3, is characterized in that, the material of described protective layer is silicon nitride or silica.
5. the chip operator guards according to claim 1 or 3, is characterized in that, the material of described sealant is silica or silicon nitride.
6. form a method for chip operator guards as described in claim 1 or 3, it is characterized in that, comprise the steps:
There is provided Semiconductor substrate, described Semiconductor substrate comprises edge seal district and crack stop district;
Form interlayer dielectric layer on a semiconductor substrate, there is in described interlayer dielectric layer the discrete metal wiring layer flushed with interlayer dielectric layer surface;
Interlayer dielectric layer and metal wiring layer form protective layer;
Form aluminum metal layer on the protection layer;
Etching aluminum metal layer, the aluminum metal layer in preserving edge seal area, makes the position of residual Al metal level in crack stop district corresponding with the partial width of each metal wiring layer; In described crack stop district, residual Al metal level forms aluminium side wall, wherein, making the step that the position of residual Al metal level in crack stop district is corresponding with the partial width of each metal wiring layer, is the width making the width of described aluminium side wall be more than or equal to the part that respective metal wiring layer is not covered by sealant;
Aluminum metal layer and protective layer form sealant;
The sealant in etching crack stop district and protective layer, form buffering groove, described residual Al metal level is positioned at the two side of buffering groove; The part of described buffering groove in described aluminium side wall is positioned at above described interlayer dielectric layer and is not positioned at above described metal wiring layer.
7. the formation method of chip operator guards according to claim 6, is characterized in that, the material of described protective layer is silicon nitride or silica, and the method forming described protective layer is chemical vapour deposition technique.
8. the formation method of chip operator guards according to claim 6, is characterized in that, the material of described sealant is silica or silicon nitride, and the method forming described sealant is chemical vapour deposition technique.
9. the formation method of chip operator guards according to claim 6, is characterized in that, the method etching described aluminum metal layer is dry etching.
10. the formation method of chip operator guards according to claim 6, is characterized in that, the method etching described protective layer and described sealant is wet etching.
The formation method of 11. chip operator guards according to claim 6; it is characterized in that; described step: also comprise the steps: form protective layer on interlayer dielectric layer and metal wiring layer after that partial protection layer in etched edge seal area is to exposing metal wiring layer, forms opening in described protective layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110049531.6A CN102655127B (en) | 2011-03-01 | 2011-03-01 | Chip protecting structure and forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110049531.6A CN102655127B (en) | 2011-03-01 | 2011-03-01 | Chip protecting structure and forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102655127A CN102655127A (en) | 2012-09-05 |
| CN102655127B true CN102655127B (en) | 2015-03-11 |
Family
ID=46730729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110049531.6A Active CN102655127B (en) | 2011-03-01 | 2011-03-01 | Chip protecting structure and forming method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102655127B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108447837A (en) * | 2017-02-16 | 2018-08-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices |
| CN110690160A (en) * | 2019-10-16 | 2020-01-14 | 上海先方半导体有限公司 | Chip protection structure and manufacturing method thereof |
| US11289385B2 (en) * | 2020-06-09 | 2022-03-29 | Winbond Electronics Corp. | Semiconductor die and a method for detecting an edge crack in a semiconductor die |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101308825A (en) * | 2007-05-14 | 2008-11-19 | 台湾积体电路制造股份有限公司 | Integrated circuit contruction |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7456507B2 (en) * | 2006-01-12 | 2008-11-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Die seal structure for reducing stress induced during die saw process |
| US7871902B2 (en) * | 2008-02-13 | 2011-01-18 | Infineon Technologies Ag | Crack stop trenches |
-
2011
- 2011-03-01 CN CN201110049531.6A patent/CN102655127B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101308825A (en) * | 2007-05-14 | 2008-11-19 | 台湾积体电路制造股份有限公司 | Integrated circuit contruction |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102655127A (en) | 2012-09-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101290912B (en) | Semiconductor device and manufacturing method thereof | |
| US8748320B2 (en) | Connection to first metal layer in thin film transistor process | |
| CN104752325B (en) | Semiconductor devices and forming method thereof, the method for improving wafer cutting yield rate | |
| CN102655127B (en) | Chip protecting structure and forming method | |
| KR100703983B1 (en) | Semiconductor device and method for fabricating the same | |
| JP4751083B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN105448741A (en) | Shield grid groove type MOSFET process method | |
| JP2015023121A (en) | Semiconductor wafer, semiconductor ic chip and manufacturing method of the same | |
| TW201906093A (en) | Trench structure | |
| CN204130517U (en) | The wafer level chip scale package structure of belt edge protection and chip packaging unit | |
| TW201306192A (en) | Die seal ring structure | |
| FR3068507B1 (en) | REALIZATION OF SEMICONDUCTOR REGIONS IN AN ELECTRONIC CHIP | |
| KR20090044262A (en) | Semiconductor device and method of fabricating the same | |
| US7358155B2 (en) | Scribe-line structures and methods of forming the same | |
| CN104465728A (en) | Gate structure of separation gate power device and process method | |
| JP2010287853A (en) | Semiconductor device and method of manufacturing the same | |
| TWI527104B (en) | Semiconductor device and manufacturing method therefor | |
| JP5678705B2 (en) | Manufacturing method of semiconductor device | |
| JP2009218504A (en) | Semiconductor device | |
| US20040188796A1 (en) | Fabricating deeper and shallower trenches in semiconductor structures | |
| US20230326882A1 (en) | Semiconductor structure and manufacturing method thereof | |
| JP7131155B2 (en) | semiconductor equipment | |
| CN214428623U (en) | Chip packaging structure | |
| CN102683278A (en) | Chip separation method | |
| ITTO20100332A1 (en) | PROCEDURE FOR THE MANUFACTURE OF SEMICONDUTTRIC PLATES AND SEMICONDUTTRIC PLATE WITH PROTECTIVE TRINCEA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |