CN102637692B - Flash memory structure and manufacturing and operation method thereof - Google Patents
Flash memory structure and manufacturing and operation method thereof Download PDFInfo
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- CN102637692B CN102637692B CN201110035673.7A CN201110035673A CN102637692B CN 102637692 B CN102637692 B CN 102637692B CN 201110035673 A CN201110035673 A CN 201110035673A CN 102637692 B CN102637692 B CN 102637692B
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Abstract
The invention discloses a flash memory structure and a manufacturing and operation method thereof. The flash memory structure comprises a plurality of memory units, a plurality of bit line groups, a plurality of source line groups, a plurality of channel groups and a plurality of insulation column bodies, wherein the memory units are arranged in three dimensions on a plane, each memory unit comprises a plurality of word lines and a plurality of composite charge capture layers which are arranged in a staggering way, and the adjacent two word lines is separated through one composite charge capture layer arranged between the two word lines; the bit line groups and the source line groups are arranged in a staggering way and are vertical to the plane of the memory units; and the channel groups and the insulation column bodies are arranged in a staggering way and are vertical to the plane of the memory units, and each channel group is arranged between the bit line group and the source line group which are adjacent.
Description
Technical field
The present invention relates to three-dimensional flash memory structure and manufacture method thereof and method of operation, and particularly relate to a kind of three-dimensional stacked AND type flash memory structure and manufacture method and method of operation.
Background technology
Non-volatile memory device has a very large feature to be in design, integrality that still can save data state after memory component loses or removes power supply.The non-volatile memory device of the existing many different kenels of industry is suggested at present.But relevant dealer still constantly researches and develops new design or in conjunction with prior art, carries out the stacking of memory cell plane and have the more memory construction of high storage capacity to reach.For example NAND gate (Not AND, NAND) the type flash memory structure of more existing plural layers transistor stack is suggested.
But, to manufacture in the process of these three-dimensional NAND gate (NAND) type flash memory structures, every layer of memory cell plane all needs the photoetching process of many roads key to make, and extremely expends time in and manufacturing cost.Although three-dimensional structure can obtain higher memory density, expensive cost has also limited development and the application of three-dimensional stacked flash memory structure.
Moreover, due to the metal oxide semiconductcor field effect transistor (MOSFET of three-dimensional stacked NAND gate (NAND) type flash memory structure, Metal-Oxide-Semiconductor Field-Effect Transistor) be series connection setting, in reading speed, can be affected and have some delay phenomenons to produce.
Therefore, relevant design person expects construction to go out three-dimensional flash memory structure invariably, not only there are many stacking planes and reach higher storage volume, and there is the operation of stable and small-sized memory component to be wiped and to programme, and entirety has reading speed faster.Moreover, also wish to see through low manufacturing cost and simple step, just can produce this three-dimensional flash memory structure.
Summary of the invention
The present invention has about the three-dimensional stacked AND type of one flash memory (3D stacked AND-typeflash memory) structure and manufacture method thereof, and propose some relevant methods of operation for this three-dimensional stacked AND type flash memory structure, as the operation such as read, programme and wipe.This three-dimensional stacked AND type flash memory structure has reading speed faster, and can be suitable for a unit one bit (1bit/cell) and operate and be suitable for the operation of a unit dibit unit (2bits/cell).
According to embodiments of the invention, a kind of three-dimensional stacked AND type flash memory (3D stackedAND-type flash memory) structure is proposed.This structure comprises that multiple memory cell plane layouts become three-dimensional arrangement, and each memory cell plane comprises that many word lines and multiple charge-trapping composite bed (chargetrapping multilayers) are staggered, two adjacent word lines are spaced from each other with each the charge-trapping composite bed arranging wherein; Multiple set of bit lines (sets of bit lines) and multiple source electrode line group (sets ofsource lines) are staggered and perpendicular to those memory cell plane layouts; And multiple raceway groove groups (setsof channels) and multiple insulation cylinder group (sets of insulation pillars) are staggered, and perpendicular to memory cell plane layout, and each raceway groove group is arranged between adjacent set of bit lines and source electrode line group.
According to embodiments of the invention, a kind of manufacture method of three-dimensional stacked AND-type flash memory structure is proposed.First substrate is provided; And alternately form multiple grid layers (gate layers) and multiple insulating barrier (insulation layers) on substrate.Then, those grid layers of patterning and those insulating barriers, to form multiple character stacked bodies (WL stacks), and each character stacked body comprises the patterned gate and the patterned insulation layer that are arranged alternately after patterning, those patterned gate are suitable for as many word lines and are patterned insulating barrier separating.Afterwards, form charge-trapping composite bed on these character stacked bodies, and lining type ground covers the sidewall of those character stacked bodies, and form multiple grooves (trenches) and lay respectively between those character stacked bodies that are lined with charge-trapping composite bed.Then, depositing conducting layer is on these character stacked bodies and fill up these grooves.And patterned conductive layer to be to form multiple bit stacked bodies (BL stacks), and these bit stacked bodies are alternatively separated by multiple gaps (gaps).Afterwards, form respectively two doped regions in the both sides of each bit stacked body, and raceway groove vertically arranges between two doped regions, wherein adjacent bit stacked body is mutually isolated.
According to embodiments of the invention, a kind of method of operation is proposed.First, provide the three-dimensional stacked AND-type flash memory structure proposing as first aspect.Select storage unit in this structure, and this memory cell is positioned at one of them plane place of those memory cell planes.In the memory cell plane place at selected memory cell place, respectively apply operating voltage in two word lines of this memory cell of next-door neighbour, be close to two word lines of this memory cell with conducting.Close the raceway groove in two word line outsides of contiguous conducting.Apply relevant voltage in selected those set of bit lines and at least one of them group of those source electrode line groups, and impose 0V voltage in all the other unselected those set of bit lines and those source electrode line groups.
For there is to better understanding above-mentioned and other aspect of the present invention, special embodiment below, and coordinate accompanying drawing, be described in detail below:
Brief description of the drawings
Fig. 1 is the schematic diagram according to the stacking AND type of the partial 3-D flash memory structure of the embodiment of the present invention.
Fig. 2 A is the stacking AND type of the partial 3-D flash memory structure according to the embodiment of the present invention, and the schematic diagram of memory cell to be read.
Fig. 2 B is the vertical view of the second plane of Fig. 2 A, and illustrates more multi-word lines clearer related description when reading.
Fig. 3 A is the stacking AND type of the partial 3-D flash memory structure according to the embodiment of the present invention, and wants the schematic diagram of the memory cell of carrying out channel hot electron programming.
Fig. 3 B is the vertical view of the second plane of Fig. 3 A, and illustrates more multi-word lines clearer related description when reading.
Fig. 4 A is the stacking AND type of the partial 3-D flash memory structure according to the embodiment of the present invention, and wants the schematic diagram of the memory cell of carrying out FN tunneling program.
Fig. 4 B is the vertical view of the second plane of Fig. 4 A, and illustrates more multi-word lines clearer related description when reading.
Fig. 5 A is the stacking AND type of the partial 3-D flash memory structure according to the embodiment of the present invention, and wants to carry out the schematic diagram of the memory cell that FN wipes comprehensively.
Fig. 5 B is the vertical view of the second plane of Fig. 5 A, and illustrates more multi-word lines clearer related description when reading.
Fig. 6 A is according to the schematic diagram of the stacking AND type of the partial 3-D flash memory structure of the embodiment of the present invention, is suitable for the operation of a unit dibit unit.
Fig. 6 B is the vertical view of the second plane of three-dimensional stacked AND type flash memory structure in Fig. 6 A, and this memory cell is by monolateral reading (one-side reading).
Fig. 7 A is according to the schematic diagram of the stacking AND type of the partial 3-D flash memory structure of the embodiment of the present invention, is suitable for the operation of a unit dibit unit.
Fig. 7 B is the vertical view of the second plane of three-dimensional stacked AND type flash memory structure in Fig. 7 A, and this memory cell is carried out monolateral programming (one-sideprogramming) with channel hot electron programmed method.
Fig. 8 A～8F illustrates the flow process profile according to the manufacture method of the three-dimensional stacked AND type flash memory structure of the embodiment of the present invention.
Fig. 9 is the schematic diagram of the stacking AND type of the partial 3-D of alternate embodiment of the present invention flash memory structure.
Figure 10 is the schematic diagram of the stacking AND type of the partial 3-D of another alternate embodiment of the present invention flash memory structure.
Description of reference numerals
10: substrate
101: base plate
103: buried oxide layer
103a: the upper surface of buried oxide layer
11,12,13: memory cell plane
111,112,113,121,122,123,131,132,133: word line
54,115,116,125,126,135,136: charge-trapping composite bed
21,22: set of bit lines
211,212,222: bit line cylinder
222a, 222b, 222c: imbed bit line portion
31,32: source electrode line group
311,312,321,322: source electrode line cylinder
322a, 322b, 322c: imbed source electrode line portion
251,252,253,254: insulation cylinder group
351,353: raceway groove group
353a, 353b, 353c: channel region
C
r, C
r': memory cell to be read
I
r: reading current
WL
n-1 (2), WL
n (2), WL
n+1 (2), WL
n+2 (2), WL
n+3 (2), WL
n+4 (2): word line
211 ', 212 ', 213 ': bit line portion
311 ', 312 ', 313 ': source electrode line portion
50: stacked body
501,503,505,506: polysilicon gate layer
501 ', 503 ', 505 ', 506 ': patterned polysilicon grid layer
511,513,515,516: insulating barrier
511 ', 513 ', 515 ', 516 ': patterned insulation layer
52: character stacked body
52a, 52b: the sidewall of character stacked body 52
55: groove
57: polysilicon layer
58: bit stacked body
582,583: two doped regions
585: raceway groove
59: gap
SSL1: the first safe socket layer-selective transistor
SSL2: the second safe socket layer-selective transistor
G1: the first common gate
G2: the second common gate
G3: the 3rd common gate
Embodiment
In the embodiment of this disclosure content, a kind of three-dimensional stacked AND type flash memory (3Dstacked AND-type flash memory) structure and manufacture method thereof are proposed.And, propose some relevant methods of operation for this three-dimensional stacked AND type flash memory structure, as read, programme and wipe the method for this memory construction.Due to the metal oxide semiconductcor field effect transistor (MOSFET of the three-dimensional stacked AND type flash memory structure of embodiment, Metal-Oxide-Semiconductor Field-EffectTransistor) be to be arranged in parallel, but not as the series connection setting in NAND gate (NAND) type flash memory structure, therefore can accelerate reading speed.Moreover, the three-dimensional stacked AND type flash memory structure of embodiment can be programmed (channel hot electronprogramming) with channel hot electron by similar NOR type flash memory, or similar NAND type flash memory is programmed by FN tunnelling (Fowler-NordheimTunneling).Moreover, the structure of embodiment is bigrid charge-trapping element, and this bigrid can be encoded independently, make this structure except being suitable for unit one bit (1bit/cell) operation, also can be suitable for the operation of a unit dibit unit (2bits/cell).
Related embodiment is below proposed, to describe three-dimensional stacked AND type flash memory structure and manufacture method and method of operation proposed by the invention in detail.But narration in embodiment, as concrete structure, processing step and material application etc., the only use for illustrating, the scope of not wish of the present invention being protected limits.
The three-dimensional stacked AND type of < flash memory structure >
Fig. 1 is the schematic diagram according to the stacking AND type of the partial 3-D flash memory structure of the embodiment of the present invention.In embodiment, three-dimensional stacked AND type flash memory structure has multiple memory cell planes (horizontal planes of memory cells) and is arranged to three-dimensional arrangement, and is built on the have buried oxide layer substrate of (buried oxide).In Fig. 1, illustrating three the memory cell planes 11,12 and 13 that are established in X-Y plane explains.Each memory cell plane comprises that many word lines and multiple charge-trapping composite bed (charge trapping multilayers) interlock and be arranged in parallel, charge-trapping composite bed is for example that (its structure can be with reference to U. S. application case number 11/419 for oxide-nitride thing-oxide (ONO) composite bed or ONONO composite bed or BE-SONOS (BandgapEngineered SONOS) composite bed, 977, the patent No. 7414889), and in each memory cell plane, two adjacent word lines are to come in each the charge-trapping composite bed space arranging wherein.As shown in Figure 1, memory cell plane 11 comprises many word lines 111,112 and 113, staggered and the arrangement in parallel to each other with multiple charge-trapping composite beds 115 and 116, wherein two adjacent word lines 111,112 are spaced apart with the charge-trapping composite bed 115 between being arranged at; Two adjacent word lines 112,113 are spaced apart with the charge-trapping composite bed 116 between being arranged at.
Same, memory cell plane 12 comprises many word lines 121,122 and 123, staggered and the arrangement in parallel to each other with multiple charge-trapping composite beds 125 and 126, wherein two adjacent word lines 121,122 are spaced apart with the charge-trapping composite bed 125 between being arranged at; Two adjacent word lines 122,123 are spaced apart with the charge-trapping composite bed 126 between being arranged at.
Similar, memory cell plane 13 comprises many word lines 131,132 and 133, staggered and the arrangement in parallel to each other with multiple charge-trapping composite beds 135 and 136, wherein two adjacent word lines 131,132 are spaced apart with the charge-trapping composite bed 135 between being arranged at; Two adjacent word lines 132,133 are spaced apart with the charge-trapping composite bed 136 between being arranged at.
Moreover, the three-dimensional stacked AND type flash memory structure of embodiment has multiple set of bit lines (setsof bit lines) and multiple source electrode line group (sets of source lines) is staggered, and vertically through those memory cell plane layouts.This adjacent set of bit lines and this source electrode line group space and independently setting.As shown in Figure 1, two groups of set of bit lines 21,22 and two groups of source electrode line group 31,32 spaces and arrange independently.Set of bit lines 21 comprise multiple bit line cylinders as bit line cylinder 211 with 212 with mutually vertical setting of memory cell plane 11-13; Another set of bit lines 22 comprise two bit line cylinders (the bit line cylinder 222 that can show as visual angle) also with memory cell plane 11-13 vertical setting mutually.Similarly, source electrode line group 31 comprises source electrode line cylinder 311 and 312, and source electrode line group 32 comprises source electrode line cylinder 321 and 322, all with memory cell plane 11-13 vertical setting mutually.
Moreover, the word line of the bit line cylinder of these set of bit lines and the source electrode line cylinder of source electrode line group and each memory cell plane and charge-trapping composite bed is orthogonal sets up.As shown in Figure 1, the word line 111-113 of bit line cylinder 211,212,222 and memory cell plane 11 and orthogonal the setting up of charge-trapping composite bed 115-116, also with word line 121-123 and orthogonal the setting up of charge-trapping composite bed 125-126 of lower one deck memory cell plane 12, also with word line 131-133 and orthogonal the setting up of charge-trapping composite bed 135-136 of lower one deck memory cell plane 13.
In the three-dimensional stacked AND type flash memory structure of embodiment, also have that multiple insulation cylinder groups (sets of insulation pillars) and multiple raceway groove group (sets of channels) are staggered and on the bearing of trend being parallel to each other perpendicular to these memory cell plane layouts, and be provided with raceway groove group between adjacent set of bit lines and source electrode line group.Insulation cylinder group and raceway groove group are extended along Z-direction.As shown in Figure 1, insulation cylinder group 251,252,253,254 and raceway groove group 351,353 are staggered and arrange perpendicular to memory cell plane 11-13.Raceway groove group 351 is between two adjacent set of bit lines 21 and source electrode line group 31, and raceway groove group 353 is between two adjacent set of bit lines 22 and source electrode line group 32.253 of insulation cylinder groups are between two adjacent source electrode line groups 31 and set of bit lines 22.Moreover set of bit lines 22 is arranged between adjacent insulation cylinder group 253 and raceway groove group 353.
In embodiment, every group of set of bit lines at least comprises that multiple bit line portions (buried bit line portions) that imbed lay respectively between these adjacent memory cell planes, and every group of source electrode line group also comprises that multiple source electrode line portions (buried source line portions) that imbed lay respectively between these adjacent memory cell planes.For example, in Fig. 1, the bit line cylinder 222 of set of bit lines 22 has imbeds the 222a of bit line portion between adjacent memory cell plane 11 and 12, have and imbed the 222b of bit line portion between adjacent memory cell plane 12 and 13, and there is the 222c of the bit line of imbedding portion between memory cell plane 13 and substrate 10.The source electrode line cylinder 322 of source electrode line group 32 has imbeds the 322a of source electrode line portion between adjacent memory cell plane 11 and 12, have and imbed the 322b of source electrode line portion between adjacent memory cell plane 12 and 13, and there is the 322c of the source electrode line of imbedding portion between memory cell plane 13 and substrate 10.Moreover in embodiment, each raceway groove group comprises multiple vertical channel regions (vertical channel regions), and each vertical channel region is arranged at the adjacent bit line portion that imbeds and imbeds between source electrode line portion.As shown in Figure 1, raceway groove 353 has vertical channel region 353a, 353b, 353c, wherein channel region 353a is in adjacent imbedding the 222a of bit line portion and imbed between the 322a of source electrode line portion, channel region 353b is in adjacent imbedding the 222b of bit line portion and imbed between the 322b of source electrode line portion, and channel region 353c is in adjacent imbedding the 222c of bit line portion and imbed between the 322c of source electrode line portion.
In addition, be encirclement insulation cylinder group, bit line cylinder, source electrode line cylinder and raceway groove at the charge-trapping composite bed of each memory cell plane.Moreover the charge-trapping composite bed of each memory cell plane also can be regarded as contacting with the opposite flank of two adjacent word lines.For example, in Fig. 1, the charge-trapping composite bed 115 of memory cell plane 11 is around insulation cylinder 251,254, set of bit lines 21,22, source electrode line group 31,32 and raceway groove 351,353.And charge-trapping composite bed 115 also can be regarded as contacting with 112 opposite flank with two adjacent word lines 111.
In embodiment, word line and raceway groove group for example comprise polycrystalline silicon material, and insulation cylinder group for example comprises oxide material, and these set of bit lines and these source electrode line groups for example comprise n+ doped polycrystalline silicon materials (n+dopedpolysilicon).Certainly also can apply other materials, the present invention is not restricted to this.
The related operating method > of the three-dimensional stacked AND type of < flash memory structure
The three-dimensional stacked AND type flash memory structure of embodiment can carry out channel hot electron programming (channel hot electron programming), or+FN tunnelling (Fowler-Nordheim Tunneling) programming.This three-dimensional stacked AND type flash memory structure also can carry out-FN tunnelling erase.Below coordinate those methods of operation of accompanying drawing narration embodiment.Should be noted, accompanying drawing has been simplified but not has been drawn according to accurate size, and the therefore use for illustrating only, not as the use of limit protection range of the present invention.
Read (Reading)
Fig. 2 A is the stacking AND type of the partial 3-D flash memory structure according to the embodiment of the present invention, and the schematic diagram of memory cell to be read.Choosing place of dotted line circle is memory cell C to be read
rposition, and be positioned at the second plane 12 places.U-shaped lines I
rrepresent reading current, it arrives the word line WL of the second plane 12 by bit line cylinder 212
n+2 (2), then flow out from source electrode line cylinder 312.Each raceway groove is controlled by two adjacent word lines.Fig. 2 B is the vertical view of the second plane of Fig. 2 A, and illustrates more multi-word lines clearer related description when reading.In Fig. 1, some same or similar labels are in order to same or similar element in sign picture 2A～2B.Moreover Fig. 2 A and Fig. 2 B also show the operating voltage of each associated word lines, bit line and source electrode line in the three-dimensional stacking structure of embodiment.But those magnitudes of voltage are the use for illustrating only, those of ordinary skill after can reference example, carries out suitable adjustment to these magnitudes of voltage depending on practical application is required.
Referring to Fig. 2 A and Fig. 2 B.As shown in Fig. 2 A, 2B, memory cell C to be read
rbe positioned at the second plane 12 places.Reading cells C
rtime, conducting two adjacent word line WL
n+1 (2)and WL
n+2 (2), for example, apply 2V voltage or reference voltage Vref, to carry out memory cell C
rread.In embodiment, read applied voltage between erase status voltage and programming state voltage.Other non-selected word lines can impose 0V voltage or lower than erasing voltage Vt, to close other memory cell.
Moreover, can apply back bias voltage to close this raceway groove for other two adjacent word lines of raceway groove.In this embodiment, can be by applying back bias voltage (as ,-3V) in adjacent word line, to guarantee memory cell C to be read
rthe raceway groove of both sides is closed completely, avoids interference.As shown in Figure 2 B, memory cell C to be read
rraceway groove 351
n+1 (2)be positioned between bit line portion 212 ' and source electrode line portion 312 ' adjoining memory cell C
rraceway groove 351
n (2)be positioned between bit line portion 211 ' and source electrode line portion 311 ' adjoining memory cell C
ranother raceway groove 351
n+2 (2)be positioned between bit line portion 213 ' and source electrode line portion 313 '.Reading cells C
rtime, apply individually back bias voltage if-3V is in two adjacent word line WL
n (2)and WL
n+3 (2), to guarantee contiguous memory cell C to be read
rraceway groove 351
n+1 (2)both sides raceway groove 351
n (2)with 351
n+2 (2)can close completely.
In addition, in embodiment, can apply respectively 1V, 0V, 0V and 0V voltage in set of bit lines 21, unselected set of bit lines 22, the source electrode line group 31 and 32 selected.And other word lines that are positioned at the first plane 11 and the 3rd plane 13 also apply 0V voltage.
Channel hot electron programming (Channel Hot Electron Programming Method)
Fig. 3 A is the stacking AND type of the partial 3-D flash memory structure according to the embodiment of the present invention, and wants the schematic diagram of the memory cell of carrying out channel hot electron programming.Same, choosing place of dotted line circle is memory cell C to be programmed
rposition, and be positioned at the second plane 12 places, and each raceway groove is controlled by two adjacent word lines.Fig. 3 B is the vertical view of the second plane of Fig. 3 A, and illustrates more multi-word lines clearer related description when reading.In Fig. 1 and Fig. 2 A～2B, some same or similar labels are in order to same or similar element in sign picture 3A～3B.Fig. 3 A and Fig. 3 B also show the operating voltage of each associated word lines, bit line and source electrode line in the three-dimensional stacking structure of embodiment.But those magnitudes of voltage are the use for illustrating only, those of ordinary skill is when after reference example, and visual practical application while carrying out channel hot electron programming is required, and those magnitudes of voltage are carried out to suitable adjustment.
Referring to Fig. 3 A and Fig. 3 B.As shown in Fig. 3 A, 3B, memory cell C
rwhile carrying out channel hot electron programming, apply high voltage conducting two adjacent word line WL
n+1 (2)and WL
n+2 (2), for example, apply 9V voltage, to produce strong vertical electric field to attract electronics.In embodiment, selected word line imposes 5V voltage as 21 of word line group, so that hot electron is pulled to the memory cell C of selection
r.
In embodiment, other non-selected word lines can impose 0V voltage (or lower than erasing voltage Vt), to close other memory cell.In addition, can apply respectively 0V, 0V and 0V voltage in unselected set of bit lines 22, source electrode line group 31 and 32.And other word lines that are positioned at the-plane 11 and the 3rd plane 13 also apply 0V voltage.
Moreover, can apply back bias voltage to close this raceway groove for other two adjacent word lines of raceway groove.In this embodiment, can be by applying back bias voltage (as ,-7V) in adjacent word line, to guarantee memory cell C
rthe raceway groove of both sides is closed completely, avoids interference.As shown in Figure 3 B, memory cell C to be programmed
rraceway groove 351
n+1 (2)be positioned between bit line portion 212 ' and source electrode line portion 312 ' adjoining memory cell C
rraceway groove 351
n (2)be positioned between bit line portion 211 ' and source electrode line portion 311 ' adjoining memory cell C
ranother raceway groove 351
n+2 (2)be positioned between bit line portion 213 ' and source electrode line portion 313 '.Memory cell C
rwhen programming, apply individually back bias voltage if-7V is in two adjacent word line WL
n (2)and WL
n+3 (2), to guarantee adjoining memory cell C
rraceway groove 351
n+1 (2)both sides raceway groove 351
n (2)with 351
n+2 (2)can close completely.
FN tunneling program (FN Programming Method)
Fig. 4 A is the stacking AND type of the partial 3-D flash memory structure according to the embodiment of the present invention, and wants the schematic diagram of the memory cell of carrying out FN tunneling program.Same, choosing place of dotted line circle is memory cell C to be programmed
rposition, and be positioned at the second plane 12 places, and each raceway groove is controlled by two adjacent word lines.Fig. 4 B is the vertical view of the second plane of Fig. 4 A, and illustrates more multi-word lines clearer related description when reading.In Fig. 1 and Fig. 2 A～2B, some same or similar labels are in order to same or similar element in sign picture 4A～4B.Fig. 4 A and Fig. 4 B also show the operating voltage of each associated word lines, bit line and source electrode line in the three-dimensional stacking structure of embodiment.But those magnitudes of voltage are the use for illustrating only, those of ordinary skill is when after reference example, and visual practical application while carrying out FN tunneling program is required, and those magnitudes of voltage are carried out to suitable adjustment.
Referring to Fig. 4 A and Fig. 4 B.As shown in Fig. 4 A, 4B, memory cell C
rwhile carrying out FN tunneling program, apply high voltage conducting two adjacent word line WL
n+1 (2)and WL
n+2 (2), for example apply+8V voltage, to produce strong vertical electric field to attract electronics.In embodiment, selected word line (as word line group 21) and bit line (as set of bit lines 31) impose respectively high back bias voltage as-10V voltage.Now, can be to select storage unit C
rthe effective pressure reduction 18V causing and cause FN tunneling effect.
In embodiment, other non-selected word lines can impose 0V voltage (or lower than erasing voltage Vt), to close other memory cell.In addition, can apply respectively 0V and 0V voltage in unselected set of bit lines 22 and source electrode line group 32.And other word lines that are positioned at the first plane 11 and the 3rd plane 13 also apply 0V voltage.
Moreover, can apply back bias voltage to close this raceway groove for other two adjacent word lines of raceway groove.In this embodiment, can be by applying back bias voltage (as ,-12V) in adjacent word line, to guarantee memory cell C
rthe raceway groove of both sides is closed completely, avoids interference.As shown in Figure 4 B, memory cell C to be programmed
rraceway groove 351
n+1 (2)be positioned between bit line portion 212 ' and source electrode line portion 312 ' adjoining memory cell C
rraceway groove 351
n (2)be positioned between bit line portion 211 ' and source electrode line portion 311 ' adjoining memory cell C
ranother raceway groove 351
n+2 (2)be positioned between bit line portion 213 ' and source electrode line portion 313 '.Memory cell C
rwhen programming, apply individually back bias voltage if-12V is in two adjacent word line WL
n (2)and WL
n+3 (2), to guarantee adjoining memory cell C
rraceway groove 351
n+1 (2)both sides raceway groove 351
n (2)with 351
n+2 (2)can close completely.
FN wipes (FN Erasing Method)
Fig. 5 A is the stacking AND type of the partial 3-D flash memory structure according to the embodiment of the present invention, and wants to carry out the schematic diagram of the memory cell that FN wipes comprehensively.Fig. 5 B is the vertical view of the second plane of Fig. 5 A, and illustrates more multi-word lines clearer related description when reading.In Fig. 1 and Fig. 2 A～2B, some same or similar labels are in order to same or similar element in sign picture 5A～5B.Fig. 5 A and Fig. 5 B also show the operating voltage of each associated word lines, bit line and source electrode line in the three-dimensional stacking structure of embodiment.But those magnitudes of voltage are the use for illustrating only, those of ordinary skill is when after reference example, and visual to carry out the practical application of FN while wiping required, and those magnitudes of voltage are carried out to suitable adjustment.
Referring to Fig. 5 A and Fig. 5 B.As shown in Fig. 5 A, 5B, memory cell C
rcarry out FN while wiping, apply high positive electricity and be pressed on all bit lines (as set of bit lines 21,22) and source electrode line (as source electrode line group 31,32), all word lines impose 0V voltage.
What one unit dibit unit operated reads (Reading by 2bits/cell operation)
The three-dimensional stacked AND type flash memory structure of embodiment is bigrid charge-trapping element (being generally BE-SONOS element), and this bigrid can be encoded independently, make this structure except being suitable for unit one bit (1bit/cell) operation, also can be suitable for the operation of a unit dibit unit (2bits/cell).
Fig. 6 A is according to the schematic diagram of the stacking AND type of the partial 3-D flash memory structure of the embodiment of the present invention, is suitable for the operation of a unit dibit unit.Fig. 6 B is the vertical view of the second plane of three-dimensional stacked AND type flash memory structure in Fig. 6 A, and this memory cell is by monolateral reading (one-sidereading).Same, in figure, choosing place of dotted line circle is memory cell C to be read
r' position, and be positioned at the second plane 12 places, each raceway groove is controlled by two adjacent word lines.In Fig. 1 and Fig. 2 A～2B, some same or similar labels are in order to same or similar element in sign picture 6A～6B.
Moreover Fig. 6 A and Fig. 6 B also show the monolateral read operation voltage of each associated word lines, bit line and source electrode line in the three-dimensional stacking structure of embodiment.But those magnitudes of voltage are the use for illustrating only, those of ordinary skill after can reference example, carries out suitable adjustment to those magnitudes of voltage depending on practical application is required.
As shown in Figure 6B, memory cell C to be read
r' raceway groove 351
n+1 (2)be positioned between bit line portion 212 ' and source electrode line portion 312 ' adjoining memory cell C
r' raceway groove 351
n+1 (2)raceway groove 351
n (2)be positioned between bit line portion 211 ' and source electrode line portion 311 ' adjoining memory cell C
r' raceway groove 351
n+1 (2)another raceway groove 351
n+2 (2)be positioned between bit line portion 213 ' and source electrode line portion 313 '.
Carry out memory cell C
r' monolateral reading time (as Fig. 6 choosing place that B encloses), only have the most close word line WL that reads region
n+2 (2)be applied in bias voltage as+2V voltage, and word line WL
n+1 (2)be applied in 0V voltage.
In embodiment, the bit line of selection (as set of bit lines 31) imposes 1V voltage, and unselected set of bit lines 22, source electrode line group 31 and 32 impose 0V voltage.In other second planes 12, non-selected word line is (as word line WL
n-1 (2), WL
n (2), WL
n+1 (2), WL
n+4 (2)) impose 0V voltage; Other word lines that are positioned at the first plane 11 and the 3rd plane 13 also apply 0V voltage (or lower than erasing voltage Vt), to close other memory cell.
Moreover the interference while reading for avoiding contiguous raceway groove unlatching to cause, can apply back bias voltage to close contiguous raceway groove in adjacent word line.In this embodiment, can be by applying back bias voltage (as ,-3V) in adjacent word line, to guarantee memory cell C
r' other raceway groove is closed completely, avoids interference.As shown in Figure 6B, can be by applying back bias voltage (as-3V) in word line WL
n+3 (2), make adjoining memory cell C
r' the monolateral raceway groove 351 that reads position
n+2 (2)close completely.
The channel hot electron programming (CHE programming by 2bits/celloperation) of one unit dibit unit operation
Fig. 7 A is according to the schematic diagram of the stacking AND type of the partial 3-D flash memory structure of the embodiment of the present invention, is suitable for the operation of a unit dibit unit.Fig. 7 B is the vertical view of the second plane of three-dimensional stacked AND type flash memory structure in Fig. 7 A, and this memory cell is carried out monolateral programming (one-side programming) with channel hot electron programmed method.Same, in figure, choosing place of dotted line circle is select storage unit C
r' position, and be positioned at the second plane 12 places, each raceway groove is controlled by two adjacent word lines.In Fig. 1, Fig. 2 A～2B and Fig. 6 A～6B, some same or similar labels are in order to same or similar element in sign picture 7A～7B.
Moreover Fig. 7 A and Fig. 7 B also show the operating voltage of the monolateral programming of each associated word lines, bit line and source electrode line in the three-dimensional stacking structure of embodiment.But those magnitudes of voltage are the use for illustrating only, those of ordinary skill after can reference example, carries out suitable adjustment to those magnitudes of voltage depending on practical application is required.
As shown in Figure 7 B, memory cell C to be read
r' raceway groove 351
n+1 (2)be positioned between bit line portion 212 ' and source electrode line portion 312 ' adjoining memory cell C
r' raceway groove 351
n+1 (2)raceway groove 351
n (2)be positioned between bit line portion 211 ' and source electrode line portion 311 ' adjoining memory cell C
r' raceway groove 351
n+1 (2)another raceway groove 351
n+2 (2)be positioned between bit line portion 213 ' and source electrode line portion 313 '.
As memory cell C
r' while carrying out monolateral channel hot electron programming (as Fig. 7 choosing place that B encloses), only has the most close word line WL that reads region
n+2 (2)be applied in high voltage, for example, apply 9V voltage, to produce strong vertical electric field to attract electronics, and word line WL
n+1 (2)be applied in 0V voltage.In embodiment, selected word line, as word line group 21, imposes 5V voltage, so that hot electron is pulled to the memory cell C of selection
r'.
In embodiment, unselected set of bit lines 22, source electrode line group 31 and 32 impose 0V voltage.In other second planes 12, non-selected word line is (as word line WL
n-1 (2), WL
n (2), WL
n+1 (2), WL
n+4 (2)) impose 0V voltage; Other word lines that are positioned at the first plane 11 and the 3rd plane 13 also apply 0V voltage (or lower than erasing voltage Vt), to close other memory cell.
Moreover the interference while reading for avoiding contiguous raceway groove unlatching to cause, can apply back bias voltage to close contiguous raceway groove in adjacent word line.In this embodiment, can be by applying back bias voltage (as ,-7V) in adjacent word line, to guarantee memory cell C
r' other raceway groove is closed completely, avoids interference.As shown in Figure 7 B, can be by applying back bias voltage (as-7V) in word line WL
n+3 (2), make adjoining memory cell C
r' the monolateral raceway groove 351 that reads position
n+2 (2)close completely.
The manufacture method > of the three-dimensional stacked AND type of < flash memory structure
Fig. 8 A～8F illustrates the flow process profile according to the manufacture method of the three-dimensional stacked AND type flash memory structure of the embodiment of the present invention.
As shown in Figure 8 A, providing substrate 10, for example, is for being formed with buried oxide layer (buried oxide) 103 on base plate 101.And forming stacked body 50 on the buried oxide layer 103 of substrate 10, this stacked body 50 comprises that the multiple grid layers that alternately form are for example as polysilicon gate layer (poly-gate layers) 501,503,505,506 and multiple insulating barrier (insulation layers) 511,513,515,516, wherein insulating barrier 511,513,515,516 is for example oxide layer (oxide layer), polysilicon gate layer 501,503,505,506 can be used as the material of word line.The application of in an embodiment, can p-type polysilicon gate injecting (lower gate injection) as the lower grid of BE-SONOS element.
Then, carry out the step of wordline patterns.Fig. 8 B carries out the schematic perspective view after wordline patterns in embodiment.In embodiment, to utilize the first photoetching process to carry out patterning to the stacked body 50 of Fig. 8 A, to form multiple character stacked bodies (WL stacks) 52 and to expose the part upper surface 103a of buried oxide layer 103, and after patterning, each character stacked body 52 comprises the patterned polysilicon grid layer 501 ', 503 ' being arranged alternately, 505 ', 506 ', and patterned insulation layer (/ oxide layer) 511 ', 513 ', 515 ', 516 '.Wherein, fit and can be patterned one by one insulating barrier 511 ', 513 ' as those patterned polysilicon grid layers 501 ', 503 ', 505 ', 506 ' of many word lines, 515 ', 516 ' is spaced apart.Moreover as shown in Figure 8 B, each character stacked body 52 extends along X-direction.
Afterwards, form charge-trapping composite bed 54 on those character stacked bodies 52, except covering the upper surface of character stacked body 52, also lining type ground covers sidewall 52a, the 52b of those character stacked bodies 52 and the part upper surface 103a of the buried oxide layer 103 that exposes.Wherein, charge-trapping composite bed 54 is for example the lamination of oxide and nitride, as ONO lamination or ONONO lamination or BE-SONOS composite bed.Fig. 8 C forms the schematic perspective view after charge-trapping composite bed in embodiment.As shown in Figure 8 C, carry out charge-trapping composite bed and form after step, also between those character stacked bodies that are lined with this charge-trapping composite bed, form groove (trench) 55.In an embodiment, groove 55 is for example about 20nm or the width that is greater than 20nm, but the present invention is not as limit.
Then, depositing conducting layer 57 (as polysilicon layer), on character stacked body 52, and covers charge-trapping composite bed 54 and fills up groove 55.Wherein conductive layer 57 is for example if any doping or undoped p-type polysilicon.Fig. 8 D forms the schematic perspective view after conductive layer in embodiment.57 contact charge-trapping composite beds 54 after conductive layer deposition.
Afterwards, patterned conductive layer 57 is to form multiple bit stacked bodies (BL stacks) 58, as shown in Fig. 8 E.Fig. 8 E forms the schematic perspective view after bit stacked body in embodiment.After patterned conductive layer 57, adjacent bit stacked body 58 is separated by gap (gaps) 59, and also exposes the part surface of charge-trapping composite bed 54.Moreover as shown in Fig. 8 E, each bit stacked body 58 extends along Y-direction.
Referring to Fig. 8 B and Fig. 8 E.After patterned conductive layer 57, each bit stacked body 58 its bearing of trend (being Y-direction) forming are mutually vertical with the bearing of trend (being X-direction) of each character stacked body 52.Moreover, the bearing of trend (being X-direction) of each groove 55 that character stacked body is 52 also with bit stacked body 58 between the bearing of trend (being Y-direction) in each gap 59 mutually vertical.
Then, form respectively two doped regions 582,583 (as n+ doped region) in the both sides of each bit stacked body 58, and raceway groove 585 vertically arranges between two doped regions 582,583.In embodiment, the raceway groove 585 being formed between two doped regions 582,583 is p-type light dope raceway groove.In doping step, the surface element of the charge-trapping composite bed 54 that can expose the both sides of each bit stacked body 58 and 59 places, gap between those adjacent bit stacked bodies 58 divides and adulterates, to form two septs in the both sides of each bit stacked body 58 as inter polysilicon parting (poly spacers, as 582,583) to fit as bit line and source electrode line, and gap location 59 between adjacent bit stacked body 58 forms bottom interval thing (bottom spacer) (not being shown in Fig. 8 F).Afterwards, remove the bottom interval thing of the gap location 59 between adjacent bit stacked body 58, to completely cut off those bit stacked bodies 58.Fig. 8 F shows and removes the bit line that forms after bottom interval thing and the schematic perspective view of source electrode line.Wherein, remove after bottom interval thing, expose the part surface of charge-trapping composite bed 54.
As shown in Figure 8 F, each raceway groove 585 that bit stacked body is 58 is perpendicular to charge-trapping composite bed 54, also vertical with the bearing of trend (being X-direction) of each word line of character stacked body 52.
Therefore, the manufacture method of three-dimensional stacked AND type flash memory structure as above is not only simple and can significantly shorten the process time.The manufacturing process that embodiment proposes first carries out the patterning (as shown in Figure 8 B) of word line, then carries out the patterning (as shown in Fig. 8 E) of bit line.And in the three-dimensional stacked AND type flash memory structure of embodiment, many word lines of multiple horizontal planes can utilize one photoetching process once to form (please refer to Fig. 8 A～8B) quickly and accurately.And equally also can utilize quickly and accurately another road photoetching process once to form perpendicular to bit line, source electrode line and the raceway groove of substrate.Therefore, the manufacture method of the three-dimensional stacked AND type flash memory structure that embodiment proposes, only utilizes twice photoetching process to reach autoregistration, simple, can significantly to shorten this three-dimensional stacking structure process time and saving manufacturing cost.
The alternate embodiment > of the three-dimensional stacked AND type of < flash memory structure
The three-dimensional stacking structure of above-described embodiment can change a little, referring to Fig. 1 and Fig. 9.As shown in Figure 9, the schematic diagram of its stacking AND type of partial 3-D flash memory structure that is alternate embodiment of the present invention.Under the help of safe socket layer-selective transistor (Secure Sockets Layer (SSL) selectiontransistors), can make bit line select more easy.Wherein, as shown in Figure 9, in three-dimensional stacking structure 60, first and second safe socket layer-selective transistor SSL1 and SSL2 are positioned at one deck memory cell plane (as memory cell plane 11) of top, and being positioned at the word line of same layer memory cell plane, below can be electrically connected, and form the first common gate G1 and the second common gate G2 in two-layer memory cell plane 12 and 13 respectively, so can make bit line decoding more easily and simplify.Moreover, while applying structure as shown in Figure 9, also can carry out the operation of channel hot electron programming (CH ElectronProgramming) or FN tunneling program (FN Programming Method) to it as above-described embodiment.
In addition, the three-dimensional stacking structure of above-described embodiment also can change a little again, referring to Fig. 1 and Figure 10.As shown in figure 10, the schematic diagram of its stacking AND type of partial 3-D flash memory structure that is another alternate embodiment of the present invention.The structure of Figure 10 and the structural similarity of Fig. 9, equally in three-dimensional stacking structure 70, the memory cell plane (as memory cell plane 11) of layer arranges first and second safe socket layer-selective transistor SSL1 and SSL2 up, and below is positioned at the word line electric connection of same layer memory cell plane, to form the first common gate G1, the second common gate G2 and the 3rd common gate G3 in three layers of memory cell plane 12,13 and 14 respectively.And in the structure of Figure 10, make the two adjacent bit line portions that imbed and imbed source electrode line portion (as the 222b of the bit line portion that imbeds in Fig. 1 and imbed the 322b of source electrode line portion) to be electrically connected, to form the three-dimensional stacked flash memory structure of virtual earth AND kenel array (virtual-ground AND-type array).Moreover, while applying structure as shown in figure 10, also can carry out the operation of channel hot electron programming (CH Electron Programming) or FN tunneling program (FN Programming Method) to it as above-described embodiment.
Above embodiment is to make related description with three-dimensional stacked AND type flash memory structure and manufacture method thereof.In sum, the three-dimensional stacked AND type flash memory structure proposing in embodiment has vertical-channel (vertical channels), is positioned at and imbeds bit line (as n+ doping) and imbed between source electrode line (as n+ doping).Because the metal oxide semiconductcor field effect transistor (MOSFET) of the three-dimensional stacked AND type flash memory structure of embodiment is arranged in parallel, but not as the series connection setting in NAND gate (NAND) type flash memory structure, therefore the reading speed of the AND type flash memory structure of embodiment is faster compared with the reading speed of NAND gate type flash memory structure.Moreover, the three-dimensional stacked AND type flash memory structure of embodiment can be programmed (channel hot electron programming) with channel hot electron by similar NOR type flash memory, or similar NAND type flash memory is programmed by FN tunnelling (Fowler-Nordheim Tunneling).Moreover, because the structure of embodiment is bigrid charge-trapping element, this bigrid can be encoded independently, make this structure can be suitable for the operation of a unit dibit unit, therefore the structure of embodiment can be suitable for unit one bit (1bit/cell) operation, also can be suitable for a unit dibit unit (2bits/cell) operation.Moreover the manufacture method that embodiment proposes only utilizes twice photoetching process can simply and accurately reach the autoregistration of structure, thereby can significantly shorten the process time and save manufacturing cost.
In sum, although the present invention discloses as above with preferred embodiment, so it is not in order to limit the present invention.Persons of ordinary skill in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when defining and be as the criterion depending on claim.
Claims (9)
1. a three-dimensional stacked AND type flash memory structure, comprising:
Multiple memory cell planes, are arranged to three-dimensional arrangement, and each this memory cell plane comprises that many word lines and multiple charge-trapping composite bed are staggered, and two adjacent word lines are spaced from each other with each this charge-trapping composite bed arranging wherein;
Multiple set of bit lines and multiple source electrode line group, be staggered and perpendicular to the plurality of memory cell plane layout; And
Multiple raceway groove groups and multiple insulation cylinder group, be staggered and perpendicular to the plurality of memory cell plane layout, and each this raceway groove group is arranged between this adjacent set of bit lines and this source electrode line group, wherein this set of bit lines is arranged between adjacent this insulation cylinder group and this raceway groove group, and this insulation cylinder is arranged between adjacent this source electrode line group and this set of bit lines.
2. structure as claimed in claim 1, wherein each this set of bit lines comprises and multiplely imbeds bit line portion, and the plurality of bit line portion of imbedding is not between adjacent the plurality of memory cell plane.
3. structure as claimed in claim 2, wherein each this source electrode line group comprises and multiplely imbeds source electrode line portion, and the plurality of source electrode line portion that imbeds lays respectively between adjacent the plurality of memory cell plane.
4. structure as claimed in claim 3, wherein each this raceway groove group comprises multiple vertical channel regions, and each this vertical channel region is arranged at, and adjacent this imbedded bit line portion and this is imbedded between source electrode line portion.
5. a manufacture method for three-dimensional stacked AND type flash memory structure, comprising:
Substrate is provided;
Alternately form multiple grid layers and multiple insulating barrier on this substrate;
The plurality of grid layer of patterning and the plurality of insulating barrier, to form multiple character stacked bodies, and each this character stacked body comprises the patterned gate and the patterned insulation layer that are arranged alternately after patterning, the plurality of patterned gate is as many word lines and be patterned insulating barrier and separate;
Form charge-trapping composite bed on the plurality of character stacked body, and lining type ground covers the sidewall of the plurality of character stacked body, and form multiple grooves and lay respectively between the plurality of character stacked body that is lined with this charge-trapping composite bed;
Depositing conducting layer is on the plurality of character stacked body and fill up the plurality of groove;
This conductive layer of patterning is to form multiple bit stacked bodies, and the plurality of bit stacked body is alternatively separated by multiple gap; And
Both sides in each this bit stacked body form respectively two doped regions, and raceway groove is vertically arranged between this two doped region, and wherein adjacent the plurality of bit stacked body is mutually isolated.
6. manufacture method as claimed in claim 5, wherein at this conductive layer of patterning to form after the step of the plurality of bit stacked body, expose the part surface of this charge-trapping composite bed.
7. manufacture method as claimed in claim 6, wherein forms respectively in the step of two these doped regions in the both sides of each this bit stacked body, comprising:
For the both sides of each this bit stacked body and between the plurality of adjacent bit stacked body the exposed surface portion thereof of this charge-trapping composite bed of this gap location adulterate, to form two septs in the both sides of each this bit stacked body using as bit line and source electrode line, and this gap location between the plurality of adjacent bit stacked body forms bottom interval thing;
Remove this bottom interval thing of this gap location between the plurality of adjacent bit stacked body, to completely cut off the plurality of bit stacked body, wherein remove after this bottom interval thing, expose the part surface of this charge-trapping composite bed.
8. a method of operation for flash memory structure, comprising:
Three-dimensional stacked AND type flash memory structure is provided, this structure comprises that multiple memory cell plane layouts become three-dimensional arrangement, multiple set of bit lines, multiple source electrode line groups, multiple raceway groove groups and multiple insulation cylinder group, and each this memory cell plane comprises that many word lines and multiple charge-trapping composite bed are staggered, two adjacent word lines are spaced from each other with each this charge-trapping composite bed arranging wherein, the plurality of set of bit lines and the plurality of source electrode line group are staggered and perpendicular to the plurality of memory cell plane layout, the plurality of raceway groove group and the plurality of insulation cylinder group are staggered and perpendicular to the plurality of memory cell plane layout, and each this raceway groove group is arranged between this adjacent set of bit lines and this source electrode line group,
Select storage unit, and this memory cell is positioned at one of them plane place of the plurality of memory cell plane;
In this memory cell plane place at selected this memory cell place, respectively apply operating voltage in two word lines of this memory cell of next-door neighbour, be close to this two words line of this memory cell with conducting;
Close contiguous conducting this two words line outside two these raceway grooves at least one of them; And
Apply relevant voltage in selected the plurality of set of bit lines and at least one of them group of the plurality of source electrode line group, and impose 0V voltage in all the other unselected the plurality of set of bit lines and the plurality of source electrode line group.
9. method of operation as claimed in claim 8, wherein has two contiguous raceway grooves in the outside of this two words line of conducting, by apply negative bias be pressed on corresponding word line with close completely this two contiguous raceway groove at least one of them.
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| JP6623247B2 (en) * | 2018-04-09 | 2019-12-18 | ウィンボンド エレクトロニクス コーポレーション | Flash memory and manufacturing method thereof |
| CN109378313B (en) * | 2018-09-23 | 2020-10-30 | 复旦大学 | Low-power-consumption three-dimensional nonvolatile memory and preparation method thereof |
| US11778819B2 (en) | 2020-07-22 | 2023-10-03 | Winbond Electronics Corp. | NAND flash memory with reduced planar size |
| CN114141772A (en) * | 2020-09-04 | 2022-03-04 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method and control method thereof |
| EP3985672B1 (en) | 2020-09-04 | 2024-01-24 | Changxin Memory Technologies, Inc. | Semiconductor structure, and fabrication method and control method therefor |
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| KR101037621B1 (en) * | 2008-05-13 | 2011-05-27 | 재단법인서울대학교산학협력재단 | And type flash memory array having vertically stacked structure and manufacturing method and operating method of the same |
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