CN102637459B - Nonvolatile memory devices - Google Patents

Nonvolatile memory devices Download PDF

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Publication number
CN102637459B
CN102637459B CN201110435822.9A CN201110435822A CN102637459B CN 102637459 B CN102637459 B CN 102637459B CN 201110435822 A CN201110435822 A CN 201110435822A CN 102637459 B CN102637459 B CN 102637459B
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circuit
voltage
bit line
size
reference voltage
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CN102637459A (en
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谷川博之
仓盛文章
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Lapis Semiconductor Co Ltd
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Lapis Semiconductor Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells

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Abstract

A kind of Nonvolatile memory devices, can suppress the generation of access delay.This Nonvolatile memory devices is before the comparing of size of the size of voltage with the reference voltage (VREF) of reference voltage line (40) of carrying out bit line (BL), charge with constant voltage (VREFEQ) pairs of bit line (BL) with charging circuit (114), then series circuit (58) is utilized to generate potential difference corresponding to the difference of the size of the size of reference voltage (VREF) and the voltage of bit line (BL) with potential difference output circuit (116B), and be absorbed in PMOS transistor (60C) and nmos pass transistor (62A by coupling counters circuit (34), the coupling electric charge produced 62C), in order to suppress the PMOS transistor (60C) of series circuit (58) and nmos pass transistor (62A along with the beginning of charging, the rising of grid voltage 62C).

Description

Nonvolatile memory devices
Technical field
The present invention relates to can the Nonvolatile memory devices of electronically written.
Background technology
As existing nonvolatile memory, such as, known a kind of nonvolatile memory as described below, that is: multiple storage unit is arranged in respectively on wordline WL and bit line BL and forms memory cell array, and the bit line of the storage unit as reading object is connected to read-out amplifier successively via selection circuit, and by utilizing read-out amplifier to read data to the mode that the size of the bit-line voltage be connected in storage unit and the size of reference voltage compare.
But, store the data of the logical value of expression " 1 " or " 0 " in the memory unit.Bit line BL is according to being stored in as the data in the storage unit of reading object, the size of its voltage changes, but due in the reading etc. of the data " 0 " after the reading of data " 1 ", bit line BL needs the time, one of this reason becoming access delay become the steady state (SS) that can judge to read (read) 0 by charging till.
As the technology solving this problem, in patent documentation 1, when disclosing one from bit line BL reading data, by utilizing the builtin voltage CSV generated by internal electric source to carry out precharge, thus make the technology of the reading high speed of data.
Patent documentation 1: Japanese Unexamined Patent Publication 2007-149296 publication.
But, the size of builtin voltage CSV not necessarily and reference voltage in the same size.Therefore, when the size of builtin voltage CSV is greater than the size of reference voltage, by precharge, bit line BL is charged the size exceeding reference voltage, causes producing overshoot (overshoot).On the contrary, when the size of builtin voltage CSV is less than the size of reference voltage, although by precharge, be shortened during the visit, because bit line BL is charged after precharging, need the time till therefore becoming steady state (SS).So, in existing nonvolatile memory, due to the size of builtin voltage CSV and not necessarily and reference voltage in the same size, so can there are the following problems, namely there is the situation producing memory access and postpone.Wherein, in this manual, except will the meaning of capacity cell accumulated charge be made to be called except " charging ", also will execute alive situation to wiring and also broadly be referred to as " charging ".Be called that " charging " is the consideration making this stray capacitance accumulated charge for there is stray capacitance in wiring.
Summary of the invention
The present invention proposes to solve the problem, and its object is to provides a kind of Nonvolatile memory devices that can suppress the generation of access delay.
To achieve these goals, the structure of the Nonvolatile memory devices recorded in scheme 1 comprises: bit line, with can electronically written ground logical value storage non-volatile memory element be connected, be applied in the voltage that size is corresponding with the logical value be stored in this memory element; Charhing unit, the size of carrying out the voltage putting on described bit line with put on reference voltage line reference voltage size compare identify described logical value time, this relatively before, described charhing unit utilizes the sizable voltage of size and described reference voltage to charge to this bit line; Voltage generating unit, be connected between described reference voltage line and described bit line, and there is the capacitive load producing coupling electric charge when charging with described charhing unit, the voltage corresponding to difference utilizing this capacitive load to generate the size of the size of the voltage of described reference voltage line and the voltage of described bit line is used as the voltage representing described comparative result; And electric charge absorptive unit, absorb the coupling electric charge that above-mentioned capacitive load produces.
According to the present invention, this effect of generation that can suppress access delay can be obtained.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of an example of the schematic configuration of the nonvolatile memory schematically showing the first embodiment.
Fig. 2 is the pie graph of an example of the schematic configuration of the nonvolatile memory representing the first embodiment.
Fig. 3 is the pie graph of an example of the formation of the major part of the amplifier representing the first embodiment.
Fig. 4 is the sequential chart of an example of the transition status of the signal represented in the nonvolatile memory of the first embodiment.
Fig. 5 is the pie graph of an example of the formation of the major part of the amplifier representing the second embodiment.
Fig. 6 is the sequential chart of the transition status of the signal represented in the nonvolatile memory of the second embodiment.
Fig. 7 is the pie graph of an example of the basic comprising of the nonvolatile memory representing embodiment.
Fig. 8 is the pie graph of an example of the basic comprising of the amplifier representing embodiment.
Description of reference numerals is as follows:
10... nonvolatile memory; 15... amplifier;
32, the different bit line amplifier of 82...; 34... coupling counters circuit;
68,84A...NMOS transistor; 70... circuit for reversing;
84... separation circuit; 102... storage unit;
110... reference amplifiers; 112... constantvoltage generation circuit;
114... charging circuit.
Embodiment
Below, be described for implementing the specific embodiment of the present invention with reference to accompanying drawing.
First, the basic comprising of the nonvolatile memory of present embodiment is described.Fig. 7 is the structural drawing of an example of the basic comprising of the nonvolatile memory representing present embodiment.As shown in this figure, nonvolatile memory 100 is configured to comprise: memory cell array 104, is arranged multiple storage unit 102 formed by rectangular; Amplifier 105, it is for reading from storage unit 102 and exporting data; Latch cicuit 106, it keeps the data exported from amplifier 105; And output circuit 107, it externally exports after data kept by latch cicuit 106 being taken out.Be arranged in parallel with in memory cell array 104 by many decoded wordline WL (WL from outside Input Address 0, WL 1, WL y).On the direction intersected relative to these many wordline WL, many numbers are defeated bit line BL (BL reportedly 0, BL 1, BL x) configure side by side across predetermined distance.In addition, near each bit line BL, be configured with many drain line DL (DL of the current potential of the drain terminal side for drop-down storage unit 102 concurrently with them 0, DL 1, DL x).
Amplifier 105 is arranged on each bit lines BL, and its structure comprises: different bit line amplifier 108, and it is current detection type amplifier; Reference current generating circuit 109, it produces reference current IREF; Reference amplifiers (referenceamplifier) 110, the reference current IREF produced by reference current generating circuit 109 is converted to reference voltage VREF by it; Constantvoltage generation circuit 112, it produces the size constant voltage VREFEQ identical with the size of the reference voltage VREF obtained by reference amplifiers 110; And charging circuit 114, it is arranged by each different bit line amplifier 108, utilizes corresponding different bit line amplifier 108 pairs of bit line BL to charge.
The structure of different bit line amplifier 108 comprises: amplifier body 116, and it generates and corresponds to via the bit line BL of correspondence from the electric current I CELL (ICELL that storage unit 102 inputs 0, ICELL 1, ICELL x) size and the voltage of difference of size of reference current IREF; And logical circuit 118, the voltage transitions generated by amplifier body 116 is that logical value exports by it.
An example of the basic comprising of the amplifier 105 of nonvolatile memory 100 has been shown in Fig. 8.As shown in this figure, the structure of the amplifier body 116 of different bit line amplifier 108 comprises: initialization executive circuit 116A, it becomes earthing potential by the current potential of the source terminal making storage unit 102, storage unit 102 is initialized as the state of readable data; And potential difference output circuit 116B, the electric current flowing through bit line BL is converted to voltage by it, and generate and correspond to conversion and the voltage (hereinafter referred to as " potential difference ") of the difference of the size of the size of voltage that obtain and the reference voltage VREF that utilizes reference amplifiers 110 to obtain, and export to logical circuit 118.In addition, different bit line amplifier 108 is to be consisted of charging circuit 114 mode that constant voltage VREFEQ pairs of bit line BL carries out charging.
In the different bit line amplifier 108 of this structure, when reading data from storage unit 102, first, the current potential of the source terminal of storage unit 102 is initialised by initialization executive circuit 116A.Then, after bit line BL is charged with constant voltage VREFEQ by charging circuit 114, from potential difference output circuit 116B output difference voltage.If the size of the electric current I CELL be transfused to via bit line BL from storage unit 102 is greater than the size of reference current IREF, then become larger than reference voltage VREF from the size of the potential difference of potential difference output circuit 116B output, if be less than the size of reference current IREF from the size of the electric current I CELL of storage unit 102 output, then become less than reference voltage VREF from the size of the potential difference of potential difference output circuit 116B output.Therefore, whether logical circuit 118 is larger than reference voltage VREF by judging the size of the potential difference inputted from potential difference output circuit 116B, identifies by the logical value of the data representation of storage unit 102.
Like this, by utilizing constant voltage VREFEQ pairs of bit line BL to charge before generation potential difference, thus compared with the technology recorded with patent documentation 1, the generation of the access delay to storage unit 102 can be suppressed.
But as shown in Figure 8, potential difference output circuit 116B is configured to comprise following circuit, that is, this circuit by multiple P channel-type MOS field effect transistor (hereinafter referred to as " PMOS transistor ".) the PMOS series connection portion 60 that is in series and multiple N channel-type MOS field effect transistor be (hereinafter referred to as " nmos pass transistor ".) the NMOS series connection portion 62 that is in series is in series.In addition, in potential difference output circuit 116B, as shown in the drawing, each gate terminal of the gate terminal of a PMOS transistor in PMOS series connection portion 60 and two nmos pass transistors in NMOS series connection portion 62 is connected via the lead-out terminal of reference voltage line with reference amplifiers 110, thus be applied in reference voltage VREF, and connect with NMOS in PMOS series connection portion 60, the contact in portion 62 is connected on the input terminal of logical circuit 118, and the source terminal being connected directly between the nmos pass transistor in PMOS series connection portion 60 is connected with bit line BL.Thus, potential difference output circuit 116B can generate the potential difference of the logical value represented by data that identifiable design stores as the storage unit 102 of digital independent object, and exports to logical circuit 118.
But, in potential difference output circuit 116B, when the charging based on charging circuit 114 starts, because the grid capacitance of PMOS transistor and nmos pass transistor can cause grid voltage to rise, therefore the size of grid voltage is difficult to the size being maintained reference voltage VREF.In addition, reference amplifiers 110 is series circuits identical with potential difference output circuit 116B, in other words, as shown in Figure 8, reference amplifiers 110 has: the series circuit be in series by the NMOS series connection portion that the PMOS series connection portion identical with PMOS series connection portion 60 is identical with portion 62 of connecting with NMOS, and due to by this series circuit generating reference voltage VREF, so supply the scarce capacity of reference voltage VREF to potential difference output circuit 116B.Therefore, the PMOS transistor of potential difference output circuit 116B and the grid voltage of nmos pass transistor are once rise, revert to reference voltage VREF also stablizes to this grid voltage and need the time, therefore comprise the possibility access of storage unit 102 being delayed by this time degree.
Therefore, in the first following embodiment and the second embodiment, disclose a kind of nonvolatile memory that can reduce the possibility that access is delayed by further.
In addition, below, to the formation identical with the amplifier 105 shown in the nonvolatile memory 100 shown in Fig. 7 and Fig. 8, give identical Reference numeral, and the description thereof will be omitted.
[the first embodiment]
An example of the formation of the nonvolatile memory 10 of this first embodiment is schematically illustrated in Fig. 1.As shown in the drawing, nonvolatile memory 10 has multiple memory cell array 104.Their shared write circuits 12 and bad wordline relief circuit 14 are provided with to multiple memory cell array 104.Write circuit 12 is the circuit of voltage storage unit 102 being applied for rewrite data.Bad wordline relief circuit 14 is when there is bad wordline WL, uses the tediously long circuit that the wordline of preparation is administered relief.
In addition, multiple memory cell array 104 is respectively arranged with amplifier 15, the relief of bad bit line circuit 16, latch cicuit 106 and ECC logical circuit 20.Amplifier 15 has the function of the amplifier 105 shown in Fig. 8.Bad bit line relief circuit 16 is for when there is bad bit line BL, uses the tediously long circuit that the bit line of preparation is administered relief.Latch cicuit 106 for keep from amplifier 105 export data represented by logical value.ECC logical circuit 20 causes the logical value from amplifier 105 output error in the defect because of storage unit 102, detect and the mistake of correction logic value.
In addition, multiple memory cell array 104 is provided with the imput output circuit 22 shared separately, and the output of the logical value represent the input of the address date of the address for determining storage unit 102, identifying with amplifier 105 is carried out respectively by imput output circuit 22.
Further, in nonvolatile memory 10, be provided with word decoder driver 26, internal electric source 28, reference current generating circuit 109 and clock signal produce circuit 30.Word decoder driver 26 is applied for the voltage reading data from the wordline WL of the determined storage unit 102 in the address represented by the address date inputted by imput output circuit 22.Internal electric source 28 supplies after the external voltage VCC transformation supplied from external power source (omitting diagram) to each portion as builtin voltage VCD.It is form the circuit of clock signal during the action in each portion of nonvolatile memory 10 for generation of being used for regulation that clock signal produces circuit 30.
An example of the formation of the nonvolatile memory 10 of this first embodiment is diagrammatically illustrated in Fig. 2.Nonvolatile memory 10 compared with the nonvolatile memory 100 shown in Fig. 7, on the point employing amplifier 15 replacing amplifier 105 and different on the point being provided with latch cicuit 18.
In memory cell array 104, the floating grid of each storage unit 102 is connected with wordline WL respectively, and the source terminal of each storage unit 102 is connected with bit line BL, and the drain terminal of each storage unit 102 is connected with drain line DL.
Each bit line BL is connected with amplifier 15.Amplifier 15 is compared with the amplifier 105 shown in Fig. 8, different on the point employing different bit line amplifier 32 replacing different bit line amplifier 108.Different bit line amplifier 32 is compared with the different bit line amplifier 108 shown in Fig. 8, different on the point being newly provided with coupling counters circuit 34.
The amplifier body 116 of different bit line amplifier 32 is connected with corresponding bit line BL.In addition, amplifier body 116 is connected with coupling counters circuit 34.In addition, coupling counters circuit 34 and clock signal produce circuit 30 and are connected, and are transfused to signal TAMP during the action that represents with high level during the action of amplifier 15.In addition, in different bit line amplifier 32, the input terminal of logical circuit 118 is connected with amplifier body 116, is supplied to potential difference VOUT from amplifier body 16.
Each different bit line amplifier 32 is respectively arranged with latch cicuit 106 and output circuit 107.Output circuit 107 is assembled in imput output circuit 22 as shown in Figure 1.The lead-out terminal of logical circuit 118 connects with the input terminal of corresponding latch cicuit 106, and the lead-out terminal of latch cicuit 106 connects with the input terminal of corresponding output circuit 107.In addition, latch cicuit 106 and clock signal produce circuit 30 and are connected, be transfused to the data that (latch) can be kept to input during with high level represent latch during signal TLAT.In addition, the state of data can be kept by latch cicuit 106 to be below referred to as " can latch mode ".
Therefore, amplifier body 16 output difference voltage VOUT (VOUT 0, VOUT 1, VOUT x), logical circuit 118 by after the potential difference VOUT logic value that supplies from amplifier body 16, output logic value SOUT (SOUT 0, SOUT 1, SOUT x).Then, latch cicuit 106 according to from clock signal produce circuit 30 input latch during signal TLAT, keep from logical circuit 118 input logical value SOUT.By the logical value SOUT that latch cicuit 106 keeps, by ECC logical circuit 20 implementation mistake correction as required, and as logical value SOUTLAT (SOUTLAT0, SOUTLAT 1, SOUTLAT x) export to output circuit 107.
The lead-out terminal of reference current generating circuit 109 is connected with the input terminal of reference amplifiers 110.The lead-out terminal of reference amplifiers 110 is connected with the amplifier body 116 of the input terminal of constantvoltage generation circuit 112 and variant bit line amplifier 32.The lead-out terminal of constantvoltage generation circuit 112 is connected with the input terminal of the input terminal of each charging circuit 114 and the coupling counters circuit 34 of variant bit line amplifier 32.In addition, charging circuit 114 and clock signal produce circuit 30 and are connected, and are transfused to signal TAMPC between the charge period that represents with high level between the charge period of carrying out charging.Wherein, 30ns is set in the present first embodiment by between charge period, this time be from be charged to the voltage of the wordline WL of storage unit 102 size reach the time of the size of the voltage that can read the data be stored in storage unit 102 after continue time more than needed of number ns further, it be by estimating that the current potential of bit line BL reaches the time till stablizing and carries out setting.
Fig. 3 illustrates an example of the formation of the amplifier 15 of this first embodiment.As shown in the drawing, the structure of reference amplifiers 110 comprises: each gate terminal is connected to clock signal and produces nmos pass transistor 112A, 112B on circuit 30 and series circuit 112C.
The structure of series circuit 112C comprises: the PMOS series connection portion 36 that PMOS transistor 36A, 36B, 36C are in series and the NMOS series connection portion 38 that nmos pass transistor 38A, 38B, 38C are in series.Source terminal as the PMOS transistor 36A of the one end in PMOS series connection portion 36 is connected with the external voltage line being applied in external voltage VCC, and the drain terminal as the PMOS transistor 36C of the other end in PMOS series connection portion 36 is connected with the drain terminal of the nmos pass transistor 38A of the one end as NMOS series connection portion 38.In addition, the source terminal as the nmos pass transistor 38C of the other end in NMOS series connection portion 38 is grounded.
The gate terminal of PMOS transistor 36B is grounded.In addition, each gate terminal of PMOS transistor 36A and nmos pass transistor 112A, 112B is connected on clock signal generation circuit 30.Each gate terminal of pair pmos transistor 36A and nmos pass transistor 112B produces by clock signal the signal that circuit 30 inputs same level, and the gate terminal of pair nmos transistor 112A produces circuit 30 by clock signal and inputs the signal reversed to this signal.
Producing the signal of circuit 30 to each gate terminal input of PMOS transistor 36A and nmos pass transistor 112A, 112B from clock signal, being different from when not reading the non-action of data by amplifier 15 from storage unit 102 when reading the action of data by amplifier 15 from storage unit 102.In other words, when action, (this low level is each gate terminal input low level of pair pmos transistor 36A and nmos pass transistor 112B: in PMOS transistor, during gate terminal input, make to become conducting state between source terminal and drain terminal, and in nmos pass transistor, during gate terminal input, make the signal level becoming nonconducting state between source terminal and drain terminal) signal STBY, (this high level is the gate terminal input high level of pair nmos transistor 112A: in PMOS transistor, during gate terminal input, make to become nonconducting state between source terminal and drain terminal, and in nmos pass transistor, during gate terminal input, make the signal level becoming conducting state between source terminal and drain terminal) signal STBYB.On the other hand, when non-action, the signal STBY of each gate terminal input high level of pair pmos transistor 36A and nmos pass transistor 112B, the signal STBYB of the gate terminal input low level of pair nmos transistor 112A.
The drain terminal of nmos pass transistor 112A is connected to the lead-out terminal of reference current generating circuit 109 via the input terminal of reference amplifiers 110.In addition, the source terminal of nmos pass transistor 112A is connected to the contact of the source terminal of the nmos pass transistor 38A in NMOS series connection portion 38 and the drain terminal of nmos pass transistor 38B.
Each gate terminal of nmos pass transistor 38A, 38B, 38C and the gate terminal of PMOS transistor 36C are interconnected, and are connected to the contact of the drain terminal of PMOS transistor 36C and the drain terminal of nmos pass transistor 38A.
The source terminal of nmos pass transistor 112B is grounded.In addition, the drain terminal of nmos pass transistor 112B is connected on each gate terminal of nmos pass transistor 38A, 38B, 38C and the gate terminal of PMOS transistor 36C.Further, the drain terminal of nmos pass transistor 112B is connected with reference voltage line 40.Therefore, reference amplifiers 110 exports via reference voltage line 40 after the reference current IREF inputted from reference current generating circuit 109 can being converted to reference voltage VREF.
The structure of constantvoltage generation circuit 112 comprises: operational amplifier 42, capacitor 44 and bleeder circuit 46.Bleeder circuit 46 is in series by PMOS transistor 46A and resistor 46B.The source terminal of PMOS transistor 46 is connected with the external voltage line being applied in external voltage VCC, and the drain terminal of PMOS transistor 46 is connected with one end of resistor 46B, and the other end of resistor 46 is grounded.The non-inverting input terminal of operational amplifier 42 is connected with reference voltage line 40, the inverting input connecting terminals of operational amplifier 42 receives the contact 46C of PMOS transistor 46 and resistor 46B and one end of capacitor 44, and the lead-out terminal of operational amplifier 42 is connected with the other end of the gate terminal of PMOS transistor 46 and capacitor 44.Therefore, constantvoltage generation circuit 112 can produce the size constant voltage VREFEQ equal with the reference voltage VREF be supplied to via reference voltage line 40 from reference amplifiers 110 at contact 46C.
The structure of charging circuit 114 comprises: nmos pass transistor 48.The drain terminal of nmos pass transistor 48 is connected with the contact 46C of constantvoltage generation circuit 112, and the source terminal of nmos pass transistor 48 connects with corresponding bit line BL.In addition, the gate terminal of nmos pass transistor 48 is connected to clock signal via transmission line 50 and produces circuit 30.Therefore, in during between the charge period being transferred to transmission line 50, the signal level of signal TAMPC is high level, owing to being conducting state between the source terminal of nmos pass transistor 48 and drain terminal, so the bit line BL of correspondence charges with constant voltage VREFEQ; Between the charge period being transferred to transmission line 50, the signal level of signal TAMPC is in low level period, owing to being nonconducting state between the source terminal of nmos pass transistor 48 and drain terminal, so the bit line BL of correspondence is not charged.
Initialization executive circuit 116A is in series by PMOS transistor 54 and nmos pass transistor 56.The source terminal of PMOS transistor 54 is connected with internal electric source 28 (with reference to Fig. 1), and is applied in builtin voltage VCD.In addition, the drain terminal of PMOS transistor 54 is connected with the drain terminal of nmos pass transistor 56, and the source terminal of nmos pass transistor 56 is grounded.In addition, PMOS transistor 54 is connected with bit line BL with the contact of nmos pass transistor 56.And, gate terminal and the clock signal of PMOS transistor 54 produce circuit 30 and are connected, and signal TAMPB during producing from clock signal the reversion action that circuit 30 inputs as the reverse signal of signal TAMP during the action will represented with high level during the action of amplifier 15.
The gate terminal of nmos pass transistor 56 also produces circuit 30 with clock signal and is connected, the interdischarge interval signal TDIS represented with high level during bit line BL being discharged from clock signal generation circuit 30 initial stage inputted during the action of amplifier 15.
The structure of potential difference output circuit 116B comprises series circuit 58.The structure of series circuit 58 comprises: the PMOS series connection portion 60 be in series by PMOS transistor 60A, 60B, 60C and the NMOS series connection portion 62 be in series by nmos pass transistor 62A, 62B, 62C.The contact of nmos pass transistor 62A and nmos pass transistor 62B is connected on bit line BL.In other words, the contact of nmos pass transistor 62A and nmos pass transistor 62B is connected to PMOS transistor 54 and the contact of nmos pass transistor 56 and the source terminal of nmos pass transistor 48 via bit line BL.
In addition, the source terminal as the PMOS transistor 60A of the one end in PMOS series connection portion 60 is connected with the external voltage line being applied in external voltage VCC; Drain terminal as the PMOS transistor 60C of the other end in PMOS series connection portion 60 is connected with the drain terminal of the nmos pass transistor 62A of the one end as NMOS series connection portion 62.In addition, the source terminal as the nmos pass transistor 62C of the other end in NMOS series connection portion 62 is grounded.
In series circuit 58, gate terminal and the clock signal of the PMOS transistor 60A in PMOS series connection portion 60 produce circuit 30 and are connected, and produce signal TAMPB during circuit 30 inputs reversion action from clock signal.In addition, the gate terminal of the PMOS transistor 60B in PMOS series connection portion 60 is grounded.In addition, each gate terminal of PMOS transistor 60C and nmos pass transistor 62A, 62C is interconnected, and is connected to reference voltage line 40.In addition, the gate terminal of nmos pass transistor 62B is connected to PMOS series connection portion 60 and is connected with the contact (drain terminal of PMOS transistor 60C and the contact of the drain terminal of nmos pass transistor 62A) 64 in NMOS series connection portion 62.In addition, this tie point 64 is connected to the input terminal of logical circuit 118 via the wiring 65 being applied in potential difference.
Different bit line amplifier 32 has PMOS transistor 66.The source terminal of PMOS transistor 66 is connected with the input terminal of logical circuit 118, and the drain terminal of PMOS transistor 66 is grounded.In addition, gate terminal and the clock signal of PMOS transistor 66 produce circuit 30 and are connected, and produce signal TAMPB during circuit 30 inputs reversion action from clock signal.
Coupling counters circuit 34 be offset utilize charging circuit 114 to start when charging series circuit 58 in PMOS transistor 60C and the electric charge that produces of the capacitive coupling of nmos pass transistor 62A, 62C (hereinafter referred to as " coupling electric charge ".) circuit.
The structure of coupling counters circuit 34 comprises: nmos pass transistor 68 and circuit for reversing 70.The gate terminal of nmos pass transistor 68 is connected with each gate terminal of PMOS transistor 60C and nmos pass transistor 62A, 62C.Circuit for reversing 70 has the 1st power supply terminal 70A, the 2nd power supply terminal 70B, input terminal 70C and lead-out terminal 70D.1st power supply terminal is connected with the contact 46C of constantvoltage generation circuit 112, is applied in constant voltage VREFEQ.In addition, the 2nd power supply terminal is grounded.In addition, input terminal 70C and clock signal produce circuit 30 and are connected, signal TAMP during producing circuit 30 input action from clock signal.Further, the source terminal of lead-out terminal 70D and nmos pass transistor 68 and drain terminal are connected.Wherein, nmos pass transistor 68 is configured to: when starting to charge by charging circuit 114, makes gate terminal to produce the electric charge with the opposite polarity of the coupling electric charge equivalent produced on each gate terminal of PMOS transistor 60C and nmos pass transistor 62A, 62C.
Next, with reference to Fig. 4, the effect of the nonvolatile memory 10 of this first embodiment is described.Wherein, the sequential chart of the conversion of the signal level the amplifier 15 when reading data from storage unit 102 has been shown in Fig. 4.In addition, here, in order to avoid intricate, the situation reading data from the storage unit 102 be connected with wordline WLy, drain line DLx and bit line BLx is described.Further, here, in order to avoid intricate, be set to bit line BLx during beyond during the action of amplifier 15 and charged with builtin voltage VCD.
As shown in the drawing, when when inputting new address date from outside, address is updated, amplifier 15 starts the access of the storage unit 102 of the address after to renewal.Wherein, " TAC " of this figure represents to storage unit 102 during the visit.
If start the access to storage unit 102, then apply to make the voltage VCW be read being stored in the data in storage unit 102 to the wordline WLy of storage unit 102, and builtin voltage VCD is applied to the drain line DLx of storage unit 102.
In addition, if start the access to storage unit 102, then during can latching between signal TLAT, interdischarge interval signal TDIS and charge period signal TAMPC synchronously from low transition be high level.When interdischarge interval signal TDIS is high level from low transition, between the source terminal of nmos pass transistor 56 and drain terminal, be transformed into conducting state from nonconducting state.Thus, during interdischarge interval signal TDIS is high level (such as, 5ns), the builtin voltage VCD being applied to bit line BLx is discharged, and the size of the voltage of bit line BLx is reduced to voltage VSS (such as, ground voltage level).On the other hand, if signal TLAT is high level from low transition during can latching, then become can latch mode for latch cicuit 106.In addition, if signal TAMPC is high level from low transition between charge period, then during high level (such as 30ns), constant voltage VREFEQ be applied to bit line BLx and connect up 65 be charged to constant voltage VREFEQ (from potential difference output circuit 116B export potential difference VOUT xrise to constant voltage VREFEQ).
In addition, if interdischarge interval signal TDIS is converted to low level from high level, then during action, signal TAMP is high level from low transition, and thereupon corresponding with the data of storage unit 102 in bit line BLx electric current starts to flow.Flow in during this electric current signal TAMP during action is high level.Further, if latch ready signal TLAT to be converted to low level from high level, then during action, signal TAMP is converted to low level from high level, thereupon at bit line BL xin become no current flows.
If signal TAMPC is converted to low level from high level between charge period, then end of charging, potential difference output circuit 116B generates the electric current I CELL corresponding to current time and flow in bit line BL xsize and the potential difference of difference of size of reference current IREF, and to export to the wiring 65 being charged to constant voltage VREFEQ.Here, if electric current I CELL xsize be greater than the size of reference current IREF, then potential difference VOUT xsize be greater than the size of reference voltage VREF, if electric current I CELL xsize be less than the size of reference current IREF, then potential difference VOUT xsize be less than the size of reference voltage VREF.
The potential difference logic value that logical circuit 118 will supply from potential difference output circuit 116B, and the logical value SOUT will obtained by logic value xexport to latch cicuit 106.Latch cicuit 106 keeps the logical value SOUT inputted from logical circuit 118 x, and when during can latching, signal TLAT is converted to low level from high level, by logical value SOUT xas logical value SOUTLAT xexport to output circuit 107.Output circuit 107 will correspond to the logical value SOUTLAT inputted from latch cicuit 106 xthe signal of (" 1 " or " 0 ") exports to the outside of nonvolatile memory 10.
So, according to the nonvolatile memory 10 of this first embodiment, before potential difference is carried out logic value, the voltage of wiring 65 is not become carry out logic value here with the voltage of the sizable size of reference voltage VREF (being constant voltage VREFEQ) situation compared with, because the voltage that can shorten wordline WLy reaches the digital independent period TREAD that voltage VCW starts to logic value terminates, so can shorten TAC during the visit.
In addition, if the A point shown in Fig. 4 utilizes charging circuit 114 to start charging, then in potential difference output circuit 116B, produce the PMOS transistor 60C of series circuit 58 and the capacitive coupling caused by the grid capacitance of nmos pass transistor 62A, 62C, thus, the reference voltage VREF as the grid voltage of MOS transistor 60C and nmos pass transistor 62A, 62C rises.
Therefore, in the nonvolatile memory 10 of this first embodiment, coupling counters circuit 34 is utilized to fall coupling electric charge that cause because of capacitive coupling, that produce at the gate terminal of PMOS transistor 60C and nmos pass transistor 62A, 62C with the charge cancellation of opposite polarity.
In other words, the circuit for reversing 70 of coupling counters circuit 34 is when during action, signal TAMP is low level (when not reading the data being stored in storage unit 102), and the source terminal of pair nmos transistor 68 and drain terminal apply constant voltage VREFEQ.And, if signal TAMP is high level from low transition during action, then during action signal TAMP during high level in (reading be stored in the data in storage unit 102 during), the source terminal of pair nmos transistor 68 and drain terminal apply the voltage of earth level, to make to produce the electric charge of the opposite polarity of the coupling electric charge equivalent produced on the gate terminal of PMOS transistor 60C and nmos pass transistor 62A, 62C with current time on the gate terminal of nmos pass transistor 68.By the electric charge of this opposite polarity, the coupling electric charge of PMOS transistor 60C and nmos pass transistor 62A, 62C is cancelled.In other words, that produce when the charging of charging circuit 114 starts, in PMOS transistor 60C and nmos pass transistor 62A, 62C capacitive coupling, is cancelled by the capacitive coupling in the nmos pass transistor 68 of coupling counters circuit 34.Therefore, it is possible to make the grid voltage of PMOS transistor 60C and nmos pass transistor 62A, 62C become reference voltage VREF in the moment that charging terminates.
As the detailed description carried out above, in the nonvolatile memory 10 of this first embodiment, to be connected with storage unit 102 and be applied in the size of the voltage of the bit line BL of the voltage of the size corresponding to the data be stored in storage unit 102, compare with the size of the reference voltage VREF of reference voltage line 40, and then utilize logical circuit 118 to identify by the data representation of storage unit 102 logical value time, in order to shortening the comparing of the size of the reference voltage VREF from the voltage swing with reference voltage line 40 carrying out bit line BL until determine the time that comparative result is required, before the comparing of size of the reference voltage VREF of the voltage swing with reference voltage line 40 that carry out bit line BL, charged with constant voltage VREFEQ pairs of bit line BL by charging circuit 114, then the potential difference corresponding to difference of the size of the size of series circuit 58 generating reference voltage VREF and the voltage of bit line BL is utilized by potential difference output circuit 116B, and be absorbed in PMOS transistor 60C and nmos pass transistor 62A by coupling counters circuit 34, the coupling electric charge produced in 62C, in order to suppress the PMOS transistor 60C of series circuit 58 and nmos pass transistor 62A along with the beginning of charging, the rising of the grid voltage of 62C, therefore, it is possible to suppress the generation of access delay.
In addition, in the nonvolatile memory 10 of this first embodiment, the electric charge with the opposite polarity of the coupling electric charge equivalent produced in PMOS transistor 60C and nmos pass transistor 62A, 62C is generated by coupling counters circuit 34, and use the electric charge generated to absorb this coupling electric charge, therefore, it is possible to easily suppress the rising of the grid voltage of PMOS transistor 60C and nmos pass transistor 62A, 62C.
In addition, in the nonvolatile memory 10 of this first embodiment, owing to coupling counters circuit 34 being configured to comprise nmos pass transistor 68 and circuit for reversing 70, therefore to be formed the rising of the grid voltage that just can suppress PMOS transistor 60C and nmos pass transistor 62A, 62C easily.
And, in the nonvolatile memory 10 of this first embodiment, due to by series circuit 58 in series for multiple field effect transistor, so easily can infer and capacity coupled generation position and coupling electric charge amount, its result, can alleviate the labour that the design because of coupling counters circuit 34 spends.
(the second embodiment)
The nonvolatile memory of this second embodiment is compared with the nonvolatile memory 10 of above-mentioned first embodiment, different on the point employing amplifier 80 replacing amplifier 15.Therefore, here, also the description thereof will be omitted to give identical Reference numeral to the structure identical with the nonvolatile memory 10 of above-mentioned first embodiment, and be described for the difference of the nonvolatile memory 10 with above-mentioned first embodiment.
An example of the formation of the amplifier 80 of this second embodiment has been shown in Fig. 5.As shown in the drawing, amplifier 80 is compared with the amplifier 15 shown in Fig. 3, different on the point employing different bit line amplifier 82 replacing different bit line amplifier 32.Different bit line amplifier 82 is compared with the different bit line amplifier 32 shown in Fig. 3, and structure bit line BL being connected to the source terminal of the nmos pass transistor 48 in charging circuit 114 replaces with the structure part of the contact 55 bit line BL being connected to the drain terminal of the PMOS transistor 54 in initialization executive circuit 116A and the drain terminal of nmos pass transistor 56 and newly to devise separation circuit 84 part different.
Separation circuit 84 is electrically separated circuit potential difference output circuit 116B, charging circuit 114 and constantvoltage generation circuit 112 being carried out specified time limit in the moment specified and initialization executive circuit 116A.Separation circuit 84 has nmos pass transistor 84A.Nmos pass transistor 84A is inserted between charge point 86 and contact 55, this charge point 86 be in bit line BL with the contact of charging circuit 48.In other words, the source terminal of nmos pass transistor 84A is connected on tie point 55 via bit line BL, and the drain terminal of nmos pass transistor 84A is connected with charge point 86 via bit line BL.In addition, the contact of the drain terminal of nmos pass transistor 62A and the drain terminal of nmos pass transistor 62B is connected in charge point 86 via bit line BL.Further, gate terminal and the clock signal of nmos pass transistor 84A produce circuit 30 and are connected, and are transfused to the signal TBLON will represented with high level during making to become conducting state between source terminal and drain terminal.
In the amplifier 80 formed as described above, as an example, as shown in Figure 6, when during action, signal TAMP is low level (when not carrying out the reading of the data of storage unit 102), by similarly signal TBLON being set to low level, make to become nonconducting state between the source terminal of nmos pass transistor 84A and drain terminal, disconnect the current path between charge point 86 and tie point 55, and when during action, signal TAMP is high level (when carrying out the reading of the data of storage unit 102), by similarly signal TBLON being set to high level, make to become conducting state between the source terminal of nmos pass transistor 84A and drain terminal, carry out the current path between conducting charge point 86 and tie point 55.
Like this, between charge period signal TAMPC high period between initial stage, during being undertaken discharging by bit line BL (during the C shown in this figure), because the current path between charge point 86 and tie point 55 is disconnected, so the generation of situation about externally flowing out via nmos pass transistor 56 at the electric current exported from constantvoltage generation circuit 112 during this period can be avoided, and the discharge time till making the size of the voltage of bit line BL be reduced to prescribed level can be shortened.
In addition, after the electric discharge of bit line BL terminates, in the same manner as the amplifier 15 of above-mentioned first embodiment, the electric current flowed in bit line BL can be supplied to potential difference output circuit 116B.Further, even at the interdischarge interval of bit line BL, electric current also externally cannot flow out via nmos pass transistor 56, and therefore shorten the duration of charging of this time degree, with this, TAC also shortens during the visit.
In addition, when not using amplifier 80 of this second embodiment, be necessary to use a kind of constantvoltage generation circuit 112 with the voltage supply capacity of amount that the electric current that can bear charging externally flows out, but in the amplifier 80 of this second embodiment, because the outflow of electric current during charging is prevented from, so the voltage supply capacity that charging electricity consumption flows to the constantvoltage generation circuit 112 of the range degree that outside outflow is prevented from can be reduced.
Wherein, in the respective embodiments described above, as the inscape of coupling counters circuit 34, employ nmos pass transistor 68, but be not limited thereto, such as, can also use PMOS transistor.In addition, the capacity cell such as electricity container, di-cap can also be made.So, as long as generate the capacity cell that can absorb the coupling electric charge of the opposite polarity of the coupling electric charge produced by series circuit 58, no matter then its pattern is all applicable.In addition, can also by series circuit that these capacity cells are connected, by the parallel circuit of these capacity cell parallel connections or the coupling electric charge circuit etc. of these electrical combination being generated opposite polarity, in order to absorb the coupling electric charge generated in series circuit 58.
In addition, in the respective embodiments described above, as the capacitive load generating coupling electric charge, be illustrated for the embodiment of the situation that make use of the series circuit 58 that multiple field effect transistor is in series, but be not limited thereto, can also use: the bleeder circuit being combined with the capacitive load of the capacity cell such as capacitor, di-cap etc. on series circuit 58, or in order to generate the bleeder circuit etc. that the capacity cell beyond field effect transistor carries out combining and forms by potential difference VOUT.So, as long as function can be played as the capacity coupled capacitive load of generation, and the voltage of the difference corresponding to the size of electric current I CELL and the size of reference current IREF can be generated, and by the circuit that it supplies to logical circuit 118, no matter any circuit.
In addition, in the above-described 2nd embodiment, situation separation circuit 84 to nmos pass transistor 84 is illustrated, but can also replace nmos pass transistor 84 and use PMOS transistor.In addition, separation circuit 84 can also be replaced and use the circuit by transistor series or parallel connection.Whichsoever, all need as illustrated in above-mentioned second embodiment, the current path between charge point 86 and tie point 55 to be carried out between conducting state and nonconducting state the mode switched, to each gate terminal input signal of transistor.

Claims (6)

1. a Nonvolatile memory devices, it comprises:
Bit line, with can electronically written ground logical value storage non-volatile memory element be connected, be applied in the voltage that size is corresponding with the logical value be stored in this memory element;
Charging circuit, the size of carrying out the voltage putting on described bit line with put on reference voltage line reference voltage size compare identify described logical value time, this relatively before, described charging circuit utilizes the sizable voltage of size and described reference voltage to charge to this bit line;
Potential difference output circuit, be connected between described reference voltage line and described bit line, and there is the capacitive load producing coupling electric charge when charging with described charging circuit, the voltage corresponding to difference utilizing this capacitive load to generate the size of the size of the voltage of described reference voltage line and the voltage of described bit line is used as the voltage representing described comparative result; And
Coupling counters circuit, possesses the first field effect transistor of the gate terminal with the tie point being connected to described reference voltage line and described capacitive load, when having carried out charging by described charging circuit, be shared voltage by the voltage of the voltage of the gate terminal by this first field effect transistor and the gate terminal of described capacitive load, thus absorb the electric charge of above-mentioned reference voltage line.
2. Nonvolatile memory devices according to claim 1, wherein, described coupling counters circuit generates the electric charge with the opposite polarity of described coupling electric charge equivalent at the gate terminal of described first field effect transistor, and utilizes the electric charge generated to absorb the electric charge of described reference voltage line.
3. Nonvolatile memory devices according to claim 1 and 2, wherein, the structure of described coupling counters circuit comprises:
Circuit for reversing, the reading carrying out described logical value from described memory element until in the read terminated, described circuit for reversing applies ground voltage to the source terminal of described first field effect transistor and drain terminal, and beyond this read during in, described circuit for reversing applies the sizable voltage of size and described reference voltage to described source terminal and described drain terminal.
4. Nonvolatile memory devices according to claim 1, wherein, described capacitive load is the series circuit that multiple field effect transistor is in series.
5. Nonvolatile memory devices according to claim 1, also comprises:
Initialization executive circuit, be inserted in described bit line as between the charge point of the contact of described charging circuit and described memory element, and carry out following action, the initial stage namely between the charge period of charging to this bit line with this charging circuit makes this bit line discharges; With
Separation circuit, be inserted between described charge point in described bit line and described initialization executive circuit, and to make the current path between this charge point and this initialization executive circuit become nonconducting state at the described initial stage, and beyond described initial stage between described charge period during in make this current path become conducting state mode switch described nonconducting state and described conducting state.
6. Nonvolatile memory devices according to claim 5, wherein, described separation circuit has the second field effect transistor, by switching to conducting state and nonconducting state between the source terminal of this second field effect transistor and drain terminal and switching conducting state and the nonconducting state of described current path.
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