CN102637458A - Memory circuits having a plurality of keepers - Google Patents
Memory circuits having a plurality of keepers Download PDFInfo
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- CN102637458A CN102637458A CN2011103262394A CN201110326239A CN102637458A CN 102637458 A CN102637458 A CN 102637458A CN 2011103262394 A CN2011103262394 A CN 2011103262394A CN 201110326239 A CN201110326239 A CN 201110326239A CN 102637458 A CN102637458 A CN 102637458A
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Abstract
A memory circuit includes a first plurality of memory arrays disposed in a column fashion; a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays; a first current limiter which is electrically coupled with and shared by the first plurality of keepers; and a first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers.
Description
The cross reference of related application
The application is the part of the 12/778th, No. 714 U.S. Patent application that is entitled as " MEMORY CIRCUITS HAVINGA PLURALITY OF KEEPERS " that proposed on May 12nd, 2010 application case that continues, and its full content is incorporated herein by reference.
Technical field
The present invention relates generally to the semiconductor circuit field, more specifically, relates to the memory circuit that has a plurality of retainers.
Background technology
Memory circuit is used for various uses.Usually, memory circuit can comprise dynamic RAM (DRAM) circuit, static RAM (SRAM) circuit, Nonvolatile memory circuit.The SRAM circuit comprises a plurality of storage unit.For traditional 6-T SRAM circuit that wherein is formed with memory cell array, each storage unit all has six transistors.6-T SRAM storage unit is connected with bit line BL, bit line bar BLB and word line WL.Four in six transistors have formed two cross-linked phase inverters, are used for perhaps data of " 1 " of storage representative " 0 ".Two remaining transistors are controlled the visit that is stored in the data in the storage unit as access transistor.
Summary of the invention
For addressing the above problem, the invention provides a kind of memory circuit, comprising: a plurality of first storage arrays, arrange with the mode of row; A plurality of first retainers, each first retainer all with a plurality of first storage arrays in corresponding one be electrically connected; First restrictor is electrically connected with a plurality of first retainers, and a plurality of first retainer is shared first restrictor; And a plurality of first sector switches, each first sector switch all is electrically connected in first restrictor and a plurality of first retainer between corresponding one.
Wherein, each in a plurality of first storage arrays all comprises: at least one storage unit, and at least one storage unit comprises read port, read port is configured to; During sensing, if the read port conducting, then first electric current can flow through read port; And at the read port two ends voltage drop is arranged, first restrictor configuration does, during sensing; Second electric current of first restrictor is flow through in control, and during sensing, first electric current is greater than second electric current.
Wherein, at least one during sensing and between precharge phase, visit in a plurality of first storage arrays, and conducting is corresponding to the sector switch of the storage array of being visited.
Wherein, first restrictor comprises: the first transistor, and each in a plurality of first sector switches all comprises core transistor, the channel length of the first transistor is greater than the channel length of core transistor.
Wherein, each in a plurality of first retainers all comprises: at least one transistor seconds; And logic gate, wherein, the output terminal of logic gate and the grid of at least one transistor seconds are electrically connected, and at least one input end of logic gate and at least one drain electrode of at least one transistor seconds are electrically connected.
Wherein, logic gate is the NOT door, and at least one transistor seconds comprises single transistor.
Wherein, logic gate is the NAND door, and at least one transistor seconds comprises two or multiple transistor more.
This memory circuit further comprises: a plurality of second storage arrays, arrange with the mode of row; A plurality of second retainers, each second retainer all with a plurality of second storage arrays in corresponding one be electrically connected; A plurality of second sector switches, each second sector switch all are electrically connected in first restrictor and a plurality of second retainer between corresponding one; The first row switch is connected electrically between first restrictor and a plurality of first sector switch; And the secondary series switch, be connected electrically between first restrictor and a plurality of second sector switch.
Wherein, first restrictor comprises the first transistor, and the first row switch comprises transistor seconds, and the channel length of transistor seconds is less than the channel length of the first transistor.
In addition, a kind of memory circuit is provided also, has comprised: first restrictor, wherein, first restrictor comprises the first transistor; A plurality of first storage arrays are arranged with the mode of row; A plurality of first retainers; Each first retainer all with a plurality of first storage arrays in corresponding one be electrically connected; A plurality of first retainers and first restrictor are electrically connected, and wherein, each in a plurality of first retainers all comprises: at least one transistor seconds; And logic gate, wherein, the output terminal of logic gate and the grid of at least one transistor seconds are electrically connected, and at least one input end of logic gate and at least one drain electrode of at least one transistor seconds are electrically connected; And a plurality of first sector switches, be connected electrically in first restrictor and a plurality of first retainer between corresponding one.
Wherein, each in a plurality of first storage arrays all comprises: at least one storage unit, and at least one storage unit comprises read port, read port is configured to; During sensing, if the read port conducting, then first electric current can flow through read port; And at the read port two ends voltage drop is arranged, first restrictor configuration does, during sensing; Second electric current of first restrictor is flow through in control, and during sensing, first electric current is greater than second electric current.
Wherein, at least one during sensing and between precharge phase, visit in a plurality of first storage arrays, and conducting is corresponding to the sector switch of the storage array of being visited.
Wherein, first sector switch comprises core transistor, and the channel length of the first transistor is greater than the channel length of core transistor.
This memory circuit further comprises: a plurality of second storage arrays, arrange with the mode of row; A plurality of second retainers, each second retainer all with a plurality of second storage arrays in corresponding one be electrically connected; A plurality of second sector switches, each second sector switch all are connected electrically in first restrictor and a plurality of second retainer between corresponding one; The first row switch is connected electrically between first restrictor and a plurality of first sector switch; And the secondary series switch, be connected electrically between first restrictor and a plurality of second sector switch.
Wherein, the first row switch comprises the 3rd transistor, and the 3rd transistorized channel length is greater than the channel length of the first transistor.
In addition, also offered a kind of memory circuit, having comprised: first restrictor, be configured to, during sensing, first electric current of first restrictor is flow through in control, and wherein, first restrictor comprises the first transistor; A plurality of first storage arrays are arranged with the mode of row, wherein; In a plurality of first storage arrays each all comprises at least one storage unit, and at least one storage unit comprises read port, and read port is configured to; During sensing; If the read port conducting, then first electric current can flow through read port, and at the read port two ends voltage drop is arranged; A plurality of first retainers; Each first retainer all with a plurality of first storage arrays in corresponding one be electrically connected; Wherein, In a plurality of first retainers each all comprises: at least one transistor seconds, and wherein, at least one source terminal and first restrictor of at least one transistor seconds are electrically connected; And logic gate, wherein, the output terminal of logic gate and the grid of at least one transistor seconds are electrically connected, and at least one input end of logic gate and at least one drain electrode of at least one transistor seconds are electrically connected; And a plurality of first sector switches, be connected electrically in first restrictor and a plurality of first retainer between corresponding one.
Wherein, at least one during sensing and between precharge phase, visit in a plurality of first memory circuits, and conducting is corresponding to the sector switch of the storage array of being visited.
Wherein, first sector switch comprises core transistor, and the channel length of the first transistor is greater than the channel length of core transistor.
Wherein, logic gate is the NOT door, and at least one transistor seconds comprises single transistor.
Wherein, logic gate is the NAND door, and at least one transistor seconds comprises two or multiple transistor more.
Description of drawings
Detailed description according to below in conjunction with accompanying drawing can be understood the present invention best.It is emphasized that according to the standard practices in the industry various different parts are not drawn in proportion, and just are used for illustrated purpose.In fact, in order to make argumentation clear, can increase or reduce the quantity and the size of various parts arbitrarily.
Fig. 1 shows the synoptic diagram of the exemplary memory circuit that comprises the restrictor that is connected with a plurality of retainers.
Fig. 2 shows the synoptic diagram of another exemplary memory circuit that comprises the restrictor that is connected with a plurality of first example retainer.
Fig. 3 shows the synoptic diagram of another exemplary memory circuit that comprises the restrictor that is connected with a plurality of second example retainer.
Fig. 4 shows the synoptic diagram of the exemplary memory circuit that comprises the restrictor that is connected with a plurality of the 3rd example retainer.
Fig. 5 shows the synoptic diagram of the exemplary memory circuit that comprises the restrictor that is connected with a plurality of the 4th example retainer.
Fig. 6 shows the synoptic diagram of another memory circuit that has the restrictor of being shared by two row retainers.
Fig. 7 shows the synoptic diagram of another memory circuit that has two restrictors being shared by the retainer of respective column.
Fig. 8 shows the synoptic diagram of the system that comprises the exemplary memory circuit.
Fig. 9 shows the synoptic diagram of the exemplary memory circuit that comprises a plurality of sector switches, and wherein, each sector switch all is electrically connected between restrictor and the corresponding retainer.
Figure 10 shows the synoptic diagram of another exemplary memory circuit that comprises a plurality of sector switches, and wherein, each sector switch all is connected electrically between restrictor and the corresponding retainer.
Figure 11 shows the synoptic diagram of the exemplary memory circuit that comprises a plurality of row switches, and wherein, each row switch all is connected electrically between the memory array of restrictor and respective column.
Figure 12 shows the synoptic diagram of another exemplary memory circuit that comprises a plurality of row switches, and wherein, each row switch all is connected electrically between the memory array of restrictor and respective column.
Embodiment
Usually, the SRAM circuit has a plurality of storage arrays and a plurality of retainer.Storage array and retainer place the single row of SRAM circuit successively.Each retainer all has long channel transistor, and this long channel transistor is electrically connected with phase inverter.The channel length of long channel transistor is basically greater than the channel length of core transistor.Because each retainer all has long channel transistor, therefore, the SRAM circuit need provide the long channel transistor that is used for holding retainer than large tracts of land.
Should be appreciated that the following discloses content provides many different embodiment or instances that are used to implement disclosed different characteristic.The instantiation of below describing assembly and configuration is to simplify the present invention.Certainly, this only is an instance, is not intended to limit the invention.In addition, content of the present disclosure can be in different instances repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, and do not represent in itself that each embodiment and/or institute discuss the relation between disposing.In addition; Being formed on parts on another parts, being connected with another parts and/or being coupled in following the present invention can comprise that parts are formed the embodiment of direct contact; Can also comprise other parts form and place between the parts (such as, parts are directly contact) embodiment.In addition; The term of relative space position; For example " below ", " top ", " level ", " vertically ", " ... on ", " ... under ", " making progress ", " downwards ", " top ", " bottom " etc. and derivative (for example, " flatly ", " downwards ", " up " etc.) thereof be used for making the parts of content of the present invention and the relation of another parts to become simple and clear.The term of relative space position has covered the different orientations of the device that comprises parts.
Fig. 1 shows the synoptic diagram of the exemplary memory circuit that comprises the restrictor that is connected with a plurality of retainers.In Fig. 1, memory circuit 100 can comprise a plurality of storage arrays (for example, storage array 101a-101d) and a plurality of retainer (for example, retainer 103a-103d).In certain embodiments; Integrated circuit 100 can be static RAM (SRAM) circuit (for example; Single port induction SRAM circuit or multi-port SRAM circuit), the memory circuit of embedded SRAM circuit (for example, single port induction embedded SRAM circuit or multiport embedded SRAM circuit) or other types.Notice that the quantity of storage array shown in Fig. 1 and retainer only is exemplary.In certain embodiments, can increase more array and/or retainer.
In certain embodiments, each among the retainer 103a-103d all is electrically connected with corresponding storage array 101a-101d respectively.Memory circuit 100 can comprise at least one restrictor, for example, and restrictor 110a.Restrictor 110a can be electrically connected with retainer 103a-103d, and this retainer 103a-103d can share this restrictor 110a.In certain embodiments, restrictor 110a can be connected electrically in provides for example V
DDSupply voltage power lead with for example V is provided
SSPerhaps between another power lead of the supply voltage of ground connection (not shown).
In certain embodiments, during the sensing of the data of in the storage unit (not shown) of one of induction storage array 101a-101d, being stored, restrictor 110a can be configured to control and/or limit the electric current that flows through restrictor 110a.During sensing, if the read port conducting of storage unit has voltage drop between the read port, then another electric current can flow through the read port of storage unit, thus the electric current among antagonism (fight) restrictor 110a.Because the electric current antagonism can be responded to the data of storing in the storage unit, and/or the data of storing in the output storage unit are further to respond to.Can find that retainer 103a-103d can share restrictor 110a, thereby move the sensed data of storing among the storage array 101a-101d respectively.Owing to the transistor that retainer 103a-103d has small channel, therefore reduced the area of retainer 103a-103d.Also reduced to be used to hold the area of the integrated circuit 100 of retainer 103a-103d.
Fig. 2 shows the synoptic diagram of the exemplary memory circuit that comprises the restrictor that is connected with a plurality of first example retainer.In Fig. 2, each among the storage array 101a-101b can comprise at least one storage unit respectively, for example, and storage unit 105a-105b.For the embodiment that uses 8-T SRAM storage unit, each among the storage array 101a-101b can comprise many word line WL1 and WL2 and multiple bit lines BL and BLB.Among the storage unit 105a-105b each can be with bit line BL, bit line bar BLB, word line WL1 and WL2, be used to provide for example V
DDSupply voltage first power lead and be used to provide for example V
SSPerhaps the second source line of the supply voltage of ground connection is electrically connected.Note,, can also other storage unit (not shown) be connected with BLB with WL2 and multiple bit lines BL with many word line WL1 of storage array 101a although in storage array 101a, only show a storage unit 105a.In certain embodiments, each among the storage array 101a-101b can have that can be arranged as word width be 8,16,32,64,128 or multiple row more.In other embodiments, word line WL1 and/or WL2 can layout for being basically perpendicular to bit line BL and BLB.Other arrangements of word line WL1 and WL2 and bit line BL and BLB can be provided in other embodiments.
With reference to figure 2, storage unit 105a can comprise that two intersections of the trigger of the data that are formed for storing storage units 105a latch phase inverter (not marking).Transistor m
1And m
2Grid can be electrically connected with word line WL 1.Transistor m
1And m
2Can be used as two transmission (pass) transistor, access transistor, or transmit the grid operation.Storage unit 105a can also comprise read port (not marking).In certain embodiments, read port can comprise transistor m
3And m
4Transistor m
3Grid can be electrically connected with word line WL2.Transistor m
3Source/drain (S/D) end can be electrically connected with retainer 103a.Transistor m
4Grid can with intersect the node N1 that latchs phase inverter and be electrically connected.Transistor m
3And m
4Can be used as two transmission transistors, access transistor, or transmit the grid operation.In the embodiment shown in Fig. 2, transistor m
3And m
4It is N type metal oxide semiconductor (NMOS) transistor.
With reference to figure 2, each among the retainer 103a-103b can comprise at least one transistor (for example, transistor 121a-121b), is electrically connected with logic gate (for example, NOT door 120a-120b) respectively.In certain embodiments, each among the NOT door 120a-120b can be called phase inverter.In this embodiment, each among the transistor 121a-121b can be P-type mos (PMOS) transistor.In certain embodiments, the input end N of NOT door 120a
2Can with drain electrode end and the transistor m of transistor 121a
3S/D end be electrically connected.The output terminal N of NOT door 120a
3Can be electrically connected with the grid of transistor 121a.In certain embodiments, each among transistor 121a and the 121b can be core transistor.The transistor according to the process node formation that forms memory circuit 100 can be represented in term " core transistor ".For example, if process node is 40-nm (nanometer) technology, then the channel length of core transistor can be about 40nm.Notice that above-mentioned process node only is exemplary.In other embodiments, process node can be bigger or littler than 40-nm technology.In other embodiments, the channel length of the transistor 121a intersection that can be substantially equal to storage unit 105a latchs the channel length of the transistor (not shown) of phase inverter.
Refer again to Fig. 2, restrictor 110a can comprise at least one transistor, for example, and transistor 107.In certain embodiments, transistor 107 can be the PMOS transistor.The source terminal of transistor 107 can with for example V is provided
DDThe power lead of supply voltage be electrically connected.The drain electrode end of transistor 107 can be electrically connected with retainer 103a and 103b.The grid of transistor 107 can with for example V is provided
SSPerhaps the power lead of the supply voltage of ground connection is electrically connected.Between precharge phase and/or during the sensing, supply voltage V
SSPerhaps ground connection can be with transistor 107 conductings.In certain embodiments, the channel length of transistor 107 is greater than the channel length of transistor 121a.In other embodiments, transistor 107 can be called long channel transistor.
As said, retainer 103a can comprise transistor 121a (for example, core transistor), and the raceway groove of the ditch channel ratio transistor 107 of this transistor 121a is little, and can be used as the operation of transmission grid.The area of retainer 103a can be less than the area of the traditional retainer that uses long channel device.Be also noted that retainer 103a-103b can share this restrictor 110a.The total area of memory circuit 100 can be less than the SRAM circuit that uses traditional retainer.
Following description is relevant for the input end N with NOT door 120a
2Precharge illustrative methods.Between precharge phase, with the input end N of NOT grid 120a
2At least one the precharge transistor (not shown) that is connected can conducting.The precharge transistor of conducting can be with the input end N of NOT door 120a
2Be electrically connected to power lead, thereby with the input end N of NOT door 120a
2Be pre-charged to supply voltage, for example, V
DDBetween precharge phase, transistor m
3Turn-off.The transistor m that turn-offs
3 Can storage unit 105a and retainer 103a electricity be isolated.
As said, the input end N of NOT door 120a
2Can be pre-charged to supply voltage V
DDIn case the input end N of NOT door 120a
2On voltage increase to predetermined voltage level or supply voltage V
DD, then NOT door 120a can be with the input end N of NOT door 120a
2On voltage status (for example, high-voltage state) be turned to the input end N of NOT door 120a
3Go up another voltage status (for example, low-voltage state).Low-voltage state (for example, has supply voltage V
SSPerhaps ground connection) can be with transistor 121a conducting.
As said, between precharge phase, transistor 107 conductings.The transistor 107 of conducting can be with supply voltage V
DDBe electrically connected to the source terminal of transistor 121a.The transistor 121a of conducting can be with the supply voltage V of the source terminal of transistor 121a
DDBe electrically connected to the input end N of NOT door 120a
2Therefore, the input end N of NOT door 120a
2On voltage level can remain on supply voltage V
DDMore than combine the described precharge operation of storage unit 105a can also be applied to storage unit 105b.
Below describedly relate to induction and be stored in the illustrative methods of the data among the storage unit 105a.In certain embodiments, before during the sensing, the precharge transistor (not shown) can turn-off.Since will the data of access stored in storage unit 105a, therefore, the word line WL1 ' of storage unit 105b and/or WL2 ' be charging not.
During sensing, the word line WL2 of storage unit 105a can charge, thereby with transistor m
3Conducting.In certain embodiments, intersection latchs the node N of phase inverter
1For example can storing, the logic state of logical one perhaps has the for example voltage status of high-voltage state.Node N
1On voltage status can be with transistor m
4Conducting.The transistor m of conducting
3And m
4Can be with the input end N of NOT door 120a
2Be electrically connected to supply voltage, for example, V
SSPerhaps ground connection.In certain embodiments, transistor m
3And m
4Activation can be called the activation of the read port of storage unit 105a.As said, between precharge phase after, the input end N of NOT door 120a
2On voltage level can remain on supply voltage V at first
DDBecause transistor m
3And m
4The voltage drop at two ends during sensing, can have electric current to flow through transistor m
3And m
4
As said, restrictor 110a is configured to control and/or limit the electric current that flows through restrictor 110a.For example, during sensing, transistor 107 conductings.During sensing, can there be electric current to flow through transistor 107.Can find, during sensing, flow through transistor m
3And m
4Electric current can be greater than the electric current that flows through transistor 107.Since the electric current antagonism, the input end N of NOT door 120a
2On voltage level can be pulled down to supply voltage V
SSPerhaps ground connection.In case the input end N of NOT door 120a
2On voltage be lower than predetermined voltage level or reach supply voltage V
SS, NOT door 120a can be with the input end N of NOT door 120a
2On voltage status (for example, low-voltage state) be turned to the input end N of NOT door 120a
3On another voltage status (for example, high-voltage state).High-voltage state (for example, has supply voltage V
DD) can transistor 121a be turn-offed.The transistor 121a that turn-offs can be with the supply voltage V on the drain electrode end of transistor 107
DDInput end N with NOT door 120a
2Electricity is isolated.Therefore, the input end N of NOT door 120a
2On voltage status can remain on supply voltage V
SSTherefore, the data that are stored among the storage unit 105a can be responded to, and/or output is further to respond to.
Fig. 3 shows the synoptic diagram of another exemplary memory circuit that comprises the restrictor that is connected with a plurality of second example retainer.In Fig. 3, each among the retainer 103a-103b can comprise at least one transistor (for example, transistor 131a, 133a and 131b, 133b), is electrically connected with logic gate (for example, NAND door 130a-130b) respectively.In certain embodiments, each among transistor 131a-131b and the transistor 133a-133b can be the PMOS transistor.The input end A of NAND door 130a can with drain electrode end and the transistor m of transistor 133a
3S/D end be electrically connected.Another input end B of NAND door 130a can be electrically connected with another storage unit (not shown) with the drain electrode end of transistor 131a.The output terminal of NAND door 130a can be electrically connected with the grid of transistor 131a and 133a.The source terminal of transistor 131a and 133a can be electrically connected with restrictor 110a.In certain embodiments, each among transistor 131a and the 133a can be core transistor.In other embodiments, the channel length of transistor 107 is respectively greater than the channel length of transistor 131a and 133a.
The precharge of storage unit 105a and inductive operation can be similar to the description that above combination Fig. 2 is done.Purposes according to logic gate is different, and the method for operation of NAND door 130a and transistor 131a and 133a also can be different.In addition, the input end A of NAND door 130a is electrically connected with different storage unit with B.
Fig. 4 shows the synoptic diagram of the exemplary memory circuit that comprises the restrictor that is connected with a plurality of the 3rd example retainer.In Fig. 4, each among the retainer 103a-103b can comprise at least one transistor (for example, transistor 141a-141b), is electrically connected with logic gate (for example, NOT door 140a-140b) respectively.In certain embodiments, each among the transistor 141a-141b can be N type metal oxide semiconductor (NMOS) transistor.For example, the input end N of NOT door 140a
2Can be electrically connected with drain electrode end and the storage unit 105a of transistor 141a.The output terminal N of NOT door 140a
3Can be electrically connected with the grid of transistor 141a.The source terminal of transistor 141a can be electrically connected with restrictor 110a.In certain embodiments, transistor 141a and 141b can be core transistors.
Refer again to Fig. 4, restrictor 110a can comprise at least one transistor, for example, and transistor 109.In certain embodiments, transistor 109 can be a nmos pass transistor.The source terminal of transistor 109 can be used to provide for example V
SSPerhaps the power lead of the supply voltage of ground connection is electrically connected.The drain electrode end of transistor 109 can be electrically connected with retainer 103a and 103b.The grid of transistor 109 can be used to provide for example V
DDThe power lead of supply voltage be electrically connected.In certain embodiments, transistor 109 can be called long channel transistor, and the channel length of this transistor 109 is greater than the channel length of transistor 141a.In the embodiment shown in Fig. 4, transistor m
3And m
4It is P-type mos (PMOS) transistor.
The precharge of storage unit 105a and inductive operation can be similar to the description that above combination Fig. 2 is done.According to dissimilar transistorized purposes, during precharge and/or inductive operation, can apply opposite voltage level and/or voltage status.
Fig. 5 shows the synoptic diagram of the exemplary memory circuit that comprises the restrictor that is connected with a plurality of the 4th retainers.In Fig. 5, each among the retainer 103a-103b can comprise at least one transistor (for example, transistor 151a, 153a and 151b, 153b), is electrically connected with logic gate (for example, NAND door 150a-150b) respectively.In certain embodiments, each among transistor 151a-151b and the transistor 153a-153b can be nmos pass transistor.For example, the input end A of NAND door 150a can with drain electrode end and the transistor m of transistor 153a
3S/D end be electrically connected.Another input end B of NAND door 150a can be electrically connected with another storage unit (not shown) with the drain electrode end of transistor 151a.The output terminal of NAND door 150a can be electrically connected with the grid of transistor 151a and 153a.The source terminal of transistor 151a and 153a can be electrically connected with restrictor 110a.In certain embodiments, each among transistor 151a and the 153a can be core transistor.In other embodiments, the channel length of transistor 109 is greater than the channel length of transistor 151a and 153a.
Notice that it only is exemplary more than combining the transistor of the described retainer 103a of Fig. 2-Fig. 5 and quantity, type and/or the configuration of logic gate.In certain embodiments, can use other logic gates (for example, AND door, OR door, NOR door, another logic gate, perhaps above-mentioned combination) that combine with at least one transistor with various configurations.The application's scope is not limited to this.
Fig. 6 shows the synoptic diagram of another memory circuit that has the restrictor of being shared by two row retainers.Among Fig. 6 with Fig. 1 in the element of the identical or similar memory circuit 200 of element of integrated circuit 100 increased by 100 or 110 than the reference number of the element among Fig. 1.In Fig. 6, memory circuit 200 can comprise a plurality of storage arrays (for example, storage array 201a-201d and 211a-211d) and a plurality of retainer (for example, retainer 203a-203d and 213a-213d).Among retainer 203a-203d and the 213a-213d each can be electrically connected with corresponding storage array 201a-201d and 211a-211d respectively.Restrictor 210a can be electrically connected with retainer 203a-203d and 213a-213d, and this retainer 203a-203d and 213a-213d can share this restrictor 210a.Because restrictor 210a can be shared by two row retainer 203a-203d and 213a-213d, therefore, the area of memory circuit 200 can further reduce.In another embodiment, restrictor 210a can with three row or more the retainer of multiple row be electrically connected, this three row or more the retainer of multiple row can share this restrictor 210a.
Fig. 7 shows the synoptic diagram of another memory circuit that has two restrictors being shared by the retainer of respective column.Among Fig. 7 with Fig. 1 in the element of the identical or similar memory circuit 300 of element of integrated circuit 100 increased by 200 or 210 than the reference number of the element among Fig. 1.In Fig. 7, memory circuit 300 can comprise a plurality of storage arrays (for example, storage array 301a-301d and 311a-311d) and a plurality of retainer (for example, retainer 303a-303d and 313a-313d).Among the storage array 311a-311d each places respectively on one the corresponding position of contiguous storage array 301a-301d.
Among retainer 303a-303d and the 313a-313d each can be electrically connected with corresponding storage array 301a-301d and 311a-311d respectively.Restrictor 310a and 310b can be electrically connected with retainer 303a-303d and 313a-313d, and this retainer 303a-303d and 313a-313d can share this restrictor 310a and 310b respectively.In certain embodiments, each among restrictor 310a and the 310b can with two row or more the multiple row retainer be electrically connected, and this two row or more the multiple row retainer can share this restrictor 310a and 310b.
Fig. 9 shows the synoptic diagram of the exemplary memory circuit that comprises a plurality of sector switches, and wherein, each sector switch all is electrically connected between restrictor and the corresponding retainer.Among Fig. 9 with Fig. 2 in the element of the identical or similar memory circuit 400 of element of integrated circuit 100 increased by 300 than the reference number of the element among Fig. 1.In Fig. 9, memory circuit 400 can comprise a plurality of storage arrays of placing with the mode of row, for example, and storage array 401a and 401b.Memory circuit 400 can comprise a plurality of retainers, and for example, retainer 403a and 403b, this retainer 403a and 403b are electrically connected with storage array 401a and 401b respectively.Memory circuit 400 can comprise restrictor, for example, restrictor 410a, this restrictor 410a can be electrically connected with retainer 403a and 403b, and this retainer 403a and 403b can share this restrictor 410a.Memory circuit 400 can comprise a plurality of sector switches, and for example, sector switch 422a and 422b, this sector switch 422a and 422b can be connected electrically between restrictor 410a and the retainer 403a respectively and between restrictor 410a and the retainer 403b.
With reference to figure 9, in certain embodiments, each among sector switch 422a and the 422b can comprise transistor, for example, and the transistor of PMOS transistor, nmos pass transistor and/or other types.In certain embodiments, the transistor of sector switch 422a can be a core transistor.The channel length of core transistor can be less than the channel length of the transistor 407 of restrictor 410a.In other embodiments, the transistorized channel length of sector switch 422a can be substantially equal to the channel length of the transistor 421a of retainer 403a.
In the embodiment of some access stored array 401a, between precharge phase and during the sensing, sector switch 422a can conducting.Between precharge phase and during the sensing, sector switch 422b can turn-off.Because sector switch 422b turn-offs, therefore, during the sensing of storage array 401a, the voltage level of retainer 403b (for example, the voltage level on the nodes X of retainer 403b) can not influence node N
4On voltage level.Because from node N
4The capacitive load of looking reduces, and therefore, the induction speed of storage array 401a improves.
Figure 10 shows the synoptic diagram of another exemplary memory circuit that comprises a plurality of sector switches, and wherein, each sector switch all is electrically connected between restrictor and the corresponding retainer.Among Figure 10 with Fig. 3 in the element of the identical or similar memory circuit 400 of element of integrated circuit 100 increased by 300 than the reference number of the element among Fig. 3.
With reference to Figure 10, memory circuit 400 can comprise sector switch 432a, 432b, 434a and 434b.Sector switch 432a, 434a can be connected electrically between restrictor 410a and the retainer 403a.Sector switch 432b, 434b can be connected electrically between restrictor 410a and the retainer 403b.In some embodiment of access stored array 410a, between precharge phase and/or during the sensing, can be with sector switch 432a and 434a conducting.Between precharge phase and during the sensing, can sector switch 432b, 434b be turn-offed.Because sector switch 432b, 434b turn-off, therefore, during the sensing of storage array 401a, the voltage level of retainer 403b (for example, the voltage level on node Y and the Z) can not influence node N
4On voltage level.Because from node N
4On the capacitive load of looking reduce, therefore, the induction speed of storage array 401a improves.
Noting, only is exemplary in conjunction with the sector switch of the above description that Fig. 9 and Figure 10 carried out.In certain embodiments, can sector switch be applied in the combination above-mentioned memory circuit 100 that Fig. 4 and Fig. 5 carried out.For example, each sector switch can comprise nmos pass transistor.Be also noted that although only show two sector switches, two storage arrays and two retainers, the application's scope is not limited to this.At some embodiment, can use more than two sector switches, more than two storage arrays and/or more than two retainers.
Figure 11 shows the synoptic diagram of the exemplary memory circuit that comprises a plurality of row switches, and wherein, each row switch all is connected electrically between restrictor and the respective column memory array.Among Figure 11 with Fig. 9 in the element of the identical or similar memory circuit 500 of element of integrated circuit 400 increased by 100 or 150 than the reference number of the element among Fig. 9.
With reference to Figure 11, memory circuit 400 can comprise row switch 502a and 502b.Row switch 502a and 502b can be connected electrically between restrictor 510a and the sector switch 522a-522b respectively and between restrictor 510a and the sector switch 572a-572b.In certain embodiments, for example, row switch 502a and 502b all can comprise the transistor of transistor such as PMOS transistor, nmos pass transistor and/or other types.The transistorized channel length of row switch 502a can be greater than the transistorized channel length of restrictor 510a.In other embodiments, the transistor of row switch 502a can be a core transistor.
In the embodiment of some access stored array 501a, between precharge phase and/or during the sensing, row switch 502a can conducting.Between precharge phase and during the sensing, row switch 502b can turn-off.Because row switch 502b turn-offs, therefore, during the sensing of the row of storage array 501a-501b, node N
5On voltage level can not influence node N
6On voltage level.Because from node N
6On the capacitive load of looking reduce, therefore, the induction speed of storage array 501a increases.
Noting, only is exemplary in conjunction with the row switch of the above description that Figure 11 carried out.In certain embodiments, can be in the memory circuit 100 that combines the above description that Figure 10 carried out with the row switch application.For example, Figure 12 shows the synoptic diagram of another exemplary memory circuit that comprises a plurality of row switches, and wherein, each row switch all is connected electrically between restrictor and the corresponding respective column memory array.The element of the identical or similar memory circuit 600 of element of the integrated circuit 500 among Figure 12 and Figure 10 has increased by 100 or 150 than the reference number of the element among Figure 10.In Figure 12, row switch 602a and 602b on the function with more than row switch 502a described in conjunction with Figure 11 similar with 502b.Be also noted that although only show two row storage arrays, the application's scope is not limited to this.In certain embodiments, can use more than two row storage arrays.
Fig. 8 shows the synoptic diagram of the system that comprises the exemplary memory circuit.In Fig. 8, system 800 can comprise processor 810, and this processor 810 is connected with memory circuit 801.Memory circuit 801 can with above combine one among Fig. 1-Fig. 7 and the described memory circuit 100-500 of Fig. 9-Figure 11 similar.Processor 810 can be that processing unit, central processing unit, digital signal processor or other are suitable for the processor of the data of access stored circuit.
In certain embodiments, processor 810 can be formed in the system with memory circuit 801, this system can with printed-wiring board (PWB) or printed circuit board (PCB) (PCB) physical connection and electrical connection mutually, thereby form electronic package.Electronic package can be the part such as the electronic system of computing machine, Wireless Telecom Equipment, computing machine periphery, amusement equipment or the like.
In certain embodiments, system 800 comprises memory circuit 801, and can on an IC, form complete system, attendes system (SOIC) device such as so-called SOC(system on a chip) (SOC) or integrated circuit.For example, these SOC devices can be provided in and realize needed all circuit of mobile phone, PDA(Personal Digital Assistant), digital VCR, DV, digital camera, MP3 player or the like in the single integrated circuit
In the application's a embodiment, a kind of memory circuit comprises: a plurality of first storage arrays, arrange with the mode of row; A plurality of first retainers, each first retainer all with a plurality of first storage arrays in corresponding one be electrically connected; First restrictor is electrically connected with a plurality of first retainers, and a plurality of first retainer is shared first restrictor; And a plurality of first sector switches, each first sector switch all is electrically connected in first restrictor and a plurality of first retainer between corresponding one.
In another embodiment of the application, a kind of memory circuit comprises: first restrictor, and wherein, first restrictor comprises the first transistor; A plurality of first storage arrays are arranged with the mode of row; A plurality of first retainers; Each first retainer all with a plurality of first storage arrays in corresponding one be electrically connected; A plurality of first retainers and first restrictor are electrically connected, and wherein, each in a plurality of first retainers all comprises: at least one transistor seconds; And logic gate, wherein, the output terminal of logic gate and the grid of at least one transistor seconds are electrically connected, and at least one input end of logic gate and at least one drain electrode of at least one transistor seconds are electrically connected; And a plurality of first sector switches, be connected electrically in first restrictor and a plurality of first retainer between corresponding one.
In other embodiment of the application, a kind of memory circuit comprises: first restrictor, be configured to, and during sensing, first electric current of first restrictor is flow through in control, and wherein, first restrictor comprises the first transistor; A plurality of first storage arrays are arranged with the mode of row, wherein; In a plurality of first storage arrays each all comprises at least one storage unit, and at least one storage unit comprises read port, and read port is configured to; During sensing; If the read port conducting, then first electric current can flow through read port, and at the read port two ends voltage drop is arranged; A plurality of first retainers; Each first retainer all with a plurality of first storage arrays in corresponding one be electrically connected; Wherein, In a plurality of first retainers each all comprises: at least one transistor seconds, and wherein, at least one source terminal and first restrictor of at least one transistor seconds are electrically connected; And logic gate, wherein, the output terminal of logic gate and the grid of at least one transistor seconds are electrically connected, and at least one input end of logic gate and at least one drain electrode of at least one transistor seconds are electrically connected; And a plurality of first sector switches, be connected electrically in first restrictor and a plurality of first retainer between corresponding one.
Discuss the parts of a plurality of embodiment above, made those of ordinary skills can understand various aspects of the present invention better.It will be understood by those skilled in the art that and to use the present invention to design or revise processing and structure that other are used to carry out the purpose identical with embodiment that this paper introduces and/or realize same advantage as the basis at an easy rate.Those of ordinary skills should also be appreciated that this equivalent constructions does not deviate from the spirit and scope of the present invention, and under the situation that does not deviate from the spirit and scope of the present invention, can carry out multiple variation, replacement and change.
Claims (10)
1. memory circuit comprises:
A plurality of first storage arrays are arranged with the mode of row;
A plurality of first retainers, each said first retainer all with said a plurality of first storage arrays in corresponding one be electrically connected;
First restrictor is electrically connected with said a plurality of first retainers, and said a plurality of first retainer is shared said first restrictor; And
A plurality of first sector switches, each said first sector switch all are electrically connected in said first restrictor and said a plurality of first retainer between corresponding one.
2. memory circuit according to claim 1, wherein, each in said a plurality of first storage arrays all comprises: at least one storage unit; Said at least one storage unit comprises read port, and said read port is configured to, during sensing; If said read port conducting, then first electric current can flow through said read port, and at said read port two ends voltage drop is arranged; Said first restrictor configuration is that during said sensing, second electric current of said first restrictor is flow through in control; And during said sensing, said first electric current is greater than said second electric current.
3. memory circuit according to claim 1 wherein, at least one during sensing and between precharge phase, visit in said a plurality of first storage array, and conducting is corresponding to the sector switch of the storage array of being visited.
4. memory circuit according to claim 1; Wherein, Said first restrictor comprises: the first transistor, and each in said a plurality of first sector switches all comprises core transistor, the channel length of said the first transistor is greater than the channel length of said core transistor.
5. memory circuit according to claim 1, wherein, each in said a plurality of first retainers all comprises:
At least one transistor seconds; And
Logic gate, wherein, the output terminal of said logic gate and the grid of said at least one transistor seconds are electrically connected, and at least one input end of said logic gate and at least one drain electrode of said at least one transistor seconds are electrically connected.
6. memory circuit according to claim 5, wherein, said logic gate is the NOT door, said at least one transistor seconds comprises single transistor.
7. memory circuit according to claim 5, wherein, said logic gate is the NAND door, said at least one transistor seconds comprises two or multiple transistor more.
8. memory circuit according to claim 1 further comprises:
A plurality of second storage arrays are arranged with the mode of row;
A plurality of second retainers, each said second retainer all with said a plurality of second storage arrays in corresponding one be electrically connected;
A plurality of second sector switches, each said second sector switch all are electrically connected in said first restrictor and said a plurality of second retainer between corresponding one;
The first row switch is connected electrically between said first restrictor and said a plurality of first sector switch; And
The secondary series switch is connected electrically between said first restrictor and said a plurality of second sector switch.
9. memory circuit comprises:
First restrictor, wherein, said first restrictor comprises the first transistor;
A plurality of first storage arrays are arranged with the mode of row;
A plurality of first retainers; Each said first retainer all with said a plurality of first storage arrays in corresponding one be electrically connected; Said a plurality of first retainer and said first restrictor are electrically connected, and wherein, each in said a plurality of first retainers all comprises:
At least one transistor seconds; And
Logic gate, wherein, the output terminal of said logic gate and the grid of said at least one transistor seconds are electrically connected, and at least one input end of said logic gate and at least one drain electrode of said at least one transistor seconds are electrically connected; And
A plurality of first sector switches are connected electrically in said first restrictor and said a plurality of first retainer between corresponding one.
10. memory circuit comprises:
First restrictor is configured to, and during sensing, first electric current of said first restrictor is flow through in control, and wherein, said first restrictor comprises the first transistor;
A plurality of first storage arrays are arranged with the mode of row, wherein; In said a plurality of first storage array each all comprises at least one storage unit, and said at least one storage unit comprises read port, and said read port is configured to; During said sensing; If said read port conducting, then first electric current can flow through said read port, and at said read port two ends voltage drop is arranged;
A plurality of first retainers, each said first retainer all with said a plurality of first storage arrays in corresponding one be electrically connected, wherein, each in said a plurality of first retainers all comprises:
At least one transistor seconds, wherein, at least one source terminal of said at least one transistor seconds and said first restrictor are electrically connected; And
Logic gate, wherein, the output terminal of said logic gate and the grid of said at least one transistor seconds are electrically connected, and at least one input end of said logic gate and at least one drain electrode of said at least one transistor seconds are electrically connected; And
A plurality of first sector switches are connected electrically in said first restrictor and said a plurality of first retainer between corresponding one.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/025,668 US8406078B2 (en) | 2010-05-12 | 2011-02-11 | Memory circuits having a plurality of keepers |
| US13/025,668 | 2011-02-11 |
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| CN102637458A true CN102637458A (en) | 2012-08-15 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103198860A (en) * | 2013-03-15 | 2013-07-10 | 清华大学 | Resistive random access memory (RRAM) writing circuit |
| CN103680625A (en) * | 2012-09-06 | 2014-03-26 | 英飞凌科技股份有限公司 | System and method for providing voltage supply protection in memory device |
| CN109217877A (en) * | 2017-06-29 | 2019-01-15 | 爱思开海力士有限公司 | Serializer and storage device including the serializer |
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| CN1199229A (en) * | 1997-03-31 | 1998-11-18 | 精工爱普生株式会社 | Low power memory including selective precharge circuit |
| US20090086529A1 (en) * | 2007-09-28 | 2009-04-02 | Nec Electronics Corporation | Semiconductor storage device |
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| CN1199229A (en) * | 1997-03-31 | 1998-11-18 | 精工爱普生株式会社 | Low power memory including selective precharge circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103680625A (en) * | 2012-09-06 | 2014-03-26 | 英飞凌科技股份有限公司 | System and method for providing voltage supply protection in memory device |
| CN103198860A (en) * | 2013-03-15 | 2013-07-10 | 清华大学 | Resistive random access memory (RRAM) writing circuit |
| CN103198860B (en) * | 2013-03-15 | 2015-12-09 | 清华大学 | A kind of RRAM write circuit |
| CN109217877A (en) * | 2017-06-29 | 2019-01-15 | 爱思开海力士有限公司 | Serializer and storage device including the serializer |
| CN109217877B (en) * | 2017-06-29 | 2022-05-31 | 爱思开海力士有限公司 | Serializer and memory device including the same |
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| CN102637458B (en) | 2015-07-08 |
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