CN102637458B - Memory circuits having a plurality of keepers - Google Patents
Memory circuits having a plurality of keepers Download PDFInfo
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- CN102637458B CN102637458B CN201110326239.4A CN201110326239A CN102637458B CN 102637458 B CN102637458 B CN 102637458B CN 201110326239 A CN201110326239 A CN 201110326239A CN 102637458 B CN102637458 B CN 102637458B
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Abstract
A memory circuit includes a first plurality of memory arrays disposed in a column fashion; a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays; a first current limiter which is electrically coupled with and shared by the first plurality of keepers; and a first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers.
Description
The cross reference of related application
The application be on May 12nd, 2010 propose be entitled as " MEMORY CIRCUITS HAVINGA PLURALITY OF KEEPERS " the 12/778th, the part continuation application of No. 714 U.S. Patent applications, its full content is incorporated herein by reference.
Technical field
The present invention relates generally to semiconductor circuit field, more specifically, relates to the memory circuit with multiple retainer.
Background technology
Memory circuit is used for various uses.Usually, memory circuit can comprise dynamic RAM (DRAM) circuit, static RAM (SRAM) circuit, Nonvolatile memory circuit.SRAM circuit comprises multiple storage unit.For traditional 6-T SRAM circuit being wherein formed with memory cell array, each storage unit has six transistors.6-T SRAM memory cell is connected with wordline WL with bit line BL, bit line bar BLB.Four in six transistors define two cross-linked phase inverters, for storing the data of representative " 0 " or " 1 ".Two remaining transistors are used as access transistor, control the access of the data stored in the memory unit.
Summary of the invention
For solving the problem, the invention provides a kind of memory circuit, comprising: multiple first storage array, arrange in the mode arranged; Multiple first retainer, one that each first retainer is corresponding with multiple first storage array is electrically connected; First restrictor, is electrically connected with multiple first retainer, and the first restrictor shared by multiple first retainer; And multiple first sector switch, each first sector switch to be electrically connected in the first restrictor and multiple first retainer between corresponding one.
Wherein, each in multiple first storage array comprises: at least one storage unit, and at least one storage unit comprises read port, read port is configured to, at sensing, if read port conducting, then the first electric current can flow through read port, and there is voltage drop at read port two ends, first restrictor configuration is, at sensing, controls the second electric current flowing through the first restrictor, and at sensing, the first electric current is greater than the second electric current.
Wherein, at least one between sensing and precharge phase, access in multiple first storage array, and conducting corresponds to the sector switch of accessed storage array.
Wherein, the first restrictor comprises: the first transistor, and each in multiple first sector switch comprises core transistor, and the channel length of the first transistor is greater than the channel length of core transistor.
Wherein, each in multiple first retainer comprises: at least one transistor seconds; And logic gate, wherein, the grid of the output terminal of logic gate and at least one transistor seconds is electrically connected, and at least one of at least one input end of logic gate and at least one transistor seconds drains and be electrically connected.
Wherein, logic gate is NOT door, and at least one transistor seconds comprises single transistor.
Wherein, logic gate is NAND door, and at least one transistor seconds comprises two or more transistor.
This memory circuit comprises further: multiple second storage array, arranges in the mode arranged; Multiple second retainer, one that each second retainer is corresponding with multiple second storage array is electrically connected; Multiple second sector switch, each second sector switch to be electrically connected in the first restrictor and multiple second retainer between corresponding one; First row switch, is connected electrically between the first restrictor and multiple first sector switch; And secondary series switch, be connected electrically between the first restrictor and multiple second sector switch.
Wherein, the first restrictor comprises the first transistor, and first row switch comprises transistor seconds, and the channel length of transistor seconds is less than the channel length of the first transistor.
In addition, additionally provide a kind of memory circuit, comprising: the first restrictor, wherein, the first restrictor comprises the first transistor; Multiple first storage array, arranges in the mode arranged; Multiple first retainer, one that each first retainer is corresponding with multiple first storage array is electrically connected, multiple first retainer and the first restrictor are electrically connected, and wherein, each in multiple first retainer comprises: at least one transistor seconds; And logic gate, wherein, the grid of the output terminal of logic gate and at least one transistor seconds is electrically connected, and at least one of at least one input end of logic gate and at least one transistor seconds drains and be electrically connected; And multiple first sector switch, to be connected electrically in the first restrictor and multiple first retainer between corresponding one.
Wherein, each in multiple first storage array comprises: at least one storage unit, and at least one storage unit comprises read port, read port is configured to, at sensing, if read port conducting, then the first electric current can flow through read port, and there is voltage drop at read port two ends, first restrictor configuration is, at sensing, controls the second electric current flowing through the first restrictor, and at sensing, the first electric current is greater than the second electric current.
Wherein, at least one between sensing and precharge phase, access in multiple first storage array, and conducting corresponds to the sector switch of accessed storage array.
Wherein, the first sector switch comprises core transistor, and the channel length of the first transistor is greater than the channel length of core transistor.
This memory circuit comprises further: multiple second storage array, arranges in the mode arranged; Multiple second retainer, one that each second retainer is corresponding with multiple second storage array is electrically connected; Multiple second sector switch, each second sector switch to be connected electrically in the first restrictor and multiple second retainer between corresponding one; First row switch, is connected electrically between the first restrictor and multiple first sector switch; And secondary series switch, be connected electrically between the first restrictor and multiple second sector switch.
Wherein, first row switch comprises third transistor, and the channel length of third transistor is greater than the channel length of the first transistor.
In addition, be also supplied to a kind of memory circuit, comprise: the first restrictor, is configured to, at sensing, control the first electric current flowing through the first restrictor, wherein, the first restrictor comprises the first transistor; Multiple first storage array, arrange in the mode of row, wherein, each in multiple first storage array comprises at least one storage unit, and at least one storage unit comprises read port, and read port is configured to, at sensing, if read port conducting, then the first electric current can flow through read port, and has voltage drop at read port two ends; Multiple first retainer, one that each first retainer is corresponding with multiple first storage array is electrically connected, wherein, each in multiple first retainer comprises: at least one transistor seconds, wherein, at least one source terminal of at least one transistor seconds and the first restrictor are electrically connected; And logic gate, wherein, the grid of the output terminal of logic gate and at least one transistor seconds is electrically connected, and at least one of at least one input end of logic gate and at least one transistor seconds drains and be electrically connected; And multiple first sector switch, to be connected electrically in the first restrictor and multiple first retainer between corresponding one.
Wherein, at least one between sensing and precharge phase, access in multiple first memory circuit, and conducting corresponds to the sector switch of accessed storage array.
Wherein, the first sector switch comprises core transistor, and the channel length of the first transistor is greater than the channel length of core transistor.
Wherein, logic gate is NOT door, and at least one transistor seconds comprises single transistor.
Wherein, logic gate is NAND door, and at least one transistor seconds comprises two or more transistor.
Accompanying drawing explanation
The present invention can be understood best according to the detailed description below in conjunction with accompanying drawing.It is emphasized that according to the standard practices in industry, various different parts are not drawn in proportion, and just for illustrated object.In fact, in order to make discussion clear, can increase arbitrarily or reduce quantity and the size of various parts.
Fig. 1 shows the schematic diagram of the exemplary memory circuit comprising the restrictor be connected with multiple retainer.
Fig. 2 shows the schematic diagram of another exemplary memory circuit comprising the restrictor be connected with multiple first example retainer.
Fig. 3 shows the schematic diagram of another exemplary memory circuit comprising the restrictor be connected with multiple second example retainer.
Fig. 4 shows the schematic diagram of the exemplary memory circuit comprising the restrictor be connected with multiple 3rd example retainer.
Fig. 5 shows the schematic diagram of the exemplary memory circuit comprising the restrictor be connected with multiple 4th example retainer.
Fig. 6 shows the schematic diagram of another memory circuit with the restrictor shared by two row retainers.
Fig. 7 shows the schematic diagram of another memory circuit of two restrictors shared with the retainer by respective column.
Fig. 8 shows the schematic diagram of the system comprising exemplary memory circuit.
Fig. 9 shows the schematic diagram of the exemplary memory circuit comprising multiple sector switch, and wherein, each sector switch is electrically connected between restrictor and corresponding retainer.
Figure 10 shows the schematic diagram of another exemplary memory circuit comprising multiple sector switch, and wherein, each sector switch is connected electrically between restrictor and corresponding retainer.
Figure 11 shows the schematic diagram of the exemplary memory circuit comprising multiple row switch, and wherein, each row switch is connected electrically between restrictor and the memory array of respective column.
Figure 12 shows the schematic diagram of another exemplary memory circuit comprising multiple row switch, and wherein, each row switch is connected electrically between restrictor and the memory array of respective column.
Embodiment
Usually, SRAM circuit has multiple storage array and multiple retainer.Storage array and retainer are placed in the single row of SRAM circuit successively.Each retainer has long channel MOSFET, and this long channel MOSFET is electrically connected with phase inverter.The channel length of long channel MOSFET is greater than the channel length of core transistor substantially.Because each retainer is with long channel MOSFET, therefore, SRAM circuit needs to provide larger area to be used for holding the long channel MOSFET of retainer.
Should be appreciated that, following discloses content provides many different embodiments for implementing disclosed different characteristic or example.The instantiation of assembly and configuration is below described to simplify the present invention.Certainly, this is only example, is not intended to limit the invention.In addition, content of the present disclosure can in different instances repeat reference numerals and/or letter.This repetition is to simplify and object clearly, and does not represent that the relation between configuring is discussed by each embodiment and/or institute in itself.In addition, being formed in by parts in following the present invention to connect on another parts, with another parts and/or is coupled and can comprise the embodiment that parts are formed directly to contact, the embodiment that other parts are formed as being placed in (such as, parts directly do not contact) between parts can also be comprised.In addition, the term of relative space position, such as " below ", " top ", " level ", " vertically ", " ... on ", " ... under ", " upwards ", " downwards ", " top ", " bottom " etc. and derivative (such as, " flatly ", " down ", " up " etc.) thereof be for making the relation of in content of the present invention parts and another parts become simple and clear.The difference that the term of relative space position covers the device comprising parts is directed.
Fig. 1 shows the schematic diagram of the exemplary memory circuit comprising the restrictor be connected with multiple retainer.In FIG, memory circuit 100 can comprise multiple storage array (such as, storage array 101a-101d) and multiple retainer (such as, retainer 103a-103d).In certain embodiments, integrated circuit 100 can be static RAM (SRAM) circuit (such as, single port induction SRAM circuit or multi-port SRAM circuit), embedded SRAM circuit (such as, single port induction embedded SRAM circuit or multiport embedded SRAM circuit) or the memory circuit of other types.Note, the quantity of the storage array shown in Fig. 1 and retainer is only exemplary.In certain embodiments, more array and/or retainer can be increased.
In certain embodiments, each in retainer 103a-103d is electrically connected with corresponding storage array 101a-101d respectively.Memory circuit 100 can comprise at least one restrictor, such as, and restrictor 110a.Restrictor 110a can be electrically connected with retainer 103a-103d, and this retainer 103a-103d can share this restrictor 110a.In certain embodiments, restrictor 110a can be connected electrically in provides such as V
dDsupply voltage power lead and such as V is provided
sSor between another power lead of the supply voltage of ground connection (not shown).
In certain embodiments, the sensing of the data stored in the storage unit (not shown) of one of induction storage array 101a-101d, restrictor 110a can be configured to control and/or limit the electric current flowing through restrictor 110a.At sensing, if the read port conducting of storage unit, have voltage drop between read port, then another electric current can flow through the read port of storage unit, thus the electric current in antagonism (fight) restrictor 110a.Due to electric current antagonism, the data stored in storage unit can be responded to, and/or the data stored in output storage unit are to respond to further.Can find, retainer 103a-103d can share restrictor 110a, thus runs the sensed data stored in storage array 101a-101d respectively.Because retainer 103a-103d has the transistor of small channel, because this reducing the area of retainer 103a-103d.Also reduce the area of the integrated circuit 100 for holding retainer 103a-103d.
Fig. 2 shows the schematic diagram of the exemplary memory circuit comprising the restrictor be connected with multiple first example retainer.In fig. 2, each in storage array 101a-101b can comprise at least one storage unit respectively, such as, and storage unit 105a-105b.For the embodiment using 8-T SRAM memory cell, each in storage array 101a-101b can comprise many wordline WL1 and WL2 and multiple bit lines BL and BLB.Each in storage unit 105a-105b can with bit line BL, bit line bar BLB, wordline WL1 and WL2, for providing such as V
dDsupply voltage the first power lead and for providing such as V
sSor the second source line of the supply voltage of ground connection is electrically connected.Note, although illustrate only a storage unit 105a in storage array 101a, other storage unit (not shown) can also be connected with WL2 and multiple bit lines BL with BLB with many wordline WL1 of storage array 101a.In certain embodiments, each in storage array 101a-101b can have, and can be arranged as word width be 8,16,32,64,128 or more multiple row.In other embodiments, wordline WL1 and/or WL2 can layout for being basically perpendicular to bit line BL and BLB.In other embodiments, other arrangements of wordline WL1 and WL2 and bit line BL and BLB can be provided.
Two intersections latch inverters (not marking) of the trigger formed for the data of storing storage units 105a can be comprised with reference to figure 2, storage unit 105a.Transistor m
1and m
2grid can be electrically connected with wordline WL 1.Transistor m
1and m
2can run as two transmission (pass) transistors, access transistor or transmission grid.Storage unit 105a can also comprise read port (not marking).In certain embodiments, read port can comprise transistor m
3and m
4.Transistor m
3grid can be electrically connected with wordline WL2.Transistor m
3source/drain (S/D) end can be electrically connected with retainer 103a.Transistor m
4grid can with intersect the node N1 of latch inverters and be electrically connected.Transistor m
3and m
4can run as two transmission transistors, access transistor or transmission grid.In embodiment in fig. 2, transistor m
3and m
4it is N-type metal-oxide semiconductor (MOS) (NMOS) transistor.
With reference to figure 2, each in retainer 103a-103b can comprise at least one transistor (such as, transistor 121a-121b), is electrically connected respectively with logic gate (such as, NOT door 120a-120b).In certain embodiments, each in NOT door 120a-120b can be called phase inverter.In this embodiment, each in transistor 121a-121b can be P-type mos (PMOS) transistor.In certain embodiments, the input end N of NOT door 120a
2can with the drain electrode end of transistor 121a and transistor m
3s/D end be electrically connected.The output terminal N of NOT door 120a
3can be electrically connected with the grid of transistor 121a.In certain embodiments, each in transistor 121a and 121b can be core transistor.Term " core transistor " can represent the transistor formed according to the process node forming memory circuit 100.Such as, if process node is 40-nm (nanometer) technology, then the channel length of core transistor can be about 40nm.Note, above-mentioned process node is only exemplary.In other embodiments, process node can be larger or less than 40-nm technology.In other embodiments, the channel length of transistor 121a can be substantially equal to the channel length of the transistor (not shown) of the intersection latch inverters of storage unit 105a.
Refer again to Fig. 2, restrictor 110a can comprise at least one transistor, such as, and transistor 107.In certain embodiments, transistor 107 can be PMOS transistor.The source terminal of transistor 107 can with provide such as V
dDthe power lead of supply voltage be electrically connected.The drain electrode end of transistor 107 can be electrically connected with retainer 103a and 103b.The grid of transistor 107 can with provide such as V
sSor the power lead of the supply voltage of ground connection is electrically connected.Between precharge phase and/or sensing, supply voltage V
sSor ground connection can by transistor 107 conducting.In certain embodiments, the channel length of transistor 107 is greater than the channel length of transistor 121a.In other embodiments, transistor 107 can be called long channel MOSFET.
As described in, retainer 103a can comprise transistor 121a (such as, core transistor), and the raceway groove of this transistor 121a is less than the raceway groove of transistor 107, and can as transmission grid run.The area of retainer 103a can be less than the area of the traditional retainers using long channel device.Be also noted that, retainer 103a-103b can share this restrictor 110a.The total area of memory circuit 100 can be less than the SRAM circuit using traditional retainers.
Following description has about the input end N by NOT door 120a
2the illustrative methods of precharge.Between precharge phase, with the input end N of NOT grid 120a
2at least one the precharge transistor (not shown) be connected can conducting.The precharge transistor of conducting can by the input end N of NOT door 120a
2be electrically connected to power lead, thus by the input end N of NOT door 120a
2be pre-charged to supply voltage, such as, V
dD.Between precharge phase, transistor m
3turn off.The transistor m turned off
3can by storage unit 105a and retainer 103a electric isolution.
As described in, the input end N of NOT door 120a
2supply voltage V can be pre-charged to
dD.Once the input end N of NOT door 120a
2on voltage increase to predetermined voltage level or supply voltage V
dD, then NOT door 120a can by the input end N of NOT door 120a
2on voltage status (such as, high-voltage state) be turned to the input end N of NOT door 120a
3upper another voltage status (such as, low-voltage state).Low-voltage state (such as, has supply voltage V
sSor ground connection) can by transistor 121a conducting.
As described in, between precharge phase, transistor 107 conducting.The transistor 107 of conducting can by supply voltage V
dDbe electrically connected to the source terminal of transistor 121a.The transistor 121a of conducting can by the supply voltage V of the source terminal of transistor 121a
dDbe electrically connected to the input end N of NOT door 120a
2.Therefore, the input end N of NOT door 120a
2on voltage level can remain on supply voltage V
dD.More than storage unit 105b can also be applied in conjunction with the precharge operation described by storage unit 105a.
Relating to below responds to the illustrative methods of the data be stored in storage unit 105a.In certain embodiments, before sensing, precharge transistor (not shown) can turn off.Due to the data be stored in storage unit 105a will be accessed, therefore, the wordline WL1 ' of storage unit 105b and/or WL2 ' not charging.
At sensing, the wordline WL2 of storage unit 105a can charge, thus by transistor m
3conducting.In certain embodiments, the node N of intersection latch inverters
1the logic state of such as logical one can be stored or there is the voltage status of such as high-voltage state.Node N
1on voltage status can by transistor m
4conducting.The transistor m of conducting
3and m
4can by the input end N of NOT door 120a
2be electrically connected to supply voltage, such as, V
sSor ground connection.In certain embodiments, transistor m
3and m
4activation can be called the activation of the read port of storage unit 105a.As described in, after between precharge phase, the input end N of NOT door 120a
2on voltage level can remain on supply voltage V at first
dD.Due to transistor m
3and m
4the voltage drop at two ends, at sensing, can have electric current to flow through transistor m
3and m
4.
As described in, restrictor 110a is configured to control and/or the electric current of restrictor 110a is flow through in restriction.Such as, at sensing, transistor 107 conducting.At sensing, electric current can be had to flow through transistor 107.Can find, at sensing, flow through transistor m
3and m
4electric current can be greater than the electric current flowing through transistor 107.Due to electric current antagonism, the input end N of NOT door 120a
2on voltage level can be pulled down to supply voltage V
sSor ground connection.Once the input end N of NOT door 120a
2on voltage lower than predetermined voltage level or reach supply voltage V
sS, NOT door 120a can by the input end N of NOT door 120a
2on voltage status (such as, low-voltage state) be turned to the input end N of NOT door 120a
3on another voltage status (such as, high-voltage state).High-voltage state (such as, has supply voltage V
dD) transistor 121a can be turned off.The transistor 121a turned off can by the supply voltage V on the drain electrode end of transistor 107
dDwith the input end N of NOT door 120a
2electric isolution.Therefore, the input end N of NOT door 120a
2on voltage status can remain on supply voltage V
sS.Therefore, the data be stored in storage unit 105a can be responded to, and/or export to respond to further.
Fig. 3 shows the schematic diagram of another exemplary memory circuit comprising the restrictor be connected with multiple second example retainer.In figure 3, each in retainer 103a-103b can comprise at least one transistor (such as, transistor 131a, 133a and 131b, 133b), is electrically connected respectively with logic gate (such as, NAND door 130a-130b).In certain embodiments, each in transistor 131a-131b and transistor 133a-133b can be PMOS transistor.The input end A of NAND door 130a can with the drain electrode end of transistor 133a and transistor m
3s/D end be electrically connected.Another input end B of NAND door 130a can be electrically connected with the drain electrode end of transistor 131a and another storage unit (not shown).The output terminal of NAND door 130a can be electrically connected with the grid of transistor 131a and 133a.The source terminal of transistor 131a and 133a can be electrically connected with restrictor 110a.In certain embodiments, each in transistor 131a and 133a can be core transistor.In other embodiments, the channel length of transistor 107 is greater than the channel length of transistor 131a and 133a respectively.
The precharge of storage unit 105a and inductive operation can be similar to the description that above composition graphs 2 is done.Different according to the purposes of logic gate, the method for operation of NAND door 130a and transistor 131a and 133a also can be different.In addition, input end A and B of NAND door 130a is electrically connected from different storage unit.
Fig. 4 shows the schematic diagram of the exemplary memory circuit comprising the restrictor be connected with multiple 3rd example retainer.In the diagram, each in retainer 103a-103b can comprise at least one transistor (such as, transistor 141a-141b), is electrically connected respectively with logic gate (such as, NOT door 140a-140b).In certain embodiments, each in transistor 141a-141b can be N-type metal-oxide semiconductor (MOS) (NMOS) transistor.Such as, the input end N of NOT door 140a
2can be electrically connected with the drain electrode end of transistor 141a and storage unit 105a.The output terminal N of NOT door 140a
3can be electrically connected with the grid of transistor 141a.The source terminal of transistor 141a can be electrically connected with restrictor 110a.In certain embodiments, transistor 141a and 141b can be core transistor.
Refer again to Fig. 4, restrictor 110a can comprise at least one transistor, such as, and transistor 109.In certain embodiments, transistor 109 can be nmos pass transistor.The source terminal of transistor 109 can with for providing such as V
sSor the power lead of the supply voltage of ground connection is electrically connected.The drain electrode end of transistor 109 can be electrically connected with retainer 103a and 103b.The grid of transistor 109 can with for providing such as V
dDthe power lead of supply voltage be electrically connected.In certain embodiments, transistor 109 can be called long channel MOSFET, and the channel length of this transistor 109 is greater than the channel length of transistor 141a.In embodiment shown in the diagram, transistor m
3and m
4it is P-type mos (PMOS) transistor.
The precharge of storage unit 105a and inductive operation can be similar to the description that above composition graphs 2 is done.According to the purposes of dissimilar transistor, during precharge and/or inductive operation, contrary voltage level and/or voltage status can be applied.
Fig. 5 shows the schematic diagram of the exemplary memory circuit comprising the restrictor be connected with multiple 4th retainer.In Figure 5, each in retainer 103a-103b can comprise at least one transistor (such as, transistor 151a, 153a and 151b, 153b), is electrically connected respectively with logic gate (such as, NAND door 150a-150b).In certain embodiments, each in transistor 151a-151b and transistor 153a-153b can be nmos pass transistor.Such as, NAND door 150a input end A can with the drain electrode end of transistor 153a and transistor m
3s/D end be electrically connected.Another input end B of NAND door 150a can be electrically connected with the drain electrode end of transistor 151a and another storage unit (not shown).The output terminal of NAND door 150a can be electrically connected with the grid of transistor 151a and 153a.The source terminal of transistor 151a and 153a can be electrically connected with restrictor 110a.In certain embodiments, each in transistor 151a and 153a can be core transistor.In other embodiments, the channel length of transistor 109 is greater than the channel length of transistor 151a and 153a.
Note, the transistor of the retainer 103a described by above composition graphs 2-Fig. 5 and the quantity of logic gate, type and/or configuration are only exemplary.In certain embodiments, other logic gates (such as, AND door, OR door, NOR door, another logic gate, or above-mentioned combination) that to combine with at least one transistor with various configuration can be used.The scope of the application is not limited to this.
Fig. 6 shows the schematic diagram of another memory circuit with the restrictor shared by two row retainers.The element of memory circuit 200 identical or similar with the element of the integrated circuit 100 in Fig. 1 in Fig. 6 adds 100 or 110 than the reference number of the element in Fig. 1.In figure 6, memory circuit 200 can comprise multiple storage array (such as, storage array 201a-201d and 211a-211d) and multiple retainer (such as, retainer 203a-203d and 213a-213d).Each in retainer 203a-203d and 213a-213d can be electrically connected with corresponding storage array 201a-201d and 211a-211d respectively.Restrictor 210a can be electrically connected with retainer 203a-203d and 213a-213d, and this retainer 203a-203d and 213a-213d can share this restrictor 210a.Because restrictor 210a can be shared by two row retainer 203a-203d and 213a-213d, therefore, the area of memory circuit 200 can reduce further.In another embodiment, restrictor 210a can arrange with three or the retainer of more multiple row is electrically connected, and the retainer of these three row or more multiple row can share this restrictor 210a.
Fig. 7 shows the schematic diagram of another memory circuit of two restrictors shared with the retainer by respective column.The element of memory circuit 300 identical or similar with the element of the integrated circuit 100 in Fig. 1 in Fig. 7 adds 200 or 210 than the reference number of the element in Fig. 1.In the figure 7, memory circuit 300 can comprise multiple storage array (such as, storage array 301a-301d and 311a-311d) and multiple retainer (such as, retainer 303a-303d and 313a-313d).On each position of being placed in contiguous storage array 301a-301d correspondence respectively in storage array 311a-311d.
Each in retainer 303a-303d and 313a-313d can be electrically connected with corresponding storage array 301a-301d and 311a-311d respectively.Restrictor 310a and 310b can be electrically connected with retainer 303a-303d and 313a-313d, and this retainer 303a-303d and 313a-313d can share this restrictor 310a and 310b respectively.In certain embodiments, each in restrictor 310a and 310b can arrange with two or more multiple row retainer is electrically connected, and these two row or more multiple row retainer can share this restrictor 310a and 310b.
Fig. 9 shows the schematic diagram of the exemplary memory circuit comprising multiple sector switch, and wherein, each sector switch is electrically connected between restrictor and corresponding retainer.The element of memory circuit 400 identical or similar with the element of the integrated circuit 100 in Fig. 2 in Fig. 9 adds 300 than the reference number of the element in Fig. 1.In fig .9, multiple storage arrays that the mode that memory circuit 400 can comprise arranging is placed, such as, storage array 401a and 401b.Memory circuit 400 can comprise multiple retainer, and such as, retainer 403a and 403b, this retainer 403a and 403b is electrically connected with storage array 401a and 401b respectively.Memory circuit 400 can comprise restrictor, and such as, restrictor 410a, this restrictor 410a can be electrically connected with retainer 403a and 403b, and this retainer 403a and 403b can share this restrictor 410a.Memory circuit 400 can comprise multiple sector switch, and such as, sector switch 422a and 422b, this sector switch 422a and 422b can be connected electrically between restrictor 410a and retainer 403a and between restrictor 410a and retainer 403b respectively.
With reference to figure 9, in certain embodiments, each in sector switch 422a and 422b can comprise transistor, such as, and the transistor of PMOS transistor, nmos pass transistor and/or other types.In certain embodiments, the transistor of sector switch 422a can be core transistor.The channel length of core transistor can be less than the channel length of the transistor 407 of restrictor 410a.In other embodiments, the channel length of the transistor of sector switch 422a can be substantially equal to the channel length of the transistor 421a of retainer 403a.
In the embodiment of some access storage array 401a, between precharge phase and sensing, sector switch 422a can conducting.Between precharge phase and sensing, sector switch 422b can turn off.Because sector switch 422b turns off, therefore, at the sensing of storage array 401a, the voltage level of retainer 403b (voltage level in the nodes X of such as, retainer 403b) can not affect node N
4on voltage level.Due to from node N
4the capacitive load of looking reduces, and therefore, the induction speed of storage array 401a improves.
Figure 10 shows the schematic diagram of another exemplary memory circuit comprising multiple sector switch, and wherein, each sector switch is electrically connected between restrictor and corresponding retainer.The element of memory circuit 400 identical or similar with the element of the integrated circuit 100 in Fig. 3 in Figure 10 adds 300 than the reference number of the element in Fig. 3.
With reference to Figure 10, memory circuit 400 can comprise sector switch 432a, 432b, 434a and 434b.Sector switch 432a, 434a can be connected electrically between restrictor 410a and retainer 403a.Sector switch 432b, 434b can be connected electrically between restrictor 410a and retainer 403b.In some embodiments of access storage array 410a, between precharge phase and/or sensing, can by sector switch 432a and 434a conducting.Between precharge phase and sensing, sector switch 432b, 434b can be turned off.Because sector switch 432b, 434b turn off, therefore, at the sensing of storage array 401a, the voltage level (voltage level such as, on node Y and Z) of retainer 403b can not affect node N
4on voltage level.Due to from node N
4on the capacitive load of looking reduce, therefore, the induction speed of storage array 401a improves.
Note, the sector switch described above that composition graphs 9 and Figure 10 carry out is only exemplary.In certain embodiments, sector switch can be applied in the above-mentioned memory circuit 100 that composition graphs 4 and Fig. 5 carry out.Such as, each sector switch can comprise nmos pass transistor.Be also noted that, although illustrate only two sector switches, two storage arrays and two retainers, the scope of the application is not limited to this.In some embodiments, can use more than two sector switches, more than two storage arrays and/or more than two retainers.
Figure 11 shows the schematic diagram of the exemplary memory circuit comprising multiple row switch, and wherein, each row switch is connected electrically between restrictor and respective column memory array.The element of memory circuit 500 identical or similar with the element of the integrated circuit 400 in Fig. 9 in Figure 11 adds 100 or 150 than the reference number of the element in Fig. 9.
With reference to Figure 11, memory circuit 400 can comprise row switch 502a and 502b.Row switch 502a and 502b can be connected electrically between restrictor 510a and sector switch 522a-522b and between restrictor 510a and sector switch 572a-572b respectively.In certain embodiments, such as, row switch 502a and 502b all can comprise the transistor of transistor such as PMOS transistor, nmos pass transistor and/or other types.The channel length of the transistor of row switch 502a can be greater than the channel length of the transistor of restrictor 510a.In other embodiments, the transistor of row switch 502a can be core transistor.
In the embodiment of some access storage array 501a, between precharge phase and/or sensing, row switch 502a can conducting.Between precharge phase and sensing, row switch 502b can turn off.Because row switch 502b turns off, therefore, at the sensing of the row of storage array 501a-501b, node N
5on voltage level can not affect node N
6on voltage level.Due to from node N
6on the capacitive load of looking reduce, therefore, the induction speed of storage array 501a increases.
Note, the row switch described above carried out in conjunction with Figure 11 is only exemplary.In certain embodiments, can by row switch application in the memory circuit described above 100 carried out in conjunction with Figure 10.Such as, Figure 12 shows the schematic diagram of another exemplary memory circuit comprising multiple row switch, and wherein, each row switch is connected electrically between restrictor and corresponding respective column memory array.The element of the memory circuit 600 that the element of the integrated circuit 500 in Figure 12 and Figure 10 is identical or similar adds 100 or 150 than the reference number of the element in Figure 10.In fig. 12, row switch 602a with 602b is functionally similar to above row switch 502a with 502b described in conjunction with Figure 11.Be also noted that, although illustrate only two row storage arrays, the scope of the application is not limited to this.In certain embodiments, can use more than two row storage arrays.
Fig. 8 shows the schematic diagram of the system comprising exemplary memory circuit.In fig. 8, system 800 can comprise processor 810, and this processor 810 is connected with memory circuit 801.Memory circuit 801 can be similar with in the memory circuit 100-500 described by above composition graphs 1-Fig. 7 and Fig. 9-Figure 11.Processor 810 can be processing unit, central processing unit, digital signal processor or other be suitable for the processor of data of accessing memory circuit.
In certain embodiments, processor 810 and memory circuit 801 can be formed in systems in which, and this system with printed-wiring board (PWB) or printed circuit board (PCB) (PCB) phase physical connection and can be electrically connected, thus form electronic package.Electronic package can be a part for the electronic system of such as computing machine, Wireless Telecom Equipment, computing machine periphery, amusement equipment etc.
In certain embodiments, system 800 comprises memory circuit 801, and can form complete system on one piece of IC, such as so-called SOC (system on a chip) (SOC) or systems on integrated circuits (SOIC) device.Such as, these SOC devices can be provided in single integrated circuit and realize the required all circuit of mobile phone, personal digital assistant (PDA), digital VCR, Digital Video, digital camera, MP3 player etc.
In an embodiment of the application, a kind of memory circuit, comprising: multiple first storage array, arranges in the mode arranged; Multiple first retainer, one that each first retainer is corresponding with multiple first storage array is electrically connected; First restrictor, is electrically connected with multiple first retainer, and the first restrictor shared by multiple first retainer; And multiple first sector switch, each first sector switch to be electrically connected in the first restrictor and multiple first retainer between corresponding one.
In another embodiment of the application, a kind of memory circuit, comprising: the first restrictor, and wherein, the first restrictor comprises the first transistor; Multiple first storage array, arranges in the mode arranged; Multiple first retainer, one that each first retainer is corresponding with multiple first storage array is electrically connected, multiple first retainer and the first restrictor are electrically connected, and wherein, each in multiple first retainer comprises: at least one transistor seconds; And logic gate, wherein, the grid of the output terminal of logic gate and at least one transistor seconds is electrically connected, and at least one of at least one input end of logic gate and at least one transistor seconds drains and be electrically connected; And multiple first sector switch, to be connected electrically in the first restrictor and multiple first retainer between corresponding one.
In other embodiments of the application, a kind of memory circuit, comprising: the first restrictor, is configured to, and at sensing, control the first electric current flowing through the first restrictor, wherein, the first restrictor comprises the first transistor; Multiple first storage array, arrange in the mode of row, wherein, each in multiple first storage array comprises at least one storage unit, and at least one storage unit comprises read port, and read port is configured to, at sensing, if read port conducting, then the first electric current can flow through read port, and has voltage drop at read port two ends; Multiple first retainer, one that each first retainer is corresponding with multiple first storage array is electrically connected, wherein, each in multiple first retainer comprises: at least one transistor seconds, wherein, at least one source terminal of at least one transistor seconds and the first restrictor are electrically connected; And logic gate, wherein, the grid of the output terminal of logic gate and at least one transistor seconds is electrically connected, and at least one of at least one input end of logic gate and at least one transistor seconds drains and be electrically connected; And multiple first sector switch, to be connected electrically in the first restrictor and multiple first retainer between corresponding one.
Discuss the parts of multiple embodiment above, make the various aspects that the present invention may be better understood for those of ordinary skill in the art.It will be understood by those skilled in the art that can use easily to design based on the present invention or revise other for perform with herein process and the structure introducing the identical object of embodiment and/or realize same advantage.Those of ordinary skill in the art should also be appreciated that this equivalent constructions does not deviate from the spirit and scope of the present invention, and when not deviating from the spirit and scope of the present invention, can carry out multiple change, replacement and change.
Claims (18)
1. a memory circuit, comprising:
Multiple first storage array, arranges in the mode arranged;
Multiple first retainer, one that each described first retainer is corresponding with described multiple first storage array is electrically connected;
First restrictor, is electrically connected with described multiple first retainer, and described first restrictor shared by described multiple first retainer; And
Multiple first sector switch, each described first sector switch to be electrically connected in described first restrictor and described multiple first retainer between corresponding one;
Wherein, each in described multiple first storage array comprises: at least one storage unit, at least one storage unit described comprises read port, described read port is configured to, at sensing, if described read port conducting, then the first electric current can flow through described read port, and there is voltage drop at described read port two ends, described first restrictor configuration is, at described sensing, controls the second electric current flowing through described first restrictor, and at described sensing, described first electric current is greater than described second electric current.
2. memory circuit according to claim 1, wherein, at least one between sensing and precharge phase, access in described multiple first storage array, and conducting corresponds to the sector switch of accessed storage array.
3. memory circuit according to claim 1, wherein, described first restrictor comprises: the first transistor, each in described multiple first sector switch comprises PMOS transistor or nmos pass transistor, and the channel length of described the first transistor is greater than the channel length of described PMOS transistor or nmos pass transistor.
4. memory circuit according to claim 1, wherein, each in described multiple first retainer comprises:
At least one transistor seconds; And
Logic gate, wherein, the output terminal of described logic gate and the grid of at least one transistor seconds described are electrically connected, and at least one of at least one input end of described logic gate and at least one transistor seconds described drains and be electrically connected.
5. memory circuit according to claim 4, wherein, described logic gate is NOT door, and at least one transistor seconds described comprises single transistor.
6. memory circuit according to claim 4, wherein, described logic gate is NAND door, and at least one transistor seconds described comprises two or more transistor.
7. memory circuit according to claim 1, comprises further:
Multiple second storage array, arranges in the mode arranged;
Multiple second retainer, one that each described second retainer is corresponding with described multiple second storage array is electrically connected;
Multiple second sector switch, each described second sector switch to be electrically connected in described first restrictor and described multiple second retainer between corresponding one;
First row switch, is connected electrically between described first restrictor and described multiple first sector switch; And
Secondary series switch, is connected electrically between described first restrictor and described multiple second sector switch.
8. memory circuit according to claim 7, wherein, described first restrictor comprises the first transistor, and described first row switch comprises transistor seconds, and the channel length of described transistor seconds is less than the channel length of described the first transistor.
9. a memory circuit, comprising:
First restrictor, wherein, described first restrictor comprises the first transistor;
Multiple first storage array, arranges in the mode arranged;
Multiple first retainer, one that each described first retainer is corresponding with described multiple first storage array is electrically connected, described multiple first retainer and described first restrictor are electrically connected, and wherein, each in described multiple first retainer comprises:
At least one transistor seconds; And
Logic gate, wherein, the output terminal of described logic gate and the grid of at least one transistor seconds described are electrically connected, and at least one of at least one input end of described logic gate and at least one transistor seconds described drains and be electrically connected; And
Multiple first sector switch, to be connected electrically in described first restrictor and described multiple first retainer between corresponding one;
Wherein, each in described multiple first storage array comprises: at least one storage unit, at least one storage unit described comprises read port, described read port is configured to, at sensing, if described read port conducting, then the first electric current can flow through described read port, and there is voltage drop at described read port two ends, described first restrictor configuration is, at described sensing, controls the second electric current flowing through described first restrictor, and at described sensing, described first electric current is greater than described second electric current.
10. memory circuit according to claim 9, wherein, at least one between sensing and precharge phase, access in described multiple first storage array, and conducting corresponds to the sector switch of accessed storage array.
11. memory circuits according to claim 9, wherein, described first sector switch comprises PMOS transistor or nmos pass transistor, and the channel length of described the first transistor is greater than the channel length of described PMOS transistor or nmos pass transistor.
12. memory circuits according to claim 9, comprise further:
Multiple second storage array, arranges in the mode arranged;
Multiple second retainer, one that each described second retainer is corresponding with described multiple second storage array is electrically connected;
Multiple second sector switch, each described second sector switch to be connected electrically in described first restrictor and described multiple second retainer between corresponding one;
First row switch, is connected electrically between described first restrictor and described multiple first sector switch; And
Secondary series switch, is connected electrically between described first restrictor and described multiple second sector switch.
13. memory circuits according to claim 12, wherein, described first row switch comprises third transistor, and the channel length of described third transistor is greater than the channel length of described the first transistor.
14. 1 kinds of memory circuits, comprising:
First restrictor, is configured to, and at sensing, control the first electric current flowing through described first restrictor, wherein, described first restrictor comprises the first transistor;
Multiple first storage array, arrange in the mode of row, wherein, each in described multiple first storage array comprises at least one storage unit, and at least one storage unit described comprises read port, and described read port is configured to, at described sensing, if described read port conducting, then the first electric current can flow through described read port, and has voltage drop at described read port two ends;
Multiple first retainer, one that each described first retainer is corresponding with described multiple first storage array is electrically connected, and wherein, each in described multiple first retainer comprises:
At least one transistor seconds, wherein, at least one source terminal and described first restrictor of at least one transistor seconds described are electrically connected; And
Logic gate, wherein, the output terminal of described logic gate and the grid of at least one transistor seconds described are electrically connected, and at least one of at least one input end of described logic gate and at least one transistor seconds described drains and be electrically connected; And
Multiple first sector switch, to be connected electrically in described first restrictor and described multiple first retainer between corresponding one.
15. memory circuits according to claim 14, wherein, at least one between sensing and precharge phase, access in described multiple first storage array, and conducting correspond to the sector switch of accessed storage array.
16. memory circuits according to claim 14, wherein, described first sector switch comprises PMOS transistor or nmos pass transistor, and the channel length of described the first transistor is greater than the channel length of described PMOS transistor or nmos pass transistor.
17. memory circuits according to claim 14, wherein, described logic gate is NOT door, and at least one transistor seconds described comprises single transistor.
18. memory circuits according to claim 14, wherein, described logic gate is NAND door, and at least one transistor seconds described comprises two or more transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/025,668 US8406078B2 (en) | 2010-05-12 | 2011-02-11 | Memory circuits having a plurality of keepers |
| US13/025,668 | 2011-02-11 |
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| US9251864B2 (en) * | 2012-09-06 | 2016-02-02 | Infineon Technologies Ag | System and method for providing voltage supply protection in a memory device |
| CN103198860B (en) * | 2013-03-15 | 2015-12-09 | 清华大学 | A kind of RRAM write circuit |
| US10607692B2 (en) * | 2017-06-29 | 2020-03-31 | SK Hynix Inc. | Serializer and memory device including the same |
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| CN1199229A (en) * | 1997-03-31 | 1998-11-18 | 精工爱普生株式会社 | Low power memory including selective precharge circuit |
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| CN1199229A (en) * | 1997-03-31 | 1998-11-18 | 精工爱普生株式会社 | Low power memory including selective precharge circuit |
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