CN103198860A

CN103198860A - Resistive random access memory (RRAM) writing circuit

Info

Publication number: CN103198860A
Application number: CN2013100845728A
Authority: CN
Inventors: 于杰; 焦斌; 伍冬; 吴华强; 钱鹤
Original assignee: Tsinghua University
Current assignee: Beijing Xin Yi Science And Technology Ltds
Priority date: 2013-03-15
Filing date: 2013-03-15
Publication date: 2013-07-10
Anticipated expiration: 2033-03-15
Also published as: CN103198860B

Abstract

The invention provides a resistive random access memory (RRAM) writing circuit, comprising a storage unit array and a current limiting module, wherein the storage unit array comprises M rows and N lines of storage units; each storage unit comprises a resistor and a transistor; the drain electrode of each transistor is connected with a bit line through the corresponding resistor; the grid electrode of each transistor is connected with a word line; the source electrodes of each line of transistors are connected; the current limiting module comprises N current limiting transistors corresponding to the N lines of storage units; the drain electrodes of the current limiting transistors are connected with the source electrodes of the corresponding lines of storage units; the grid electrodes of the current limiting transistors are connected with current limiting voltage; and the source electrodes of the current limiting transistors are connected with a source line. The RRAM writing circuit provided by the invention limits current in the bit line in a setting process; and under the condition of not increasing area, a decoding circuit is simple in structure, and multi-bit data signals comprising '0' and '1' can be written in the decoding circuit in parallel.

Description

A kind of RRAM write circuit

Technical field

The present invention relates to the resistance-variable storing device design field, refer more particularly to a kind of RRAM write circuit.

Background technology

Resistance-variable storing device (RRAM) is because of its performance advantage in every respect, simple as memory cell structure, operating rate is fast, low in energy consumption, information keeps stablizing, have involatile and be easy to realize the integrated and many-valued storage of 3 D stereo etc., has become the research focus of storer.The resistance that becomes the resistance material in the resistance-variable storing device can change by the difference that its upper/lower electrode is applied voltage or electric current, presents low-resistance and high resistant two states, comes stored logic ' 0 ' and logic ' 1 ' with this two states.There is set (set) in write operation to resistive element and (reset) two processes that reset, and wherein set process is that the change resistance is become low resistive state by high-impedance state, and reseting procedure is that the change resistance is become high-impedance state by low resistive state.Having greatest problem in the write operation process at present is that set needs the added voltage of word line different with reseting procedure, otherwise namely the resistive material is not then needed by high resistant step-down resistance process need current limliting.This just makes the not only effect of a selector switch of word-line decoder also will supply to provide current-limiting function simultaneously.And design not only can increase the complexity that column decode circuitry designs like this, and feasible can not writing simultaneously comprises ' 0 ' and ' 1 ' multibit data signal.

Summary of the invention

The present invention one of is intended to solve the problems of the technologies described above at least to a certain extent or provides a kind of useful commerce to select at least.For this reason, one object of the present invention is to propose that a kind of have can current limliting, allows to write simultaneously the RRAM write circuit of multibit data signal.

RRAM write circuit according to the embodiment of the invention, comprise: memory cell array, described memory cell array comprises the capable N array storage unit of M, wherein each described storage unit comprises a resistance and a transistor, wherein, described transistor drain links to each other with bit line through described resistance, and described transistorized grid links to each other with the word line, and each is listed as described transistorized source electrode and links to each other; With the current limliting module, described current limliting module comprises the N corresponding with a N array storage unit current limliting transistor, described current limliting transistor drain links to each other with the source electrode of the described storage unit of respective column, and the transistorized grid of described current limliting connects current limliting voltage, and the transistorized source electrode of described current limliting links to each other with the source line.

The present invention proposes the RRAM write circuit of set process neutrality line current limliting, under the situation that does not increase area, make decoding circuit structure simple, and can be written in parallel to and comprise ' 0 ' and ' 1 ' multibit data signal.

Additional aspect of the present invention and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.

Description of drawings

Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment in conjunction with following accompanying drawing, wherein:

Fig. 1 is the RRAM write circuit of the embodiment of the invention and the structural representation of array;

Fig. 2 is the comparison diagram of the operating conditions curve of the embodiment of the invention and existing RRAM write circuit.

Embodiment

Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical or similar label is represented identical or similar elements or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, be intended to for explaining the present invention, and can not be interpreted as limitation of the present invention.

In description of the invention, it will be appreciated that, term " " center "; " vertically "; " laterally "; " length "; " width "; " thickness ", " on ", D score, " preceding ", " back ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", close the orientation of indications such as " counterclockwise " or position is based on orientation shown in the drawings or position relation, only be that the present invention for convenience of description and simplification are described, rather than device or the element of indication or hint indication must have specific orientation, with specific orientation structure and operation, therefore can not be interpreted as limitation of the present invention.

In addition, term " first ", " second " only are used for describing purpose, and can not be interpreted as indication or hint relative importance or the implicit quantity that indicates indicated technical characterictic.Thus, one or more these features can be expressed or impliedly be comprised to the feature that is limited with " first ", " second ".In description of the invention, the implication of " a plurality of " is two or more, unless clear and definite concrete restriction is arranged in addition.

In the present invention, unless clear and definite regulation and restriction are arranged in addition, broad understanding should be done in terms such as term " installation ", " linking to each other ", " connection ", " fixing ", for example, can be fixedly connected, also can be to removably connect, or connect integratedly; Can be mechanical connection, also can be to be electrically connected; Can be directly to link to each other, also can link to each other indirectly by intermediary, can be the connection of two element internals.For the ordinary skill in the art, can understand above-mentioned term concrete implication in the present invention as the case may be.

In the present invention, unless clear and definite regulation and restriction are arranged in addition, first feature second feature it " on " or D score can comprise that first and second features directly contact, can comprise that also first and second features are not directly contacts but by the contact of the additional features between them.And, first feature second feature " on ", " top " and " above " comprise first feature directly over second feature and oblique upper, or only represent that the first characteristic level height is higher than second feature.First feature second feature " under ", " below " and " below " comprise first feature under second feature and tiltedly, or only represent that the first characteristic level height is less than second feature.

The present invention proposes and a kind ofly add the current limliting module at bit line and replace word line voltage to switch the RRAM write circuit of metering function, the present invention can make that decoding circuit structure is simple, and can write simultaneously comprise ' 0 ' with ' 1 ' multibit data signal.

RRAM write circuit according to the embodiment of the invention comprises: memory cell array 100 and current limliting module 200.

Wherein, memory cell array 100 comprises the capable N array storage unit of M, and wherein each storage unit comprises a resistance and a transistor, wherein, transistor drain links to each other with bit line through resistance, and transistorized grid links to each other with the word line, and the source electrode of each rowed transistor links to each other.

Wherein current limliting module 200 comprises the N corresponding with a N array storage unit current limliting transistor, and the current limliting transistor drain links to each other with the source electrode of the storage unit of respective column, and the transistorized grid of current limliting connects current limliting voltage, and the transistorized source electrode of current limliting links to each other with the source line.

The transistorized metering function of set process need of RRAM storer, resistance after the resistive element set is according to the difference that flows through the resistive element size of current in the set process and difference, the more big resistive element low-resistance of the electric current that flows through resistance is more little, and the more little resistive element low-resistance of the electric current that flows through resistance is more big.According to transistor I-V characteristic as can be known, when transistor is operated in the saturation region, flowing through transistorized electric current will remain unchanged substantially, and finally maintain different current values according to the difference of magnitude of voltage on the grid.The transistorized principle of work of current limliting is utilized this specific character exactly, and is simultaneously again that word-line decoder is independent, makes word-line decoder tightly play the effect of decoding gating, thereby can realize that the multibyte data that comprises " 0 " and " 1 " writes.

The present invention proposes the RRAM write circuit of set process neutrality line current limliting, adding current limiting tube at bit line replaces word line voltage to switch the effect of current limliting, under the situation that does not increase area, make decoding circuit structure simple, and can be written in parallel to and comprise ' 0 ' and ' 1 ' multibit data signal.

As shown in Figure 2, dotted line is the simulation result that has increased the RRAM of current limliting module (being 1T1R+1T) of the present invention, and solid line is the simulation result of RRAM of the unlimited flow module (1T1R) of prior art.The former uses the current limiting tube current limliting, the latter uses the transistor current limliting in the 1T1R unit, as can be seen, at first both results are basic identical, that is to say on the bit line current limitation effect that the structure that adds current limiting tube and 1T1R structure are compared and can be reached identical, secondly write fashionablely when the multibit data signal that comprises ' 0 ' and ' 1 ' that according to the difference decision current limliting of input signal whether the structure that adds current limiting tube on the bit line can realize, really realize being written in parallel to of data, improved writing speed.Thereby and the current-limiting mode of the structure that generally adopts at present can only select to limit the full line unit because of it or select the full line unit all not the modes of current limliting can only realize entirely " 0 " data or write " 1 " data the time entirely.

In the description of this instructions, concrete feature, structure, material or characteristics that the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means in conjunction with this embodiment or example description are contained at least one embodiment of the present invention or the example.In this manual, the schematic statement to above-mentioned term not necessarily refers to identical embodiment or example.And concrete feature, structure, material or the characteristics of description can be with the suitable manner combination in any one or more embodiment or example.

Although illustrated and described embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, those of ordinary skill in the art can change above-described embodiment under the situation that does not break away from principle of the present invention and aim within the scope of the invention, modification, replacement and modification.

Claims

1. a RRAM write circuit is characterized in that, comprising:

Memory cell array, described memory cell array comprises the capable N array storage unit of M, wherein each described storage unit comprises a resistance and a transistor, wherein, described transistor drain links to each other with bit line through described resistance, described transistorized grid links to each other with the word line, and each is listed as described transistorized source electrode and links to each other; With

The current limliting module, described current limliting module comprises the N corresponding with a N array storage unit current limliting transistor, described current limliting transistor drain links to each other with the source electrode of the described storage unit of respective column, and the transistorized grid of described current limliting connects current limliting voltage, and the transistorized source electrode of described current limliting links to each other with the source line.