CN102629581A - TFT array substrate, liquid crystal display panel method for manufacturing the array substrate - Google Patents
TFT array substrate, liquid crystal display panel method for manufacturing the array substrate Download PDFInfo
- Publication number
- CN102629581A CN102629581A CN2011103050259A CN201110305025A CN102629581A CN 102629581 A CN102629581 A CN 102629581A CN 2011103050259 A CN2011103050259 A CN 2011103050259A CN 201110305025 A CN201110305025 A CN 201110305025A CN 102629581 A CN102629581 A CN 102629581A
- Authority
- CN
- China
- Prior art keywords
- array substrate
- active layer
- photoresist
- layer
- tft array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention, which relates to the liquid crystal display panel manufacturing field, discloses a thin film transistor (TFT) array substrate, a liquid crystal display panel method for manufacturing the array substrate, so that toppling of a space can be prevented and a display effect of a liquid crystal panel is improved. The method for manufacturing a TFT array substrate comprises the following steps that: an active layer is coated on a substrate provided with a gate line, a gate electrode and a gate insulating layer; a data metal layer is coated on the active layer and a data line, a source electrode, a drain electrode, a semiconductor active layer and a groove on the semiconductor active layer above the gate line are obtained by processing according to a composition process; a protective layer is formed on the data line, the source electrode and the drain electrode; and a pixel electrode layer connected with the drain electrode is formed on the protective layer. According to the invention, the TFT array substrate, the liquid crystal display panel the method for manufacturing the array substrate are applied to manufacturing of the liquid crystal display panel.
Description
Technical field
The present invention relates to display panels and make the field, relate in particular to a kind of tft array substrate, display panels and manufacturing method of array base plate.
Background technology
The display panels of TFT-LCD (Thin Film Transistor-Liquid Crystal Display, TFT LCD) is by two glass substrates up and down of box moulding and the liquid crystal layer of filling are therebetween constituted at present.
For control box is thick, generally adopt chock insulator matter to support, wherein, chock insulator matter mainly is placed in the non-transmission region of tft array substrate.
After chock insulator matter was placed, when liquid crystal panel received the external force extruding, the chock insulator matter that is positioned on the tft array substrate was toppled over easily, touched the alignment films on the tft array substrate after toppling over easily or was incorporated in the liquid crystal layer, and then influenced the display effect of liquid crystal panel.
Summary of the invention
The present invention provides a kind of tft array substrate, display panels and manufacturing method of array base plate, can prevent that chock insulator matter from toppling over, and has improved the display effect of liquid crystal panel.
For achieving the above object, the present invention adopts following technical scheme:
A kind of manufacturing approach of tft array substrate comprises:
On the substrate that is formed with grid line, grid, gate insulation layer, be coated with active layer;
On said active layer, be coated with data metal layer, obtain data wire, source electrode, drain electrode, semiconductor active layer and be positioned at the groove on the semiconductor active layer of said grid line top through the composition PROCESS FOR TREATMENT;
In said data wire, source electrode, drain electrode, form protective layer;
On said protective layer, form the pixel electrode layer that is connected with said drain electrode.
A kind of tft array substrate; Comprise: substrate; With the grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode, drain electrode, the protective layer that are positioned on the said substrate; And the pixel electrode layer that is connected with said drain electrode that is positioned at said protective layer top, the semiconductor active layer of said grid line top is provided with groove.
A kind of display panels; The tft array substrate and the color membrane substrates that comprise involutory shaping; Said tft array substrate is above-mentioned tft array substrate; Wherein, the chock insulator matter between said tft array substrate and the said color membrane substrates is positioned at the groove of the semiconductor active layer formation of said tft array substrate.
Tft array substrate provided by the invention, display panels and tft array substrate manufacturing approach; Utilize the composition technology that forms data wire, source electrode, drain electrode; Simultaneously on the semiconductor active layer above the grid line, form groove; So that the chock insulator matter between tft array substrate and the color membrane substrates is positioned in this groove, reach the purpose that prevents that chock insulator matter from toppling over, improve LCD panel display effect.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
A pixel region structural representation of the tft array substrate that Fig. 1 provides for the embodiment of the invention one;
Fig. 2 be Fig. 1 along A-A to the sectional structure sketch map;
The manufacturing approach schematic flow sheet of the tft array substrate that Fig. 3 provides for the embodiment of the invention two;
Tft array substrate structural representation in the manufacturing approach of the tft array substrate that Fig. 4 provides for the embodiment of the invention two behind the completing steps S301;
Tft array substrate structural representation in the manufacturing approach of the tft array substrate that Fig. 5 provides for the embodiment of the invention two behind the completing steps S302;
Tft array substrate structural representation in the manufacturing approach of the tft array substrate that Fig. 6 provides for the embodiment of the invention two behind the completing steps S303;
Tft array substrate structural representation in the manufacturing approach of the tft array substrate that Fig. 7 provides for the embodiment of the invention two behind the completing steps S304;
Tft array substrate structural representation in the manufacturing approach of the tft array substrate that Fig. 8 provides for the embodiment of the invention two behind the completing steps S305;
Tft array substrate structural representation in the manufacturing approach of the tft array substrate that Fig. 9 provides for the embodiment of the invention two behind the completing steps S306;
Tft array substrate structural representation in the manufacturing approach of the tft array substrate that Figure 10 provides for the embodiment of the invention two behind the completing steps S307;
Tft array substrate structural representation in the manufacturing approach of the tft array substrate that Figure 11 provides for the embodiment of the invention two behind the completing steps S308;
Tft array substrate structural representation in the manufacturing approach of the tft array substrate that Figure 12 provides for the embodiment of the invention two behind the completing steps S309;
Tft array substrate structural representation in the manufacturing approach of the tft array substrate that Figure 13 provides for the embodiment of the invention two behind the completing steps S310;
The structural representation of the display panels that Figure 14 provides for the embodiment of the invention three.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
Embodiment one
The tft array substrate that the embodiment of the invention provides, like Fig. 1, shown in Figure 2, Fig. 1 is the structural representation vertical view of a pixel region of tft array substrate, Fig. 2 be tft array substrate shown in Figure 1 along A-A to cutaway view.
This tft array substrate comprises: substrate 10; Be formed at grid line 11 and grid 12 on the substrate 10; Be formed at the gate insulation layer 20 on grid line 11 and the grid 12; Be formed at the semiconductor active layer 21 of gate insulation layer 20 tops, be formed at source electrode 13, drain electrode 14, the data wire 15 of semiconductor active layer 21 tops; Be positioned on the semiconductor active layer 21 of grid line 11 tops and have groove 18; In addition, above data wire 15, source electrode 13, drain electrode 14, also be formed with protective layer 19; In the zone that surrounds by data wire 15 and grid line 11 intersections, be formed with pixel electrode 16.This pixel electrode 16 can link to each other with drain electrode 14 through via hole 17, and grid 12, source electrode 13, drain electrode 14, semiconductor active layer 21 constitute TFT.
The tft array substrate that the embodiment of the invention provides; Be positioned on the semiconductor active layer 21 of grid line 11 tops and have groove structure; Can in follow-up display panels manufacture process, put into chock insulator matter; When keeping the liquid crystal panel box thick, can also prevent that chock insulator matter from toppling over, guaranteed the display effect of liquid crystal panel.
Embodiment two
Below through accompanying drawing 3～shown in Figure 13, the manufacturing approach of the tft array substrate that the embodiment of the invention is provided describes.Fig. 4～Figure 13 is the sectional position identical with Fig. 2 in the present embodiment.As shown in Figure 3, method step comprises:
S301, on glass substrate depositing metal layers, obtain grid line 11 and grid 12 through the composition PROCESS FOR TREATMENT.
As shown in Figure 4; Can use magnetically controlled sputter method, preparation one layer thickness is at
metal film layer to
on glass substrate 10.Metal material can adopt metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper usually, also can use the combining structure of above-mentioned different materials film.Then, with mask through exposure, development, etching, composition PROCESS FOR TREATMENT for the first time such as peel off, on certain zone of glass substrate 10, form many horizontal grid lines 11 and the grid that links to each other with grid line 12.
S302, on grid line 11 and grid 12, form gate insulation layer 20.
As shown in Figure 5; Can utilize chemical vapor deposition method (Plasma EnhancedChemical Vapor Deposition; PECVD) deposit thickness is
gate insulator 20 to
on grid line 11, grid 12; The material of gate insulation layer 20 is silicon nitride normally, also can use silica and silicon oxynitride etc.
S303, on gate insulation layer 20 coating active layer 41 (in the present embodiment, with the active layer that is called that at first is coated on the whole base plate, the part that this active layer is constituted TFT after etching is called semiconductor active layer).
As shown in Figure 6, can be that
metal-oxide film is as active layer 41 through sputtering method successive sedimentation thickness.
S304, on active layer 41 coating data metal layer 42.
As shown in Figure 7, can adopt with form grid line 11, grid 12 identical technologies are coated with data metal layer 42 on active layer 41.
S305, as shown in Figure 8, coating photoresist 45 on data metal layer 42.
S306, as shown in Figure 9 utilizes gray tone mask plate or 50 pairs of photoresists 45 of half-penetration type mask plate to make public, and the back of developing forms the complete reserve area of photoresist 451, photoresist half reserve area 452 and photoresist and removes the zone fully.Wherein, In pixel cell; The complete reserve area of photoresist 451 respective data lines 15, source electrode 13, drain electrode 14; The semiconductor active layer except that groove 18 of the corresponding grid lines of photoresist half reserve area 452 top, photoresist are removed the complete reserve area of photoresist and the zone outside photoresist half reserve area in the regional respective pixel unit fully, are positioned at the groove 18 of grid line 11 tops like pixel electrode, grid line and semiconductor active layer.
S307, utilize etching technics get rid of photoresist remove fully the zone data metal layer 42 and active layer 41, obtain structure shown in figure 10.
S308, utilize plasma ashing technology to get rid of the photoresist of photoresist half reserve area 452; Obtain structure shown in figure 11; The data metal layer 42 of exposing semiconductor active layer 21 tops (in the present embodiment; With the active layer that is called that at first is coated on the whole base plate, the part that this active layer is constituted TFT after etching is called semiconductor active layer).
S309, utilize etching technics to get rid of the data metal layer 42 of photoresist half reserve area 451, obtain structure shown in figure 12.
S310, peel off the photoresist 45 of the complete reserve area 451 of photoresist, structure shown in figure 13 obtains data wire 15, source electrode 13, drain electrode 14 and semiconductor active layer 21.In Figure 13, also be formed with the groove 18 on the semiconductor active layer 21 that is positioned at grid line 11 tops.
S311, in data wire 15, source electrode 13, drain electrode 14, form protective layer 19, obtain tft array substrate structure as shown in Figure 2.
S312, the pixel electrode layer 16 that formation is connected with drain electrode 14 on protective layer 19.
The tft array substrate manufacturing approach that the embodiment of the invention provides; Utilize the composition technology that forms data wire, source electrode, drain electrode; Simultaneously on the semiconductor active layer above the grid line, form groove; So that the chock insulator matter between tft array substrate and the color membrane substrates is positioned in this groove, prevent that chock insulator matter from toppling over, improve the purpose of LCD panel display effect.
In addition and since the groove on the semiconductor active layer be in manufacturing source, drain electrode by a composition technology gained, therefore do not increase extra manufacturing cost and operation.
Embodiment three
The display panels that the embodiment of the invention provides; Shown in figure 14; Comprise tft array substrate 80 and color membrane substrates 70 to synthesis type; And the tft array substrate of this tft array substrate 80 for providing in the foregoing description two, wherein, the chock insulator matter 60 between this tft array substrate 80 and the color membrane substrates 70 is positioned at the groove 18 of semiconductor active layer 41 formation of tft array substrate 80.
The display panels that the embodiment of the invention provides; Chock insulator matter between tft array substrate and the color membrane substrates is positioned in the groove of the semiconductor active layer formation above the grid line; When liquid crystal panel receives the external force extruding; Can prevent that chock insulator matter from toppling over the touching alignment films, thereby improve the display effect of liquid crystal panel.
The display panels that the embodiment of the invention provides; Chock insulator matter between tft array substrate and the color membrane substrates is positioned in the groove of the said semiconductor active layer formation above the grid line; When liquid crystal panel receives the external force extruding; Prevent that chock insulator matter from toppling over the touching alignment films, thereby improved the display effect of liquid crystal panel.
The above; Be merely embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technical staff who is familiar with the present technique field is in the technical scope that the present invention discloses; Can expect easily changing or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of said claim.
Claims (4)
1. the manufacturing approach of a tft array substrate is characterized in that, comprising:
On the substrate that is formed with grid line, grid, gate insulation layer, be coated with active layer;
On said active layer, be coated with data metal layer, obtain data wire, source electrode, drain electrode, semiconductor active layer and be positioned at the groove on the semiconductor active layer of said grid line top through the composition PROCESS FOR TREATMENT;
In said data wire, source electrode, drain electrode, form protective layer;
On said protective layer, form the pixel electrode layer that is connected with said drain electrode.
2. method according to claim 1; It is characterized in that; On said active layer, be coated with data metal layer, obtain data wire, source electrode, drain electrode, semiconductor active layer and the groove that is positioned on the semiconductor active layer of said grid line top comprises through the composition PROCESS FOR TREATMENT:
On said active layer, be coated with data metal layer;
On said data metal layer, be coated with photoresist;
Utilize gray tone mask plate or half-penetration type mask plate that said photoresist is made public, the back of developing forms the complete reserve area of photoresist, photoresist half reserve area and photoresist and removes the zone fully; Wherein, In pixel cell; The complete reserve area respective data lines of said photoresist, source electrode, drain electrode; The corresponding semiconductor active layer except that grooved area of said photoresist half reserve area, said photoresist are removed the complete reserve area of photoresist and the zone outside said photoresist half reserve area in the regional corresponding said pixel cell fully;
Utilize etching technics to get rid of data metal layer and active layer that said photoresist is removed the zone fully;
Utilize plasma ashing technology to get rid of the photoresist of said photoresist half reserve area;
Utilize etching technics to get rid of the data metal layer of said photoresist half reserve area;
Peel off the photoresist of the complete reserve area of said photoresist.
3. tft array substrate; Comprise: substrate; With the grid line, grid, gate insulation layer, semiconductor active layer, data wire, source electrode, drain electrode, the protective layer that are positioned on the said substrate; And the pixel electrode layer that is connected with said drain electrode that is positioned at said protective layer top, it is characterized in that the semiconductor active layer of said grid line top is provided with groove.
4. display panels; Comprise tft array substrate and color membrane substrates to synthesis type; It is characterized in that; Said tft array substrate is the described tft array substrate of claim 3, and wherein, the chock insulator matter between said tft array substrate and the said color membrane substrates is positioned at the groove of the semiconductor active layer formation of said tft array substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103050259A CN102629581A (en) | 2011-10-10 | 2011-10-10 | TFT array substrate, liquid crystal display panel method for manufacturing the array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103050259A CN102629581A (en) | 2011-10-10 | 2011-10-10 | TFT array substrate, liquid crystal display panel method for manufacturing the array substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102629581A true CN102629581A (en) | 2012-08-08 |
Family
ID=46587809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103050259A Pending CN102629581A (en) | 2011-10-10 | 2011-10-10 | TFT array substrate, liquid crystal display panel method for manufacturing the array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102629581A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016065851A1 (en) * | 2014-10-27 | 2016-05-06 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display device |
| CN107179641A (en) * | 2017-06-05 | 2017-09-19 | 深圳市华星光电技术有限公司 | A kind of array base palte and preparation method thereof, liquid crystal display panel |
| CN109659313A (en) * | 2018-11-12 | 2019-04-19 | 惠科股份有限公司 | A kind of array substrate, the production method of array substrate and display panel |
| US10824031B2 (en) | 2017-06-05 | 2020-11-03 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Manufacturing method of an array substrate comprising a source electrode, a drain electrode, and a pixel electrode that are configured to be directly exposed within a liquid crystal layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7557891B2 (en) * | 2004-04-30 | 2009-07-07 | Lg Display Co., Ltd. | Liquid crystal display device and method for fabricating the same |
| US7570338B2 (en) * | 2005-06-14 | 2009-08-04 | Lg Display Co., Ltd. | LCD panel and fabricating method with ball spacer within dummy source/drain electrode pattern and dummy semiconductor pattern over gate line for maintaining cell gap |
| CN101752319A (en) * | 2008-12-19 | 2010-06-23 | 京东方科技集团股份有限公司 | Manufacture method of thin film transistor liquid crystal display array substrate |
-
2011
- 2011-10-10 CN CN2011103050259A patent/CN102629581A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7557891B2 (en) * | 2004-04-30 | 2009-07-07 | Lg Display Co., Ltd. | Liquid crystal display device and method for fabricating the same |
| US7570338B2 (en) * | 2005-06-14 | 2009-08-04 | Lg Display Co., Ltd. | LCD panel and fabricating method with ball spacer within dummy source/drain electrode pattern and dummy semiconductor pattern over gate line for maintaining cell gap |
| CN101752319A (en) * | 2008-12-19 | 2010-06-23 | 京东方科技集团股份有限公司 | Manufacture method of thin film transistor liquid crystal display array substrate |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016065851A1 (en) * | 2014-10-27 | 2016-05-06 | 京东方科技集团股份有限公司 | Array substrate, display panel, and display device |
| US9897863B2 (en) | 2014-10-27 | 2018-02-20 | Boe Technology Group Co., Ltd. | Array substrate, display panel and display apparatus having recesses on data lines or gate lines |
| CN107179641A (en) * | 2017-06-05 | 2017-09-19 | 深圳市华星光电技术有限公司 | A kind of array base palte and preparation method thereof, liquid crystal display panel |
| WO2018223497A1 (en) * | 2017-06-05 | 2018-12-13 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and manufacturing method therefor, and liquid crystal display panel |
| US10824031B2 (en) | 2017-06-05 | 2020-11-03 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Manufacturing method of an array substrate comprising a source electrode, a drain electrode, and a pixel electrode that are configured to be directly exposed within a liquid crystal layer |
| CN109659313A (en) * | 2018-11-12 | 2019-04-19 | 惠科股份有限公司 | A kind of array substrate, the production method of array substrate and display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102629577A (en) | TFT array substrate and manufacturing method thereof and display device | |
| US11114474B2 (en) | Thin film transistor, manufacturing method thereof, array substrate, and display panel | |
| CN102629584B (en) | Array substrate and manufacturing method thereof and display device | |
| CN102629628A (en) | TFT array substrate and manufacturing method thereof and liquid crystal display | |
| CN102629579A (en) | Flexible TFT array substrate and manufacturing method thereof and display device | |
| CN102738007A (en) | Manufacturing method of thin film transistor and manufacturing method of array base plate | |
| CN103489918A (en) | Thin-film transistor, array substrate and manufacturing method thereof | |
| CN102023432A (en) | FFS type TFT-LCD array substrate and manufacturing method thereof | |
| US20090146151A1 (en) | Thin film transistor array substrate and method of manufacturing the same | |
| CN102651322A (en) | Thin film transistor and manufacturing method thereof, array substrate and display device | |
| CN103456746A (en) | Array substrate, manufacturing method thereof and display device | |
| CN104078470A (en) | Array substrate, producing method thereof, display device | |
| CN102629581A (en) | TFT array substrate, liquid crystal display panel method for manufacturing the array substrate | |
| EP2819155B1 (en) | Thin film transistor array substrate and producing method thereof | |
| CN103413782A (en) | Array substrate, method for manufacturing array substrate and display panel | |
| CN102569185A (en) | Array substrate, production method thereof and liquid crystal display | |
| CN101661908B (en) | Method for manufacturing array substrate of horizontal electric field type semi-permeable liquid crystal display device | |
| CN102723309B (en) | Array substrate and manufacturing method thereof as well as display device | |
| CN101414564B (en) | Method for manufacturing low-temperature polycrystalline silicon film transistor | |
| CN102629578A (en) | TFT array substrate and manufacturing method thereof and display device | |
| CN102819138A (en) | Array base plate and display device | |
| CN101393363A (en) | FFS type TFT-LCD array substrate structure and method for manufacturing same | |
| CN103441129A (en) | Array substrate, manufacturing method of array substrate and display device | |
| CN104091806A (en) | Array substrate, manufacturing method of array substrate and display panel of array substrate | |
| CN102629018A (en) | Color film substrate, thin film transistor (TFT) array substrate, manufacturing method thereof and liquid crystal display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120808 |