CN102624577A - Flow reproducing method and system thereof - Google Patents
Flow reproducing method and system thereof Download PDFInfo
- Publication number
- CN102624577A CN102624577A CN2011100335073A CN201110033507A CN102624577A CN 102624577 A CN102624577 A CN 102624577A CN 2011100335073 A CN2011100335073 A CN 2011100335073A CN 201110033507 A CN201110033507 A CN 201110033507A CN 102624577 A CN102624577 A CN 102624577A
- Authority
- CN
- China
- Prior art keywords
- bit stream
- buffer memory
- under test
- equipment under
- head
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000015654 memory Effects 0.000 claims abstract description 121
- 238000012360 testing method Methods 0.000 claims description 88
- 238000012544 monitoring process Methods 0.000 claims description 17
- 230000010365 information processing Effects 0.000 abstract description 2
- 230000006855 networking Effects 0.000 description 32
- 230000005540 biological transmission Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 238000011161 development Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
Images
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention is suitable for the information processing field and provides a flow reproducing method and a system thereof. The method comprises the following steps: collecting a bit stream sent to detected equipment in an original line; caching the collected bit stream, stopping bit stream cache after the information that the detected equipment is crashed is received, identifying the head of the cached bit stream and outputting the cached bit stream; receiving and storing the output bit stream; reading the bit stream from the head of the bit stream stored in a memory and caching the read bit stream; reading the bit stream from the head of the cached bit stream and returning the read bit stream to the original line. Through collecting and storing the bit stream which is sent to the detected equipment from the original line, when the detected equipment is crashed, network environment at that time can be reproduced, which is helpful for a network product developer to analyze a reason why a network product can cause the detected equipment to crash. Problems existing in the network product can be effectively solved.
Description
Technical field
The invention belongs to field of information processing, relate in particular to a kind of flow reproducting method and system.
Background technology
The existing network product generally need carry out alpha test and β test to networking products before listing.Alpha test is meant the close beta that networking products development company carries out networking products; β test is meant behind alpha test actual in routine duties these networking products that use of particular group of being organized each side by networking products development company; And require abnormal conditions that the user report networking products occur, propose to criticize suggestion, by networking products development company these networking products are made amendment then and perfect.
In the β of networking products test process, the most fatal problem is to cause the deadlock of equipment under test.After the deadlock, can not feed back the reason that causes equipment under test to crash with the phase-split network product, the problem that causes these networking products to exist can't solve, and influences the Time To Market of networking products.Therefore, the networking products developer urgently hopes can reproduce network environment at that time through a kind of method, helps to solve the problem that networking products occur, and shortens the Time To Market of networking products.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of flow reproducting method; Be intended to solve networking products in carrying out the β test process; Can not feed back the reason that causes equipment under test to crash with the phase-split network product; The problem that causes networking products to exist can't solve, and influences the problem of networking products Time To Market.
The embodiment of the invention is achieved in that a kind of flow reproducting method, said method comprising the steps of:
Gather the bit stream that sends to equipment under test in the original circuit;
The bit stream of the said collection of buffer memory, and after the information that receives the equipment under test deadlock, stop the buffer memory of bit stream, identify the head of the bit stream of buffer memory, export the bit stream of said buffer memory;
Receive and store the bit stream of said output;
Begin to read said bit stream from the head of the bit stream of said storage, and the said bit stream that reads is carried out buffer memory;
Begin to read said bit stream from the head of the bit stream of buffer memory, the said bit stream that reads is returned to original circuit.
A kind of flow storage means is characterized in that, said method comprising the steps of:
Gather the bit stream that sends to equipment under test in the original circuit;
Whether the monitoring equipment under test crashes, and when monitoring the equipment under test deadlock, exports said equipment under test deadlock information;
The bit stream of the said collection of buffer memory, and after the information that the equipment under test that receives said output crashes, stop the buffer memory of bit stream, identify the head of the bit stream of buffer memory, export the bit stream of said buffer memory;
Receive and store the bit stream of said output.
Another purpose of the embodiment of the invention is to provide a kind of flow playback system, and said system comprises:
Data acquisition unit is used for gathering the bit stream that original circuit sends to equipment under test;
Cache element is used for the bit stream of the said collection of buffer memory, and after the information that receives the equipment under test deadlock, stops the buffer memory of bit stream, identifies the head of the bit stream of buffer memory, exports the bit stream of said buffer memory;
Memory cell is used to receive and store the bit stream of said output;
Read memory cell is used for beginning to read said bit stream from the head of the bit stream of said storage, and the said bit stream that reads is carried out buffer memory;
Read buffer unit, be used for beginning to read said bit stream, the said bit stream that reads is returned to original circuit from the head of the bit stream of buffer memory.
A kind of flow storage system is characterized in that, said system comprises:
Data acquisition unit is used for gathering the bit stream that original circuit sends to equipment under test;
Whether monitoring means is used to monitor equipment under test and crashes, and when monitoring the equipment under test deadlock, exports said equipment under test deadlock information;
Cache element is used for the bit stream of the said collection of buffer memory, and after the information that the equipment under test that receives said output crashes, stops the buffer memory of bit stream, identifies the head of the bit stream of buffer memory, exports the bit stream of said buffer memory;
Memory cell is used to receive and store the bit stream of said output.
In embodiments of the present invention; Through gathering the bit stream that sends to equipment under test in the original circuit, preserve and reproduce said bit stream, make when networking products cause equipment under test to crash in carrying out the β test process; Can simulation reconstruction network environment at that time; Help the networking products developer to cause the reason that equipment under test crashes to be analyzed, effectively solve the problem that networking products exist, shorten the Time To Market of networking products networking products.
Description of drawings
Fig. 1 is the realization flow figure of the flow reproducting method that provides of the embodiment of the invention one;
Fig. 2 is the particular flow sheet of the flow buffering that provides of the embodiment of the invention one;
Fig. 3 is the particular flow sheet of the flow storage that provides of the embodiment of the invention one;
Fig. 4 is the structured flowchart of the flow playback system that provides of the embodiment of the invention two.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In the embodiment of the invention through gathering the bit stream that sends to equipment under test in the original circuit; Preserve and reproduce said bit stream; Make when networking products cause equipment under test to crash in carrying out the β test process, can simulation reconstruction network environment at that time, help the networking products developer to cause the reason that equipment under test crashes to be analyzed to networking products; Effectively solve the problem that networking products exist, shorten the Time To Market of networking products.
For technical scheme of the present invention is described, describe through specific embodiment below.
Embodiment one:
Fig. 1 shows the realization flow of the flow reproducting method that the embodiment of the invention one provides, and details are as follows for this procedure:
In step S101, gather the bit stream that sends to equipment under test in the original circuit.
In the present embodiment, can adopt corresponding collector, for example:, then gather through optical splitter if original circuit adopts Optical Fiber Transmission according to the transmission medium of original circuit; If original circuit adopts cable transmission, but then pass through the electric mouthpiece collection of mirror image.The trunk roads of collector and original circuit are compatible, during data in gathering original circuit, the data that collect exported from bypass, and the transfer of data that does not influence trunk roads is given equipment under test.Wherein, said data are bit stream.
As one embodiment of the present of invention,, so just need to gather and preserve the bit stream of N bar circuit if equipment under test has N port that is used to receive bit stream.But because the deadlock of equipment under test generally is the influence of being received data, so unidirectional data are only gathered and preserved to present embodiment, promptly original circuit sends to the data of equipment under test, is not then gathered and is preserved by the data that equipment under test sends.
In step S102, the bit stream of the said collection of buffer memory, and after the information that receives the equipment under test deadlock, stop the buffer memory of bit stream, and identify the head of the bit stream of buffer memory, export the bit stream of said buffer memory.
In the present embodiment, concrete steps such as Fig. 2 of buffer memory bit stream are said:
In step S201, write the bit stream of said collection, and after the information that receives the equipment under test deadlock, stop to write of bit stream, the head of the bit stream that sign writes;
In step S202, the bit stream of buffer memory said write;
In step S203, begin to read said bit stream from the head of the bit stream of said buffer memory, and export the said bit stream that reads.
In the present embodiment, the bit stream of gathering is write a circulating line in the direction of the clock and carry out buffer memory.If after this circulating line buffer memory is full, also have new bit stream to write, then cover the bit stream that writes at first, be the bit stream of up-to-date a period of time with the bit stream that guarantees institute's buffer memory.And after the information that receives the equipment under test deadlock; Stop to write of bit stream; Sign has write the head of the bit stream of buffer memory; Begin to read said bit stream from the head of the bit stream of said buffer memory, and export the said bit stream that reads, guarantee when flow reproduces, can accurately simulate network environment at that time.
In step S103, receive and store the bit stream of said output.
In the present embodiment, the concrete steps of stored bits stream are as shown in Figure 3:
In step S301, write the bit stream that receives;
In step S302, the bit stream of storage said write.
In the present embodiment, the mode of storage is including, but not limited to hard disk or electric board.
In step S104, begin to read bit stream from the head of the bit stream of said storage, and the said bit stream that reads is carried out buffer memory;
In step S105, begin to read said bit stream from the head of the bit stream of buffer memory, the said bit stream that reads is returned to original circuit.
In the present embodiment, begin to read bit stream from the head of the bit stream of said storage, and the said bit stream that reads is carried out buffer memory, begin to read said bit stream, the said bit stream that reads is returned to original circuit from the head of the bit stream of buffer memory.Can return to original circuit again behind the whole buffer memorys of bit stream with storage earlier, perhaps buffer memory limit in limit returns to former circuit.Begin to read said bit stream from the head of bit stream of sign, to guarantee when flow reproduces, accurately simulating network environment at that time.
As another embodiment of the present invention, in order to grasp the state of equipment under test in real time, said flow reproducting method also comprises the steps:
Whether the monitoring equipment under test crashes in real time, when monitoring the equipment under test deadlock, exports said equipment under test deadlock information.
Embodiment two:
Fig. 4 shows the structure of the flow playback system that the embodiment of the invention two provides, and for the ease of explanation, only shows the part relevant with the embodiment of the invention.This flow playback system can be the software unit that is built in the information terminal, the unit that hardware cell or software and hardware combine.
This flow playback system comprises data acquisition unit 41, cache element 42, memory cell 43, read memory cell 44 and reads cache element 45.The concrete function of each unit is following:
Data acquisition unit 41 is used for gathering the bit stream that original circuit sends to equipment under test, and said bit stream is sent to cache element 42.
In the present embodiment, data acquisition unit can adopt corresponding collector according to the transmission medium of original circuit, for example: if original circuit adopts Optical Fiber Transmission, then gather through optical splitter; If original circuit adopts cable transmission, but then pass through the electric mouthpiece collection of mirror image.The collector of data acquisition unit and the trunk roads of original circuit are compatible, and when gathering the original line circuit-switched data, the transfer of data that does not influence trunk roads is given equipment under test.Wherein, said data are bit stream, and data acquisition unit sends to cache element through bypass with said bit stream after in collecting original circuit, sending to the bit stream of equipment under test.
As one embodiment of the present of invention,, so just need to gather and preserve the bit stream of N bar circuit if equipment under test has N port that is used to receive bit stream.But because the deadlock of equipment under test generally is the influence of being received data, so unidirectional data are only gathered and preserved to present embodiment, promptly original circuit sends to the data of equipment under test, is not then gathered and is preserved by the data that equipment under test sends.
Cache element 42 is used for the said bit stream of buffer memory, and after receiving the information that equipment under test crashes, stops the buffer memory of bit stream, identifies the head of the bit stream of buffer memory, and the bit stream of said buffer memory is sent to memory cell 43.Wherein, said cache element 42 also comprises write cache module 421, cache module 422 and reads cache module 423.The concrete function of each module is following:
Write cache module 421 is used for the bit stream write cache module 422 that receives, and after receiving the information that equipment under test crashes, stops to write of bit stream, identifies the head of the bit stream in the write cache module 422;
Cache module 422 is used for the bit stream that buffer memory writes;
Read cache module 423, be used for beginning to read said bit stream, and the said bit stream that reads is sent to memory cell 43 from the head of the bit stream of cache module 422 buffer memorys.
In the present embodiment, cache element after receiving the bit stream that data acquisition unit sends, through the write cache module in the cache element with in the cache module in this bit stream write cache unit.Wherein, cache module is a looped pipeline, and the write cache module writes bit stream in the direction of the clock; Behind the full ring bit stream of storage; Write as new bit stream, then cover the bit stream that writes at first, with buffer memory in the assurance cache module is the bit stream of up-to-date a period of time.
As another embodiment of the present invention; Whether said flow storage device also comprises a monitoring means, be used for monitoring in real time equipment under test and crash, when monitoring the equipment under test deadlock; The information that equipment under test is crashed sends to cache element; Cache element stops the buffer memory of bit stream, and identifies the head of the bit stream of buffer memory after the information that receives the equipment under test deadlock; The head of reading cache module bit stream of buffer memory from cache module begins said bit stream is sent to memory cell, to guarantee when flow reproduces, accurately simulating network environment at that time.
Memory cell 43 is used for receiving and storing said bit stream.Wherein, said memory cell 43 also comprises writes memory module 431 and memory module 432, and the concrete function of each module is following:
Write memory module 431, be used for the bit stream that receives is write memory module 432;
Memory module 432 is used to store said bit stream.
In the present embodiment, memory cell is after receiving the bit stream that cache element sends, through writing memory module with in the memory module in this bit stream write storage unit in the memory cell.Wherein, said memory module can be hard disk or electric board etc.
The head of the bit stream that read memory cell 44 is stored from memory cell 43 begins to read bit stream, and the said bit stream that reads is sent to cache element 42.
In the present embodiment; The head of the bit stream of storing in the memory module of read memory cell from memory cell begins to read bit stream; And the said bit stream that reads sent to cache element, till all bit streams of in memory module, storing have read.
The head of reading cache element 45 bit stream of buffer memory from cache element 42 begins to read bit stream, and the said bit stream that reads is returned to original circuit.
In the present embodiment, cache element after receiving the bit stream that read memory cell sends, through through the write cache module in the cache element with the cache module in this bit stream write cache unit.Wherein, Cache module is a looped pipeline; The write cache module writes bit stream in the direction of the clock; After all bit streams were written to cache module, the head of reading the bit stream of buffer memory in the cache module of cache element from cache element began to read bit stream, and the said bit stream that reads is returned to original circuit.
In embodiments of the present invention; Through gathering the bit stream that sends to equipment under test in the original circuit, preserve and reproduce said bit stream, make when networking products cause equipment under test to crash in carrying out the β test process; Can simulation reconstruction network environment at that time; Help the networking products developer to cause the reason that equipment under test crashes to be analyzed, effectively solve the problem that networking products exist, shorten the Time To Market of networking products networking products.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a flow reproducting method is characterized in that, said method comprising the steps of:
Gather the bit stream that sends to equipment under test in the original circuit;
The bit stream of the said collection of buffer memory, and after the information that receives the equipment under test deadlock, stop the buffer memory of bit stream, identify the head of the bit stream of buffer memory, export the bit stream of said buffer memory;
Receive and store the bit stream of said output;
Begin to read said bit stream from the head of the bit stream of said storage, and the said bit stream that reads is carried out buffer memory;
Begin to read said bit stream from the head of the bit stream of buffer memory, the said bit stream that reads is returned to original circuit.
2. the method for claim 1 is characterized in that, said method also comprises the steps:
Whether the monitoring equipment under test crashes, and when monitoring the equipment under test deadlock, exports said equipment under test deadlock information.
3. the method for claim 1 is characterized in that, the bit stream of the said collection of said buffer memory; And after the information that receives the equipment under test deadlock; Stop the buffer memory of bit stream, the head of the bit stream of sign buffer memory, the step of exporting the bit stream of said buffer memory is specially:
Write the bit stream of said collection, and after the information that receives the equipment under test deadlock, stop to write of bit stream, the head of the bit stream that sign writes;
The bit stream of buffer memory said write;
Begin to read said bit stream from the head of the bit stream of said buffer memory, and export the bit stream of said buffer memory.
4. a flow storage means is characterized in that, said method comprising the steps of:
Gather the bit stream that sends to equipment under test in the original circuit;
Whether the monitoring equipment under test crashes, and when monitoring the equipment under test deadlock, exports said equipment under test deadlock information;
The bit stream of the said collection of buffer memory, and after the information that the equipment under test that receives said output crashes, stop the buffer memory of bit stream, identify the head of the bit stream of buffer memory, export the bit stream of said buffer memory;
Receive and store the bit stream of said output.
5. method as claimed in claim 4 is characterized in that, the bit stream of the said collection of said buffer memory; And after the information that receives the equipment under test deadlock; Stop the buffer memory of bit stream, the head of the bit stream of sign buffer memory, the step of exporting the bit stream of said buffer memory is specially:
Write the bit stream of said collection, and after the information that receives the equipment under test deadlock, stop to write of bit stream, the head of the bit stream that sign writes;
The bit stream of buffer memory said write;
Begin to read said bit stream from the head of the bit stream of said buffer memory, and export the bit stream of said buffer memory.
6. a flow playback system is characterized in that, said system comprises:
Data acquisition unit is used for gathering the bit stream that original circuit sends to equipment under test;
Cache element is used for the bit stream of the said collection of buffer memory, and after the information that receives the equipment under test deadlock, stops the buffer memory of bit stream, identifies the head of the bit stream of buffer memory, exports the bit stream of said buffer memory;
Memory cell is used to receive and store the bit stream of said output;
Read memory cell is used for beginning to read said bit stream from the head of the bit stream of said storage, and the said bit stream that reads is carried out buffer memory;
Read buffer unit, be used for beginning to read said bit stream, the said bit stream that reads is returned to original circuit from the head of the bit stream of buffer memory.
7. system as claimed in claim 6 is characterized in that, said system also comprises:
Whether monitoring means is used to monitor equipment under test and crashes, and when monitoring the equipment under test deadlock, the information that said equipment under test is crashed sends to said cache element.
8. system as claimed in claim 6 is characterized in that, said cache element comprises write cache module, cache module and reads cache module.
Said write cache module is used for the bit stream write cache module that receives, and after receiving the information that equipment under test crashes, stops to write of bit stream, identifies the head of the bit stream in the write cache module;
Said cache module is used for the bit stream that buffer memory writes;
The said cache module of reading is used for beginning to read said bit stream from the head of the bit stream of cache module buffer memory, and the said bit stream that reads is stored in the memory.
9. a flow storage system is characterized in that, said system comprises:
Data acquisition unit is used for gathering the bit stream that original circuit sends to equipment under test;
Whether monitoring means is used to monitor equipment under test and crashes, and when monitoring the equipment under test deadlock, exports said equipment under test deadlock information;
Cache element is used for the bit stream of the said collection of buffer memory, and after the information that the equipment under test that receives said output crashes, stops the buffer memory of bit stream, identifies the head of the bit stream of buffer memory, exports the bit stream of said buffer memory;
Memory cell is used to receive and store the bit stream of said output.
10. system as claimed in claim 9 is characterized in that, said cache element comprises write cache module, cache module and reads cache module.
Said write cache module is used for the bit stream write cache module that receives, and after receiving the information that equipment under test crashes, stops to write of bit stream, identifies the head of the bit stream in the write cache module;
Said cache module is used for the bit stream that buffer memory writes;
The said cache module of reading is used for beginning to read said bit stream from the head of the bit stream of cache module buffer memory, and the said bit stream that reads is stored in the memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110033507.3A CN102624577B (en) | 2011-01-30 | 2011-01-30 | Flow reproducing method and system thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110033507.3A CN102624577B (en) | 2011-01-30 | 2011-01-30 | Flow reproducing method and system thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102624577A true CN102624577A (en) | 2012-08-01 |
| CN102624577B CN102624577B (en) | 2014-12-31 |
Family
ID=46564268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110033507.3A Active CN102624577B (en) | 2011-01-30 | 2011-01-30 | Flow reproducing method and system thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102624577B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104079435A (en) * | 2014-07-10 | 2014-10-01 | 南威软件股份有限公司 | Method for regenerating Ethernet flow |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101140507A (en) * | 2007-09-24 | 2008-03-12 | 北京大学 | Data readback method and apparatus |
| US20080240576A1 (en) * | 2007-03-29 | 2008-10-02 | Samsung Electronics Co., Ltd. | Method of and apparatus for detecting error in image data stream |
| CN101360015A (en) * | 2008-09-02 | 2009-02-04 | 北京星网锐捷网络技术有限公司 | Method, system and apparatus for test network appliance |
-
2011
- 2011-01-30 CN CN201110033507.3A patent/CN102624577B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080240576A1 (en) * | 2007-03-29 | 2008-10-02 | Samsung Electronics Co., Ltd. | Method of and apparatus for detecting error in image data stream |
| CN101140507A (en) * | 2007-09-24 | 2008-03-12 | 北京大学 | Data readback method and apparatus |
| CN101360015A (en) * | 2008-09-02 | 2009-02-04 | 北京星网锐捷网络技术有限公司 | Method, system and apparatus for test network appliance |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104079435A (en) * | 2014-07-10 | 2014-10-01 | 南威软件股份有限公司 | Method for regenerating Ethernet flow |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102624577B (en) | 2014-12-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102761466B (en) | IEEE (Institute of Electrical and Electronics Engineers) 1394 bus data record processing system and method | |
| US20060259822A1 (en) | Profiling system | |
| CN101710270B (en) | High-speed mass memory based on flash memory and chip data management method | |
| CN102930615B (en) | Method, device and system for recording train operation status data | |
| CN103037203B (en) | A kind of index restoration methods based on block storage and device | |
| CN103455424A (en) | Dynamic internal memory leakage detecting method and device based on VxWorks operation system | |
| CN105681783B (en) | Audio, video data acquisition interface circuit design method | |
| CN101751327B (en) | Method for tracing embedded processor debugging | |
| CN115687228B (en) | PCIe bus-based satellite-borne solid-state storage system and method | |
| CN207115383U (en) | A kind of storage system based on FPGA+EMMC storage arrays | |
| CN101594305B (en) | Method and device for processing messages | |
| CN107967118A (en) | A kind of method and apparatus realized hard disc data high speed dump and checked | |
| CN103605833A (en) | Method and device for simulating performance of storage array system | |
| CN102624577B (en) | Flow reproducing method and system thereof | |
| CN109902000A (en) | Speed change multichannel debugs tracing system, method, equipment and storage medium | |
| CN201726415U (en) | IEC61850 communication-oriented network wave recorder | |
| CN101998135A (en) | System for collecting and playing mobile television signal and control method | |
| US20210124810A1 (en) | Method of debugging hardware and firmware of data storage | |
| CN111628996A (en) | Electronic data communication method and system based on Internet of things | |
| CN101883046A (en) | Data cache architecture applied to EPON terminal system | |
| CN114556283B (en) | Method and device for data writing, consistency checking and reading | |
| CN104243197B (en) | Data transmission method, system and virtual memory gateway | |
| CN203422841U (en) | Electricity utilization information acquisition system based on WSN (wireless sensor network) and light communication | |
| CN105701060A (en) | FPGA-based high-speed real-time data recording system | |
| CN201338640Y (en) | Railway system reverse playback processing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: SHENZHEN SEMPTIAN TECHNOLOGIES?CO.,?LTD. Free format text: FORMER NAME: SEMPTIAN TECHNOLOGY CO., LTD. |
|
| CP03 | Change of name, title or address |
Address after: 518000, Guangdong Shenzhen hi tech Southern District, Haitian two road 14, software industry base, 5D block, 7, Nanshan District Patentee after: SEMPTIAN TECHNOLOGIES LTD. Address before: 518000 Guangdong Province, Shenzhen city Nanshan District District Science Park Road, building 6 storey main building Jiada Lang Patentee before: Semptian Technologies Ltd. |
|
| C56 | Change in the name or address of the patentee | ||
| CP03 | Change of name, title or address |
Address after: 518000 Guangdong city of Shenzhen province Nanshan District Guangdong streets two Haitian Road No. 14, block 5D 8 layer software industry base Patentee after: Shenzhen Hengyang Data Co.,Ltd. Address before: 518000, Guangdong Shenzhen hi tech Southern District, Haitian two road 14, software industry base, 5D block, 7, Nanshan District Patentee before: SEMPTIAN TECHNOLOGIES LTD. |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Flow reproducing method and system thereof Effective date of registration: 20170713 Granted publication date: 20141231 Pledgee: Bank of Beijing Limited by Share Ltd. Shenzhen branch Pledgor: Shenzhen Hengyang Data Co.,Ltd. Registration number: 2017990000630 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20190520 Granted publication date: 20141231 Pledgee: Bank of Beijing Limited by Share Ltd. Shenzhen branch Pledgor: Shenzhen Hengyang Data Co.,Ltd. Registration number: 2017990000630 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A method and a flow reconstruction system Effective date of registration: 20200826 Granted publication date: 20141231 Pledgee: Bank of Beijing Limited by Share Ltd. Shenzhen branch Pledgor: Shenzhen Hengyang Data Co.,Ltd. Registration number: Y2020980005382 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20210803 Granted publication date: 20141231 Pledgee: Bank of Beijing Limited by Share Ltd. Shenzhen branch Pledgor: Shenzhen Hengyang Data Co.,Ltd. Registration number: Y2020980005382 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A flow reproduction method and system Effective date of registration: 20210816 Granted publication date: 20141231 Pledgee: Bank of Beijing Limited by Share Ltd. Shenzhen branch Pledgor: Shenzhen Hengyang Data Co.,Ltd. Registration number: Y2021440020082 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20141231 Pledgee: Bank of Beijing Limited by Share Ltd. Shenzhen branch Pledgor: Shenzhen Hengyang Data Co.,Ltd. Registration number: Y2021440020082 |