CN102624475B - A kind of realization method and system for improving 1588 frequency retrieval performances - Google Patents
A kind of realization method and system for improving 1588 frequency retrieval performances Download PDFInfo
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Abstract
The invention discloses a kind of method and system for improving 1588 frequency retrieval performances, it is related to network communication field, methods described to include：Judge the change of 1588 timestamps and local 1588 timestamp of master clock, obtain network delay change PDV shakes, eliminate after PDV shake after filtering, the phase place change of adjustment VCXO obtain and export the 1588 frequency retrieval clock signals for following master clock；Monitor the variable quantity of the PDV shakes；If the variable quantity of the PDV shakes is more than predetermined value, then interrupt the 1588 frequency retrieval clock signal and export the PDV wobble variations amount more than the 1588 frequency retrieval clock signal before predetermined value, if the PDV wobble variations amount is less than predetermined value, the treatment output for continuing step A follows 1588 frequency retrieval clock signals of master clock.Present invention ensure that the stability of 1588 frequency retrievals, improves frequency retrieval quality.
Description
Technical Field
The invention relates to the field of network communication, in particular to a method and a system for improving 1588 frequency recovery performance.
Background
With the rapid development of 3G networks, 1588 time synchronization protocol gets more and more attention and application in communication networks. The 1588 protocol is a network time synchronization protocol, and has time synchronization performance of a sub-microsecond level, good carrier transplantation capability and penetration capability of penetrating a non-1588 network. Home and abroad operators continuously use 1588 protocol to perform time synchronization, and gradually replace GPS (Global Positioning System) to perform time synchronization.
1588 besides having strong time synchronization function, it also has frequency recovery capability. 1588 frequency recovery is widely used in non-clocked networks, penetrating microwaves, traditional routers and switches, DWDM (Dense wavelength division Multiplexing) and OTN (Optical Transport Network). In recent years, the 1588 frequency recovery function has been developed and applied to a great extent, and becomes a great characteristic of the 1588 function, and is also an advantage in the 1588 application.
Fig. 1 is a diagram of a common 1588 frequency recovery device provided in the prior art, and as shown in fig. 1, 1588 frequency recovery mainly eliminates network transmission PDV (packet delay variation) jitter by determining changes of a 1588 timestamp of a master clock and a local 1588 timestamp, and adjusts phase variation of a voltage-controlled crystal oscillator to follow the frequency of the master clock through functions such as filtering, so as to achieve a function of performing frequency recovery by using 1588.
The traditional 1588 frequency recovery is easily affected by PDV jitter, and when the PDV jitter is too large, the quality of the recovered frequency is poor, and even the frequency jitter and the frequency drift cannot meet the standard requirements of ITU (international telecommunications Union, international telecommunication Union) and the like.
Disclosure of Invention
The invention aims to provide a realization method and a system for improving 1588 frequency recovery performance, which can better solve the problem of reduced quality of 1588 frequency recovery caused by overlarge PDV jitter in the 1588 frequency recovery process.
According to an aspect of the present invention, there is provided an implementation method for improving 1588 frequency recovery performance, where the method includes:
A. judging the change of a 1588 timestamp of a master clock and the change of a local 1588 timestamp to obtain network delay change PDV jitter, eliminating the PDV jitter, filtering, adjusting the phase change of a voltage-controlled crystal oscillator to obtain and output a 1588 frequency recovery clock signal following the master clock;
B. monitoring the variation of the PDV jitter;
C. if the variation of the PDV jitter is larger than a preset value, interrupting the 1588 frequency recovery clock signal and outputting the 1588 frequency recovery clock signal before the PDV jitter variation is larger than the preset value, and if the PDV jitter variation is smaller than the preset value, continuing the processing of the step A and outputting a 1588 frequency recovery clock signal following the main clock.
Wherein, step B also includes before:
the 1588 frequency recovery clock signal is input to a clock phase-locked loop through a signal output switch;
the PDV dither is input to a control module.
Wherein the step C comprises:
if the variation of the PDV jitter is larger than a preset value, the clock signal of the 1588 frequency recovery is not input into a clock phase-locked loop, and the clock phase-locked loop is forced to enter a clock holding state;
and if the variation of the PDV jitter is smaller than a preset value, controlling the clock signal of the 1588 frequency recovery to be input into a clock phase-locked loop, and controlling the clock phase-locked loop to enter a clock tracking state.
Wherein, the step of forcing the clock phase-locked loop to enter the clock holding state further comprises:
the clock phase-locked loop keeps outputting a 1588 frequency recovery clock signal before the PDV jitter variation processed by the clock phase-locked loop is larger than a preset value.
Wherein, the step of controlling the clock phase-locked loop to enter the clock tracking state further comprises:
and the clock phase-locked loop locks the 1588 frequency recovery clock signal and outputs the 1588 frequency recovery clock signal processed by the clock phase-locked loop.
According to another aspect of the present invention, there is provided a system for improving 1588 frequency recovery performance, the system comprising:
the recovery device is used for judging the change of a 1588 timestamp of the main clock and a local 1588 timestamp to obtain network delay change PDV jitter, filtering and adjusting the phase change of the voltage-controlled crystal oscillator after the PDV jitter is eliminated to obtain and output a 1588 frequency recovery clock signal following the main clock;
the control module is used for monitoring the variation of the PDV jitter and controlling the states of a switch of the signal output switch and a clock phase-locked loop according to the variation of the PDV jitter;
the signal output switch is used for cutting off the clock signal of the 1588 frequency recovery to be input into the clock phase-locked loop when the variation of the PDV jitter is larger than a preset value and outputting the clock signal of the 1588 frequency recovery to the clock phase-locked loop when the variation of the PDV jitter is smaller than the preset value according to the control of the control module;
and the clock phase-locked loop is used for outputting a 1588 frequency recovery clock signal processed by the clock phase-locked loop when the PDV jitter variation is larger than a preset value and outputting the processed 1588 frequency recovery clock signal when the PDV jitter variation is smaller than the preset value according to the control of the control module.
Wherein,
the control module is further used for cutting off the signal output switch when the PDV jitter variation is larger than a preset value, forcing the clock phase-locked loop to enter a clock holding state, and opening the signal output switch and controlling the clock phase-locked loop to enter a clock tracking state when the PDV jitter variation is smaller than the preset value.
Wherein,
and the clock phase-locked loop is also used for keeping outputting a 1588 frequency recovery clock signal before the PDV jitter variation processed by the clock phase-locked loop is larger than a preset value after entering a clock holding state.
Wherein,
and the clock phase-locked loop is also used for locking the 1588 frequency recovery clock signal after entering a clock tracking state and outputting the 1588 frequency recovery clock signal processed by the clock phase-locked loop.
Wherein the recovery apparatus further comprises:
the PDV analysis module is used for judging the change of a 1588 timestamp of the master clock and a local 1588 timestamp to obtain a clock signal containing PDV jitter;
the time phase discriminator is used for eliminating PDV jitter of the clock signal;
the time filter is used for filtering the clock signal without PDV jitter;
and the voltage-controlled crystal oscillator is used for adjusting the phase change of the filtered clock signal and generating a 1588 frequency recovery clock signal following the main clock.
Compared with the prior art, the invention has the beneficial effects that: the stability of 1588 frequency recovery is ensured, and the frequency recovery quality is improved.
Drawings
Fig. 1 is a diagram of a conventional 1588 frequency recovery device provided by the prior art;
fig. 2 is a schematic diagram of an implementation method for improving 1588 frequency recovery performance according to an embodiment of the present invention;
fig. 3 is a flowchart of an implementation method for improving 1588 frequency recovery performance according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a system for improving 1588 frequency recovery performance according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, and it should be understood that the preferred embodiments described below are only for the purpose of illustrating and explaining the present invention, and are not to be construed as limiting the present invention.
The invention adds a control module, a clock phase-locked loop and a signal output switch on the basis of the existing 1588 frequency recovery device. The conventional 1588 frequency recovery device comprises a PDV analysis module, a time phase discriminator, a time filter and a voltage-controlled crystal oscillator. A clock signal which is output by the PDV analysis module and contains PDV jitter is input to the control module, and a clock signal which is output by the voltage-controlled crystal oscillator and is recovered by 1588 frequency is input to the clock phase-locked loop through the signal output switch. The control module monitors PDV jitter forwarded by the 1588 message in real time, cuts off 1588 frequency recovery when the PDV jitter is found to be large, and forces the clock phase-locked loop to enter a clock holding state.
A clock phase locked loop is a device that achieves clock synchronization. The clock synchronization effect is directly related to whether the communication system can normally communicate. The working principle of the clock phase-locked loop is that the frequency phases of a received reference clock and an output clock are compared to obtain a difference value to control the output frequency of the clock phase-locked loop so as to realize the consistency of the frequency of a reference clock source and the frequency of the clock output by the clock phase-locked loop.
According to current international regulations, a clock phase-locked loop must have a free state, a fast acquisition state, a locked state (tracking state), a hold state, and an out-of-lock state. The free state is the working state of the clock phase-locked loop when the reference clock source is not locked; the fast capture state is a working state when the clock phase-locked loop starts to track a clock signal of a reference clock source; the locking state is that the clock phase-locked loop enters the locking state when in the fast capture state and if the output clock frequency of the clock phase-locked loop is close to the reference clock frequency, so as to realize the synchronization of the input reference clock signal and the clock signal output by the clock phase-locked loop; when the reference clock signal of the input clock phase-locked loop is lost, the numerical value output by the filter forming the phase-locked loop maintains the numerical value output by the last filter before the reference clock signal is not lost so as to maintain the frequency value output by the clock phase-locked loop when the external reference signal is lost; the out-of-lock state is an operating state in which the clock phase locked loop cannot lock the reference clock in the tracking state due to deterioration of the clock signal of the external reference clock source or the like, and new parameters are reset so that the new reference clock can be locked again.
Fig. 2 is a schematic diagram of an implementation method for improving 1588 frequency recovery performance according to an embodiment of the present invention, as shown in fig. 2, the method includes:
step S201, judging the change of the 1588 timestamp of the main clock and the local 1588 timestamp to obtain network delay change PDV jitter, eliminating the PDV jitter, filtering, adjusting the phase change of the voltage-controlled crystal oscillator to obtain and output a 1588 frequency recovery clock signal following the main clock.
Step S202, monitoring the variation of the PDV jitter.
And the 1588 frequency recovery clock signal is input into a clock phase-locked loop through a signal output switch, and the PDV jitter is input into a control module. A control module monitors the amount of change in the PDV jitter.
Step S203, if the variation of the PDV jitter is greater than a predetermined value, interrupting the 1588 frequency recovery clock signal and outputting the 1588 frequency recovery clock signal before the PDV jitter variation is greater than the predetermined value, and if the PDV jitter variation is smaller than the predetermined value, continuing the processing of step a and outputting a 1588 frequency recovery clock signal following the master clock.
Specifically, if the variation of the PDV jitter is greater than a predetermined value, the clock signal recovered by the 1588 frequency is not input to the clock phase-locked loop, and the clock phase-locked loop is forced to enter a clock holding state; and if the variation of the PDV jitter is smaller than a preset value, controlling the clock signal of the 1588 frequency recovery to be input into a clock phase-locked loop, and controlling the clock phase-locked loop to enter a clock tracking state. And after the forced clock phase-locked loop enters a clock holding state, the 1588 frequency recovery clock signal before the PDV jitter variation processed by the forced clock phase-locked loop is larger than a preset value is kept and output. And after the control clock phase-locked loop enters a clock tracking state, the 1588 frequency recovery clock signal is locked and the 1588 frequency recovery clock signal processed by the clock phase-locked loop is output.
Fig. 3 is a flowchart of an implementation method for improving 1588 frequency recovery performance according to an embodiment of the present invention, and as shown in fig. 3, the method includes the following steps:
step S301, configuring a clock signal for locking 1588 frequency recovery output.
And the clock signal output by the 1588 frequency recovery is configured and locked by the clock phase-locked loop control configuration module.
And step S302, outputting the 1588 frequency recovery clock to a clock phase-locked loop through a switch control circuit.
The PDV analysis module judges the change of the 1588 timestamp of the master clock and the local 1588 timestamp, after PDV jitter is eliminated, the phase change of the voltage-controlled crystal oscillator is adjusted through the functions of filtering and the like, and finally, a clock signal which is recovered along with the 1588 frequency of the master clock is output. 1588 frequency recovery is prior art and is not described here.
1588 the frequency recovery clock output is output to the clock phase-locked loop through the signal output switch, and the clock phase-locked loop locks the clock signal and outputs the clock signal to the outside.
In step S303, the amount of shake variation is determined.
And the PDV jitter detection unit of the control module is used for monitoring the PDV jitter change of the message with the frequency recovery of 1588 in real time. When the PDV jitter variation is larger than the predetermined value, step S304 is performed, otherwise step S306 is performed.
And step S304, closing the clock with the 1588 frequency recovered and outputting the clock to a clock phase-locked loop.
And when the PDV jitter detection unit detects that the PDV jitter is larger than a preset value, the control module cuts off the signal output switch, and closes the 1588 frequency recovered clock signal recovered by the prior art and outputs the clock signal to the clock phase-locked loop.
In step S305, the clock phase locked loop enters a clock holding state.
When the PDV jitter detection unit detects that the PDV jitter is greater than the predetermined value, the control module controls the clock phase-locked loop to enter a clock holding state, and then executes step S309.
Step S306, determine whether the clock signal recovered by the 1588 frequency is input to the clock phase-locked loop.
And if the clock signal recovered by the 1588 frequency is not input to the clock phase-locked loop, namely the signal output switch closes the clock signal recovered by the 1588 frequency and inputs the clock phase-locked loop, executing the step S307, otherwise executing the step S303.
In step S307, the clock signal with the recovered 1588 frequency is output to a clock phase-locked loop.
And under the condition that the PDV jitter detection unit detects that the PDV jitter variation is smaller than a preset value and the 1588 frequency recovered clock signal is not output to the clock phase-locked loop, the control module opens the signal output switch to control the 1588 frequency recovered clock recovered by the prior art to be output to the clock phase-locked loop.
In step S308, the clock phase-locked loop enters a locked state.
And under the condition that the PDV jitter variation is smaller than the preset value, the control module controls the clock phase-locked loop to relock the clock signal output by the 1588 frequency recovery, enters a locking state and executes the step S309.
In step S309, the clock phase-locked loop outputs the signal processed by the clock phase-locked loop.
The clock phase-locked loop outputs the 1588 frequency-recovered clock signal processed by the clock phase-locked loop. If the clock phase-locked loop is in a locked state, the clock phase-locked loop processes a clock signal input by the existing recovery device and output by 1588 frequency recovery of the main clock; and if the clock phase-locked loop is in a holding state, the clock phase-locked loop processes the clock signal input by the existing recovery device and output by the 1588 frequency recovery before the PDV jitter variation is larger than the preset value, and outputs the processed clock signal output by the 1588 frequency recovery.
Fig. 4 is a schematic structural diagram of a system for improving 1588 frequency recovery performance according to an embodiment of the present invention, and as shown in fig. 4, the system includes a recovery device, a control module, a signal output switch, and a clock phase-locked loop.
The recovery device is used for judging the change of a 1588 timestamp (master clock time information) of a master clock and the change of a local 1588 timestamp (local time information), obtaining network delay change PDV jitter, eliminating the PDV jitter, filtering, adjusting the phase change of a voltage-controlled crystal oscillator, obtaining and outputting a 1588 frequency recovery clock signal following the master clock. The recovery device comprises a PDV analysis module, a time phase discriminator, a time filter and a voltage-controlled crystal oscillator. The PDV analysis module is used for judging the change of a 1588 timestamp of the master clock and a local 1588 timestamp to obtain a clock signal containing PDV jitter; the time phase discriminator is used for eliminating PDV jitter of the clock signal; the time filter is used for filtering the clock signal without PDV jitter; and the voltage-controlled crystal oscillator is used for adjusting the phase change of the filtered clock signal and generating a 1588 frequency recovery clock signal following the main clock.
The control module is used for monitoring the variation of the PDV jitter and controlling the switch of the signal output switch. The control module comprises a PDV jitter detection unit which is responsible for detecting PDV jitter of the 1588 frequency recovery message and is mainly responsible for controlling a phase-locked loop to lock a clock signal output by 1588 frequency recovery and clock maintenance. The control module controls the state of the switch of the signal output switch and the clock phase-locked loop according to the PDV jitter variation. When the PDV jitter variation is larger than a preset value, the control module closes the signal output switch and forces the clock phase-locked loop to enter a clock holding state, and when the PDV jitter variation is smaller than the preset value, the control module opens the signal output switch and controls the clock phase-locked loop to enter a clock tracking state.
And the signal output switch is used for judging whether the clock signal with the 1588 frequency recovery is output to the clock phase-locked loop or not. And the signal output switch cuts off the clock signal of the 1588 frequency recovery from being input to the clock phase-locked loop when the variation of the PDV jitter is larger than a preset value and outputs the clock signal of the 1588 frequency recovery to the clock phase-locked loop when the variation of the PDV jitter is smaller than the preset value according to the instruction of the control module.
The clock phase-locked loop is used for outputting a 1588 frequency recovery clock signal processed by the clock phase-locked loop when the PDV jitter variation is larger than a preset value and outputting the 1588 frequency recovery clock signal processed by the clock phase-locked loop when the PDV jitter variation is smaller than the preset value according to the control of the control module. After the clock phase-locked loop enters a clock holding state, a 1588 frequency recovery clock signal before PDV jitter variation processed by the clock phase-locked loop is larger than a preset value is kept output; and after the clock phase-locked loop enters a clock tracking state, locking the 1588 frequency recovery clock signal and outputting the 1588 frequency recovery clock signal processed by the clock phase-locked loop.
In summary, the invention controls the clock phase-locked loop to enter the clock holding state by detecting the PDV jitter variation, and further controls whether the 1588 frequency recovery output is input to the clock phase-locked loop, thereby ensuring the stability of 1588 frequency recovery and improving the frequency recovery quality.
Although the present invention has been described in detail hereinabove, the present invention is not limited thereto, and various modifications can be made by those skilled in the art in light of the principle of the present invention. Thus, modifications made in accordance with the principles of the present invention should be understood to fall within the scope of the present invention.
Claims (10)
1. An implementation method for improving 1588 frequency recovery performance, comprising:
A. judging the change of a 1588 timestamp of a master clock and the change of a local 1588 timestamp to obtain network delay change PDV jitter, eliminating the PDV jitter, filtering, adjusting the phase change of a voltage-controlled crystal oscillator to obtain and output a 1588 frequency recovery clock signal following the master clock;
B. monitoring the variation of the PDV jitter during the period of obtaining and outputting a 1588 frequency recovery clock signal following the main clock;
C. if the variation of the PDV jitter is larger than a preset value, interrupting the 1588 frequency recovery clock signal and outputting the 1588 frequency recovery clock signal before the PDV jitter variation is larger than the preset value;
D. and if the PDV jitter variation is smaller than a preset value, outputting the 1588 frequency recovery clock signal following the master clock to a clock phase-locked loop for processing, and outputting the 1588 frequency recovery clock signal processed by the phase-locked loop.
2. The method of claim 1, wherein step B is preceded by:
the 1588 frequency recovery clock signal is input to a clock phase-locked loop through a signal output switch;
the PDV dither is input to a control module.
3. The method of claim 2, wherein step C comprises:
if the variation of the PDV jitter is larger than a preset value, the clock signal of the 1588 frequency recovery is not input into a clock phase-locked loop, and the clock phase-locked loop is forced to enter a clock holding state;
and if the variation of the PDV jitter is smaller than a preset value, controlling the clock signal of the 1588 frequency recovery to be input into a clock phase-locked loop, and controlling the clock phase-locked loop to enter a clock tracking state.
4. The method of claim 3, wherein said step of forcing the clock phase locked loop to enter a clock hold state further comprises:
the clock phase-locked loop keeps outputting a 1588 frequency recovery clock signal before the PDV jitter variation processed by the clock phase-locked loop is larger than a preset value.
5. The method of claim 3, wherein the step of controlling the clock phase locked loop to enter the clock tracking state further comprises:
and the clock phase-locked loop locks the 1588 frequency recovery clock signal and outputs the 1588 frequency recovery clock signal processed by the clock phase-locked loop.
6. A system for improving 1588 frequency recovery performance, said system comprising:
the recovery device is used for judging the change of a 1588 timestamp of the main clock and a local 1588 timestamp to obtain network delay change PDV jitter, filtering and adjusting the phase change of the voltage-controlled crystal oscillator after the PDV jitter is eliminated to obtain and output a 1588 frequency recovery clock signal following the main clock;
the control module is used for monitoring the variation of the PDV jitter during the period of obtaining and outputting a 1588 frequency recovery clock signal following a master clock, and controlling the states of a switch of a 1588 frequency recovery clock signal output switch and a clock phase-locked loop according to the variation of the PDV jitter;
the signal output switch is used for cutting off the clock signal of the 1588 frequency recovery to be input to the clock phase-locked loop when the variation of the PDV jitter is larger than a preset value according to the control of the control module; when the PDV jitter variation is smaller than a preset value, outputting the 1588 frequency recovery clock signal to a clock phase-locked loop;
the clock phase-locked loop is used for outputting a 1588 frequency recovery clock signal processed by the clock phase-locked loop when the PDV jitter variation is larger than a preset value according to the control of the control module; and when the PDV jitter variation is smaller than a preset value, processing the 1588 frequency recovery clock signal from the signal output switch, and outputting the processed 1588 frequency recovery clock signal.
7. The system of claim 6,
the control module is further used for cutting off the signal output switch when the PDV jitter variation is larger than a preset value, forcing the clock phase-locked loop to enter a clock holding state, and opening the signal output switch and controlling the clock phase-locked loop to enter a clock tracking state when the PDV jitter variation is smaller than the preset value.
8. The system of claim 7,
and the clock phase-locked loop is also used for keeping outputting a 1588 frequency recovery clock signal before the PDV jitter variation processed by the clock phase-locked loop is larger than a preset value after entering a clock holding state.
9. The system of claim 8,
and the clock phase-locked loop is also used for locking the 1588 frequency recovery clock signal after entering a clock tracking state and outputting the 1588 frequency recovery clock signal processed by the clock phase-locked loop.
10. The system according to any one of claims 6 to 9, wherein the recovery means further comprises:
the PDV analysis module is used for judging the change of a 1588 timestamp of the master clock and a local 1588 timestamp to obtain a clock signal containing PDV jitter;
the time phase discriminator is used for eliminating PDV jitter of the clock signal;
the time filter is used for filtering the clock signal without PDV jitter;
and the voltage-controlled crystal oscillator is used for adjusting the phase change of the filtered clock signal and generating a 1588 frequency recovery clock signal following the main clock.
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| CN101083523B (en) * | 2007-07-27 | 2010-08-11 | 华南理工大学 | Method and device for realizing integrated time stamp clock synchronous phase-locked loop |
| CN101222288B (en) * | 2008-02-01 | 2011-07-20 | 华为技术有限公司 | IP network transmission method, system and equipment automatically adapting network jitter |
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| CN101083523B (en) * | 2007-07-27 | 2010-08-11 | 华南理工大学 | Method and device for realizing integrated time stamp clock synchronous phase-locked loop |
| CN101222288B (en) * | 2008-02-01 | 2011-07-20 | 华为技术有限公司 | IP network transmission method, system and equipment automatically adapting network jitter |
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