CN102623426B - Semiconductor packaging method - Google Patents
Semiconductor packaging method Download PDFInfo
- Publication number
- CN102623426B CN102623426B CN201210094779.9A CN201210094779A CN102623426B CN 102623426 B CN102623426 B CN 102623426B CN 201210094779 A CN201210094779 A CN 201210094779A CN 102623426 B CN102623426 B CN 102623426B
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- China
- Prior art keywords
- keyset
- receiving space
- conducting medium
- chip
- weld pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses a semiconductor packaging method including: providing an adapter plate of which an upper surface forms a sunk receiving space; providing a chip provided with a plurality of welding pads, arranging an adhesive layer on one side of the chip where the welding pads are, and adhering the chip to a bottom wall of the receiving space through the adhesive layer; forming through holes which penetrate the adapter plate and are communicated with the receiving space, on the adapter plate; arranging conductive mediums in the through holes and on a lower surface of the adapter plate, electrically connecting the welding pads and the conductive mediums, and forming a plurality of metal embosses on the lower surface of the adapter plate, and the metal embosses having pitches larger than the pitches of the plurality of welding pads and being electrically connected to the conductive mediums. By arranged the receiving space capable of receiving the chip on the adapter plate, the process difficulty of the adapter plate packaging is reduced and further the production cost is reduced.
Description
Technical field
The invention belongs to field of semiconductor manufacture technology, particularly relate to a kind of method for packaging semiconductor.
Background technology
Along with the development of semiconductor technology, the function of one single chip is from strength to strength, but more and more less to the dimensional requirement of chip, and the I/O quantity of unit are is also mutually deserved more and more, and the appearance of keyset solves this problem.
In prior art, normally on keyset, form through hole by silicon through hole technology, and the circuit that reroutes in the front of keyset, reroute circuit at the back side, and make the salient point matched with pcb board weld pad size, to solve and PCB incompatibility problem.
But, in existing this keyset encapsulation technology, due to the via process difficulty of keyset, cause keyset can not be blocked up, in order to ensure its performance, usually adopting interim pressing (Temporary bonding) technique keyset and a temporary base to be pressed together, then carrying out ensuing processing procedure, peeled off by temporary base on keyset after having encapsulated, technique is more complicated and cost is higher again.
Summary of the invention
The object of the present invention is to provide a kind of method for packaging semiconductor, it, by arranging the receiving space that can hold chip on keyset, reduces the technology difficulty of keyset encapsulation.
For solving an above-mentioned goal of the invention, the invention provides a kind of method for packaging semiconductor, the method comprises the following steps:
One keyset is provided, forms the receiving space of depression from described keyset upper surface;
There is provided a chip, which is provided with multiple weld pad, the one side being provided with weld pad at described chip arranges adhesion coating, and is bonded in by described adhesion coating on the diapire of described receiving space by described chip;
Described keyset is formed and runs through described keyset and the through hole be communicated with described receiving space;
In described through hole and described keyset lower surface conducting medium is set, described weld pad and described conducting medium are electrically connected, and are greater than the metal salient point of described multiple weld pad pitch in multiple pitches that described keyset lower surface is formed and described conducting medium is electrically connected.
As a further improvement on the present invention, " in described through hole, to arrange conducting medium " front also comprises:
Described through-hole wall and described keyset lower surface form insulating barrier;
Run through described adhesion coating, expose described weld pad.
As a further improvement on the present invention, " and form the multiple arrangement density be electrically connected with described conducting medium at described keyset lower surface be less than described multiple weld pad and arrange the metal salient point of density " specifically comprises:
Described conducting medium is formed a welding resisting layer;
On the welding resisting layer of described keyset lower surface, forming section exposes the opening of described conducting medium;
Form the multiple arrangement density be electrically connected with described conducting medium to be over said opening less than described multiple weld pad and to arrange the metal salient point of density.
As a further improvement on the present invention, described " formed on described keyset and run through described keyset and the through hole be communicated with described receiving space " step specifically comprises:
Formed in described keyset upper and lower surface and run through described keyset and multiple through holes of the described multiple bond pad locations of coupling be communicated with described receiving space.
Compared with prior art, the present invention, by arranging the receiving space that can hold chip on keyset, reduces the technology difficulty of keyset encapsulation, and then reduces production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of the keyset of an embodiment of the present invention encapsulating structure;
Fig. 2 is the structural representation being formed with the keyset of receiving space of an embodiment of the present invention encapsulating structure;
Fig. 3 is the structural representation in the chip of an embodiment of the present invention encapsulating structure is contained on keyset receiving space;
Fig. 4 is the keyset being formed with through hole of an embodiment of the present invention encapsulating structure and the structural representation coordinated of chip;
In this invention one execution mode encapsulating structure of Fig. 5, keyset is formed with insulating barrier in through hole and the structural representation coordinated with chip;
Fig. 6 is in an embodiment of the present invention encapsulating structure, keyset is formed with insulating barrier, conducting medium and redistribution lines road floor in through hole and the structural representation coordinated with chip;
Fig. 7 is in an embodiment of the present invention encapsulating structure shown in Fig. 6, and the redistribution lines road floor of keyset forms take precautions against drought floor the structural representation coordinated with chip;
Fig. 8 is in an embodiment of the present invention encapsulating structure shown in Fig. 7, and keyset makes the metal salient point be connected with redistribution lines road floor and the structural representation coordinated with chip;
Fig. 9 is the structural representation that an embodiment of the present invention encapsulating structure has encapsulated;
Figure 10 is the flow chart of the method for packaging semiconductor of an embodiment of the present invention.
Embodiment
Describe the present invention below with reference to embodiment shown in the drawings.But these execution modes do not limit the present invention, the structure that those of ordinary skill in the art makes according to these execution modes, method or conversion functionally are all included in protection scope of the present invention.
Ginseng Fig. 1 to Fig. 9, introduces an execution mode of semiconductor package of the present invention.This encapsulating structure comprises keyset 10, chip 20." chip 20 " mentioned here can comprise passive device, integrated circuit (IC) chip etc.
On the upper surface 100a of this keyset, depression has receiving space 11, and chip 20 is arranged in receiving space 11.On described keyset, the lower surface opposing with described keyset upper surface is formed and runs through this keyset 10 and the through hole 12 be communicated with this receiving space 11, in this through hole 12 and described keyset lower surface be provided with conducting medium 14.
In the present embodiment, the rectangular in cross-section shape of receiving space 11.In the execution mode that other is replaced, the cross section of this receiving space 11 also can be trapezoidal shape.That is, receiving space 11 mentioned here can comprise one, two and even the more receiving space interconnected, like this, semiconductor package provided by the invention can encapsulate the chip of more than, to meet the package requirements of multiple integrated chip.
The one side of described chip 20 is provided with multiple weld pad 22, simultaneously, this face is also provided with adhesion coating 21, and chip 20 is relative fixing with described keyset 10 by adhesion coating 21, and chip 20 is electrically connected by weld pad 22 and the conducting medium 14 be arranged in through hole 12.The benefit done like this is, chip 20 is directly fixed in the receiving space 11 of keyset 10 by adhesion coating 21, avoids and chip 20 is encapsulated the step that injecting glue is fixing again after the receiving space 11 of keyset 10, simplify technological process.And, encapsulate relative to the keyset 10 not arranging receiving space 11, this encapsulating structure volume provided by the invention is less, more adapts to following lightening package requirements, and the chip 20 encapsulated is not vulnerable to the impact of external environment, can improve the yield of encapsulation.
In the present embodiment, this semiconductor package also comprises insulating barrier 13, and on the inwall that this insulating barrier 13 is formed at through hole 12 and keyset 10 lower surface 100b, preferably, described conducting medium 14 is formed on this insulating barrier 13.
Described conducting medium 14 is also formed with welding resisting layer 15.Welding resisting layer 15 is provided with the opening that part exposes conducting medium 14, the multiple metal salient points 16 be electrically connected with conducting medium 14 are provided with by these openings, for connecting external pcb board 30, preferably, described opening is formed on described welding resisting layer 15 by the mode of photoetching.The pitch of the plurality of metal salient point is greater than the pitch of multiple weld pad, to solve the matching problem of chip and sequent surface attachment process.Preferably, described pitch refers to the spacing of the center line of a weld pad or metal salient point to adjacent welding-pad or metal salient point center line.
As preferred embodiment, multiple through hole is provided with in present embodiment, each through hole 12 runs through diapire and the keyset 10 lower surface 100b of described receiving space 11, and the position at described receiving space diapire of each through hole corresponds to the weld pad matched with this lead to the hole site.By such setting, fit in described conducting medium 14 and can be set to the shortest, with reduce encapsulate size, reduce the power consumption produced by conducting medium 14, and the present invention does not need to make redistribution lines road floor in the both sides of keyset 10, reduce process complexity, and then reduce production cost.
Coordinate with reference to Figure 10, introduce an embodiment of the method for packing of semiconductor package of the present invention, the method specifically comprises the following steps:
S1, provide a keyset 10, by photoetching, etch the receiving space 11 forming depression from keyset 10 upper surface.The material of this keyset 10 can be selected from the semiconductor technology baseplate material well known to those of ordinary skill in the art such as silicon, glass.Then, desired thickness is thinned to this keyset 10.In the present embodiment, to make the receiving space 11 of square-section by lithography: be first coated with one deck positive photoresist on keyset 10, and through pre-designed mask plate (not shown), the one side scribbling photoresist is exposed, in developer solution, the photoresist through overexposure is washed subsequently and expose keyset 10 with part; Keyset 10 will be exposed by dry etching or wet etch technique again and be etched to a desired depth, form receiving space 11.
Certainly, if need to make more receiving spaces 11 by lithography, photoetching can be repeated on receiving space 11 diapire 101 completed, to produce the receiving space 11 of the stepped cross-section can accommodating multiple chip.
S2, chip is provided with multiple weld pad 22 one side and coats adhesion coating 21, and by described chip adhesive on the diapire of receiving space 11.As known to persons of ordinary skill in the art, chip 20 generally includes functional surfaces nand function face, and the one side scribbling adhesion coating 21 mentioned here is often referred to the functional surfaces of chip 20.The benefit of setting like this is, in a subsequent step, conducting medium 14 just can be electrically connected with chip 20 by arranging shorter length, reduces the power consumption that may be produced by conducting medium 14.
S3, on described keyset formed run through described keyset 10 and the through hole 12 be communicated with described receiving space 11; Concrete technology is: at keyset lower surface 100b spin coating photoresist, by with similar photoetching process in step S1, form the through hole 12 running through keyset 10, preferably, formed in described keyset upper and lower surface to run through described keyset and multiple through holes of the described multiple bond pad locations of coupling be communicated with described receiving space, in the present embodiment, by arranging described receiving space, indirectly reduce the thickness of keyset 10, make through hole 12 be more prone to make, reduce the difficulty of etch process.
S4, on the inwall and keyset lower surface 100b of through hole 12 depositing insulating layer 13, to isolate with keyset 10.The material of insulating barrier 13 such as comprises epoxy resin, anti-welding material or other megohmite insulant be applicable to, or the silica of such as inorganic material, silicon nitride, silicon oxynitride.The generation type of insulating barrier 13 can comprise coating method, such as, and rotary coating, spraying, or other depositional mode be applicable to, such as, physical vapour deposition (PVD), chemical vapour deposition (CVD).
S5, employing laser or etch process run through the weld pad of chip 20 and the adhesion coating 21 of through hole 12 corresponding position, to expose described weld pad 22.
S6, utilization plating or sputtering process form conducting medium 14 on insulating barrier 13, and, the conducting medium 14 in described through hole 12 is electrically connected with the weld pad 22 on described chip 20.
Should be understood that, conducting medium 14 is formed by physical gas-phase deposition, such as sputters.The material of conducting medium 14 can be selected from copper, aluminium, gold, platinum, tungsten or its combination.
S7, on described conducting medium 14 spin coating one welding resisting layer 15, and by with similar photoetching process in step S1, welding resisting layer 15 on described keyset lower surface makes multiple opening (not shown) that part exposes conducting medium 14 by lithography, and be electrically connected multiple metal salient point 16 by the plurality of opening formation with described conducting medium 14, the pitch of the plurality of metal salient point is greater than the pitch of multiple weld pad, be connected better to match with external pcb board 30, complete surface mount process.
Be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should by specification integrally, technical scheme in each execution mode also through appropriately combined, can form other execution modes that it will be appreciated by those skilled in the art that.
A series of detailed description listed is above only illustrating for feasibility execution mode of the present invention; they are also not used to limit the scope of the invention, all do not depart from the skill of the present invention equivalent implementations done of spirit or change all should be included within protection scope of the present invention.
Claims (4)
1. a method for packaging semiconductor, is characterized in that, the method comprises the following steps:
One keyset is provided, forms the receiving space of depression from described keyset upper surface;
There is provided a chip, which is provided with multiple weld pad, the one side being provided with weld pad at described chip arranges adhesion coating, and is bonded in by described adhesion coating on the diapire of described receiving space by described chip;
Described keyset is formed and runs through described keyset and the through hole be communicated with described receiving space;
In described through hole and described keyset lower surface conducting medium is set, described weld pad and described conducting medium are electrically connected, and are greater than the metal salient point of described multiple weld pad pitch in multiple pitches that described keyset lower surface is formed and described conducting medium is electrically connected.
2. method according to claim 1, is characterized in that, " in described through hole, arranging conducting medium " is front also to be comprised:
Described through-hole wall and described keyset lower surface form insulating barrier;
Run through described adhesion coating, expose described weld pad.
3. method according to claim 2, is characterized in that, " and form the multiple arrangement density be electrically connected with described conducting medium at described keyset lower surface be less than described multiple weld pad and arrange the metal salient point of density " specifically comprises:
Described conducting medium is formed a welding resisting layer;
On the welding resisting layer of described keyset lower surface, forming section exposes the opening of described conducting medium;
Form the multiple arrangement density be electrically connected with described conducting medium to be over said opening less than described multiple weld pad and to arrange the metal salient point of density.
4. method as claimed in any of claims 1 to 3, is characterized in that, described " formed on described keyset and run through described keyset and the through hole be communicated with described receiving space " step specifically comprises:
Formed in described keyset upper and lower surface and run through described keyset and multiple through holes of the described multiple bond pad locations of coupling be communicated with described receiving space.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210094779.9A CN102623426B (en) | 2012-03-31 | 2012-03-31 | Semiconductor packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210094779.9A CN102623426B (en) | 2012-03-31 | 2012-03-31 | Semiconductor packaging method |
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| Publication Number | Publication Date |
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| CN102623426A CN102623426A (en) | 2012-08-01 |
| CN102623426B true CN102623426B (en) | 2015-04-22 |
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| CN201210094779.9A Active CN102623426B (en) | 2012-03-31 | 2012-03-31 | Semiconductor packaging method |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103227117B (en) * | 2013-04-15 | 2016-01-13 | 江阴长电先进封装有限公司 | A kind of method for packing of silicon substrate pinboard |
| TWI603447B (en) * | 2014-12-30 | 2017-10-21 | 精材科技股份有限公司 | Chip package and manufacturing method thereof |
| CN104576520A (en) * | 2015-01-14 | 2015-04-29 | 华天科技（昆山）电子有限公司 | Method for interconnecting back faces of wafer level chips during packaging |
| CN109962019A (en) * | 2017-12-22 | 2019-07-02 | 中芯长电半导体（江阴）有限公司 | A kind of fan-out-type wafer level packaging structure and method |
| WO2020029096A1 (en) * | 2018-08-07 | 2020-02-13 | 深圳市为通博科技有限责任公司 | Chip package structure and manufacturing method therefor |
| CN110634829A (en) * | 2019-08-29 | 2019-12-31 | 上海先方半导体有限公司 | Fan-out type chip packaging structure and preparation method |
| CN111403332B (en) * | 2020-02-28 | 2023-04-28 | 浙江集迈科微电子有限公司 | Manufacturing method of ultra-thick adapter plate |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297253A (en) * | 1999-10-05 | 2001-05-30 | 日本电气株式会社 | Wiring baseboard, semiconductor device with wiring baseboard, and mfg. and installing method thereof |
| CN101252141A (en) * | 2007-02-21 | 2008-08-27 | 育霈科技股份有限公司 | Wafer level image sensor package with die receiving cavity and method of making the same |
| CN201608172U (en) * | 2010-02-08 | 2010-10-13 | 江阴长电先进封装有限公司 | Packaging carrier plate structure |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI236122B (en) * | 2004-02-27 | 2005-07-11 | Via Tech Inc | A low thermal expansion build-up layer packaging and a method to package a die using the same |
| US8101868B2 (en) * | 2005-10-14 | 2012-01-24 | Ibiden Co., Ltd. | Multilayered printed circuit board and method for manufacturing the same |
-
2012
- 2012-03-31 CN CN201210094779.9A patent/CN102623426B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1297253A (en) * | 1999-10-05 | 2001-05-30 | 日本电气株式会社 | Wiring baseboard, semiconductor device with wiring baseboard, and mfg. and installing method thereof |
| CN101252141A (en) * | 2007-02-21 | 2008-08-27 | 育霈科技股份有限公司 | Wafer level image sensor package with die receiving cavity and method of making the same |
| CN201608172U (en) * | 2010-02-08 | 2010-10-13 | 江阴长电先进封装有限公司 | Packaging carrier plate structure |
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| CN102623426A (en) | 2012-08-01 |
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