CN102623303A - SOI wafer and preparation method thereof - Google Patents
SOI wafer and preparation method thereof Download PDFInfo
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- CN102623303A CN102623303A CN2011100303941A CN201110030394A CN102623303A CN 102623303 A CN102623303 A CN 102623303A CN 2011100303941 A CN2011100303941 A CN 2011100303941A CN 201110030394 A CN201110030394 A CN 201110030394A CN 102623303 A CN102623303 A CN 102623303A
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- substrate
- semiconductor layer
- annealing
- soi wafer
- insulating barrier
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- 238000002360 preparation method Methods 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000000463 material Substances 0.000 claims abstract description 17
- 238000002425 crystallisation Methods 0.000 claims abstract description 15
- 230000008025 crystallization Effects 0.000 claims abstract description 15
- 239000013078 crystal Substances 0.000 claims abstract description 14
- 238000000137 annealing Methods 0.000 claims abstract description 13
- 230000008569 process Effects 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims description 30
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical group [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 12
- 238000013459 approach Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000005224 laser annealing Methods 0.000 claims description 6
- 239000011521 glass Chemical group 0.000 claims description 4
- 229910001220 stainless steel Chemical group 0.000 claims description 4
- 239000010935 stainless steel Chemical group 0.000 claims description 4
- 239000000428 dust Substances 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000012545 processing Methods 0.000 claims description 2
- 238000004151 rapid thermal annealing Methods 0.000 claims description 2
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 claims description 2
- 238000006356 dehydrogenation reaction Methods 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 11
- 230000008901 benefit Effects 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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Abstract
The invention provides a SOI wafer and a preparation method thereof. The method comprises: providing a substrate, wherein the substrate comprises materials with low price and high temperature resistance; forming insulating layers on the upper, lower and side surfaces of the substrate so that the substrate is covered by the insulating layers; forming a semiconductor layer upon the insulating layer on the upper surface of the substrate; and carrying out an annealing crystallization process so that a top surface semiconductor layer is crystallized to a monocrystalline semiconductor layer or a polycrystalline semiconductor layer with large-sized crystal grains and high quality. The method of the invention adopts materials with low price and high temperature resistance as the supporting substrate and adopts a crystallization process, so that the monocrystalline top surface semiconductor layer or the polycrystalline top surface semiconductor layer with large-sized crystal grains is formed on the top surface, thereby forming the SOI wafer with low price and high quality.
Description
Technical field
The present invention relates to semiconductor device and manufacturing field, particularly a kind of manufacturing approach of SOI wafer and SOI wafer thereof.
Background technology
(Silicon-on-insulator, SOI) technology is a kind ofly on the basis of silicon materials and silicon integrated circuit immense success, to occur, its unique advantage is arranged, can break through the new technology that silicon materials and silicon integrated circuit limit to silicon-on-insulator.Along with fast development of information technology, the SOI technology shows especially in the advantage of main flow commercial information technical fields such as high speed microelectronic component, low pressure/low energy-consumption electronic device, anti-irradiation circuit, high-temperature electronic device and micromechanics gradually, is acknowledged as " silicon of new generation ".
SOI is as a kind of improvement technology of standard CMOS process; Through the oxide layer of an insulation of inclosure between two-layer silicon substrate, thereby transistor unit is isolated each other, the SOI substrate constitutes by following three layers usually: top layer silicon; Be generally the monocrystalline top layer silicon, be used to form device; The intermediate layer of thin insulation silicon dioxide; And very thick layer-of-substrate silicon, be used to the two-layer mechanical support that provides above it.Though the SOI wafer has more high-performance and special advantages, its cost is also very high, can increase manufacturing cost greatly.
Therefore, be necessary to propose SOI wafer and the manufacturing approach thereof that a kind of cost is low and quality is high.
Summary of the invention
In order to address the above problem, the invention provides a kind of manufacturing approach of SOI wafer, said method comprises: substrate is provided, and said substrate comprises the low and resistant to elevated temperatures material of price; On upper surface, lower surface and the side of said substrate, form insulating barrier, so that substrate is surrounded by said insulating barrier; On the insulating barrier of said substrate top surface, form semiconductor layer; The crystallization of annealing is handled, so that the said semiconductor layer crystallization of top layer is the semiconductor layer of monocrystalline or the polycrystal semiconductor layer with large scale crystal grain.
In addition, the present invention also provides the SOI wafer that forms according to said method, comprising: substrate, said substrate comprise the low and resistant to elevated temperatures material of price; Be formed at the insulating barrier on upper surface, lower surface and the side of said substrate, said substrate is surrounded by said insulating barrier; Be formed at the top-layer semiconductor on the insulating barrier of said substrate top surface, wherein said top-layer semiconductor is the semiconductor layer of monocrystalline or the polycrystal semiconductor layer with large scale crystal grain.
According to SOI wafer manufacturing approach of the present invention; The material that the employing price is low and ability is high temperature resistant is as support substrates; For example secondary silicon, and behind the polycrystal semiconductor layer that forms top layer, through crystallization process; Form the polycrystal semiconductor layer of monocrystalline or large scale crystal grain at top layer, thereby form the SOI wafer that price is low and quality is high.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 shows the flow chart of the manufacturing approach of SOI wafer according to an embodiment of the invention;
Fig. 2-Fig. 5 shows the sketch map of each fabrication stage of SOI wafer according to an embodiment of the invention.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.Disclosing of hereinafter provides many various embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition; First characteristic of below describing second characteristic it " on " structure can comprise that first and second characteristics form the embodiment of direct contact; Can comprise that also additional features is formed on the embodiment between first and second characteristics, such first and second characteristics possibly not be direct contacts.
With reference to figure 1, Fig. 1 shows the flow chart according to the SOI wafer manufacturing approach of the embodiment of the invention.Step S01, as shown in Figure 2, substrate 200 is provided, said substrate comprises the low and resistant to elevated temperatures material of price.Said substrate can select price to be lower than the material of polycrystalline substrate price, and the heat resisting temperature of said substrate is more than 600 ℃, in embodiments of the present invention; Can select secondary silicon; The silicon chip of for example using in the solar industry, the impurity concentration that its silicon chip that has than uses in the microprocessor industry is high has the low characteristics of price; In other embodiments, said substrate can also be other suitable low price materials such as glass, aluminium oxide or stainless steel.The present invention does not limit the shape and the size of said substrate, can be circular, and size can be 100mm, 200mm, 300mm or large scale more, also can be square, and size can be 100mm*100mm, 200mm*200mm, 300mm*300mm or bigger.
Step S02 forms insulating barrier 210 on upper surface 200-1, lower surface 200-2 and the side 200-3 of said substrate 200, so that substrate 200 is by said insulating barrier 210 encirclements, with reference to figure 3.Said insulating barrier 210 can comprise SiO
2, Si
3N
4, Al
2O
3Or other insulating material, or their combination, can be one deck structure or multiple-level stack structure, in one embodiment of the invention, said insulating barrier 210 is SiO
2Can adopt the method deposition insulating material of PECVD (plasma enhanced CVD), LPCVD (low-pressure chemical vapor phase deposition) or ALD (atomic layer deposition) to form insulating barrier 210; Also can adopt the method oxidation substrate 200 of dry method or wet oxidation to form insulating barrier 210, can also through initial oxidation then the method for deposition insulating material form insulating barrier 210, to improve process efficiency; Be merely example here, be not limited to this.The thickness of the insulating barrier 210 on the said upper surface 200-1 can be about 9000-11000 dust, and the thickness of the insulating barrier of said lower surface 200-2 grid can be less than the thickness of upper surface insulating barrier, and for example 5000 Izods are right.The purpose that on the lower surface 200-2 of said substrate 200 and side 200-3, forms insulating barrier 210 is as diffusion impervious layer, to prevent that the impurity in the substrate 200 is to outdiffusion when follow-up crystallization is handled.
Step S03 forms semiconductor layer 220, with reference to figure 4 on the insulating barrier 210 of said substrate top surface 200-1.Said semiconductor layer 220 can be the semi-conducting material of polycrystalline; In the preferred embodiment; Can be polysilicon layer, can adopt the method for PECVD or LPCVD on the insulating barrier 210 of said substrate top surface 200-1, to form this polysilicon layer, the thickness of said polysilicon layer can be the 200-1500 dust.
Preferably, after forming semiconductor layer, can go H to handle, to reduce the H content in semiconductor layer 220 and the insulating barrier 210.Can adopt methods such as heating anneal or UV-irradiation to go H to handle; The minimizing of the H content in semiconductor layer and the insulating barrier; Can increase the coefficient of safety of subsequent technique because too high H content, can cause semiconductor layer among a small circle blast and cause accident or low rate of finished products.
Step S04, the crystallization of annealing is handled.Can adopt rapid thermal annealing, laser annealing or its combination and other suitable methods to carry out crystallization and handle, wherein laser annealing comprises ELA laser annealing, Green laser, SLS annealing or its combination.Can be as required; Select different annealing processs and the technological parameter of annealing (angle of temperature, energy, time and laser beam etc.); Can with the top-layer semiconductor crystallization semiconductor layer (for example monocrystalline silicon) of monocrystalline; Or crystallization is the polycrystal semiconductor layer 230 (the for example polysilicon layer of large scale crystal grain) with large scale crystal grain; With reference to figure 5, thus the quality of raising top-layer semiconductor, and the size of polycrystalline top-layer semiconductor crystal grain is by annealing process and selection of process parameters decision.
More than the manufacturing approach of the SOI wafer of the embodiment of the invention has been carried out detailed description; In addition, the present invention also provides the SOI wafer that forms according to said method, with reference to figure 5; Said wafer comprises: substrate 200; Said substrate 200 comprises the low and resistant to elevated temperatures material of price, and the price of said substrate can be the price that is lower than the polysilicon substrate, and the high temperature that said substrate can bear is for being not less than 600 ℃; The example of said substrate can comprise secondary silicon, glass, aluminium oxide or stainless steel, thereby reduces the price of wafer; Be formed at the insulating barrier 210 on upper surface 200-1, lower surface 200-2 and the side 200-3 of said substrate 200, said substrate 200 is surrounded by said insulating barrier 210; Be formed at the top-layer semiconductor 230 on the insulating barrier 210 of said substrate 200 upper surface 200-1; Wherein said top-layer semiconductor 230 is for the semiconductor layer of monocrystalline or have the polycrystal semiconductor layer of large scale crystal grain, for example monocrystalline silicon or have the polysilicon of big crystal grain.
More than the manufacturing approach and the SOI wafer thereof of the SOI wafer of the embodiment of the invention carried out detailed description; The material that the employing price is low and ability is high temperature resistant is as support substrates; For example secondary silicon, and behind the semiconductor layer that forms top layer, through crystallization process; Form the top-layer semiconductor of monocrystalline or large scale crystal grain at top layer, thereby formed the SOI wafer that price is low and quality is high.With the transistor of this kind SOI wafer manufacturing have speed fast with advantages such as electric leakage is little.
Though specify about example embodiment and advantage thereof, be to be understood that under the situation of the protection range that does not break away from the qualification of spirit of the present invention and accompanying claims, can carry out various variations, replacement and modification to these embodiment.For other examples, when those of ordinary skill in the art should understand easily in keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technology, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the specification.From disclosure of the present invention; To easily understand as those of ordinary skill in the art; For the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present; Wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the present invention or obtain identical substantially result, can use them according to the present invention.Therefore, accompanying claims of the present invention is intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection range.
Claims (13)
1. the manufacturing approach of a SOI wafer, said method comprises:
Substrate is provided, and said substrate comprises the low and resistant to elevated temperatures material of price;
On upper surface, lower surface and the side of said substrate, form insulating barrier, so that said substrate is surrounded by said insulating barrier;
On the insulating barrier of said substrate top surface, form semiconductor layer;
The crystallization of annealing is handled, so that the said semiconductor layer crystallization of top layer is the semiconductor layer of monocrystalline or the polycrystal semiconductor layer with large scale crystal grain.
2. method according to claim 1, wherein said high temperature is for being not less than 600 ℃.
3. method according to claim 1, wherein said substrate comprises secondary silicon, glass, aluminium oxide or stainless steel.
4. method according to claim 1, wherein said semiconductor layer comprise unordered silicon, polysilicon or its combination.
5. method according to claim 4, the thickness of wherein said semiconductor layer are the 200-1500 dust.
6. method according to claim 1, before the crystallization of annealing is handled, form semiconductor layer after, also comprise step: carry out the dehydrogenation processing.
7. method according to claim 6, wherein said dehydrogenation are handled and are comprised: heating anneal or UV-irradiation.
8. according to each described method among the claim 1-7, the annealing process during wherein said annealing crystallization is handled comprises: rapid thermal annealing, laser annealing, flash annealing or its combination.
9. method according to claim 8, said laser annealing comprise ELA laser annealing, Green laser, SLS annealing or its combination.
10. SOI wafer, said SOI wafer comprises:
Substrate, said substrate comprise the low and resistant to elevated temperatures material of price;
Be formed at the insulating barrier on upper surface, lower surface and the side of said substrate, said substrate is surrounded by said insulating barrier;
Be formed at the top-layer semiconductor on the insulating barrier of said substrate top surface, wherein said top-layer semiconductor is the semiconductor layer of monocrystalline or the polycrystal semiconductor layer with large scale crystal grain.
11. SOI wafer according to claim 10, wherein said high temperature is for being not less than 600 ℃.
12. SOI wafer according to claim 10, wherein said substrate comprises secondary silicon, glass, aluminium oxide or stainless steel.
13. SOI wafer according to claim 10, wherein said top-layer semiconductor comprise monocrystalline silicon or have the polysilicon of big crystal grain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100303941A CN102623303A (en) | 2011-01-27 | 2011-01-27 | SOI wafer and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100303941A CN102623303A (en) | 2011-01-27 | 2011-01-27 | SOI wafer and preparation method thereof |
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| CN102623303A true CN102623303A (en) | 2012-08-01 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425340A (en) * | 2013-08-22 | 2015-03-18 | 中国科学院微电子研究所 | semiconductor manufacturing method |
| CN111290148A (en) * | 2020-02-19 | 2020-06-16 | 联合微电子中心有限责任公司 | Method for manufacturing modulator with SiO2 substrate formed based on wafer bonding and modulator structure thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05211151A (en) * | 1991-11-29 | 1993-08-20 | Nec Corp | Substrate for semiconductor element and manufacture of semiconductor element |
| US5416341A (en) * | 1993-02-22 | 1995-05-16 | Nec Corporation | Substrate for a semiconductor device and method for manufacturing a semiconductor device from the substrate |
| US20080128851A1 (en) * | 2004-09-13 | 2008-06-05 | Shin-Etsu Handotai Co., Ltd. | Method Of Manufacturing Soi Wafer And Thus-Manufactured Soi Wafer |
| CN101946303A (en) * | 2008-02-14 | 2011-01-12 | 信越化学工业株式会社 | The surface treatment method of SOI substrate |
-
2011
- 2011-01-27 CN CN2011100303941A patent/CN102623303A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05211151A (en) * | 1991-11-29 | 1993-08-20 | Nec Corp | Substrate for semiconductor element and manufacture of semiconductor element |
| US5416341A (en) * | 1993-02-22 | 1995-05-16 | Nec Corporation | Substrate for a semiconductor device and method for manufacturing a semiconductor device from the substrate |
| US20080128851A1 (en) * | 2004-09-13 | 2008-06-05 | Shin-Etsu Handotai Co., Ltd. | Method Of Manufacturing Soi Wafer And Thus-Manufactured Soi Wafer |
| CN101946303A (en) * | 2008-02-14 | 2011-01-12 | 信越化学工业株式会社 | The surface treatment method of SOI substrate |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104425340A (en) * | 2013-08-22 | 2015-03-18 | 中国科学院微电子研究所 | semiconductor manufacturing method |
| CN111290148A (en) * | 2020-02-19 | 2020-06-16 | 联合微电子中心有限责任公司 | Method for manufacturing modulator with SiO2 substrate formed based on wafer bonding and modulator structure thereof |
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