CN102611592B - Ethernet RMII (reduced medium independent interface) based on FPGA (field programmable gate array) and realization method - Google Patents
Ethernet RMII (reduced medium independent interface) based on FPGA (field programmable gate array) and realization method Download PDFInfo
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Abstract
The invention discloses an Ethernet RMII (reduced medium independent interface) based on an FPGA (field programmable gate array) and a realization method. The Ethernet RMII comprises an FPGA and a physical layer chip, wherein the FPGA comprises a sending module and a receiving module; the sending module comprises a sending state machine, a first state counter, a first CRC (cyclic redundancy check) generation circuit module and a random number generator; the sending module sends Ethernet data according to the standard RMII stipulated by the IEEE802.3 protocol; the receiving module comprises a receiving state machine, a second state counter, a second CRC generation circuit module and an address detector; and the receiving module receives the Ethernet data according to the standard RMII stipulated by the IEEE802.3 protocol. In the invention, the RMII is directly realized in the FPGA, thus the hardware I/O (input/output) port of the FPGA is saved, and a relatively large space is reserved for upgrading the merging unit of a hardware PCB (printed circuit board).
Description
[technical field]
The invention belongs to microelectronic, relate to a kind of high-voltage ac current high-acruracy survey field merging unit of electronic transformer multichannel Ethernet output interface, especially a kind of Ethernet RMII (Reduced Medium Independent Interface is called for short RMII interface) based on field programmable gate array (FPGA).
[background technology]
China national grid company proposes " strong intelligent grid " development plan in May, 2009, proposition will be built the sturdy power grid developing taking extra-high voltage grid as key, at different levels electric network coordination as basis, and its construction is planned to be divided into three phases: 2009-2010 study emphasis intelligent grid development plan is worked; 2011-2015 is the all-round construction stage; 2016-2020 is for leading the improvement stage.And the equipment that forms whole intelligent grid is with regard to necessary and network integration, to reach unified management, to dispatch, the functions such as monitoring, really realize the intellectuality of operation of power networks.Wherein the data of the output interface of electronic mutual inductor just must be to upload data to process layer for the standard of 10BaseT (the 14th article) and 100BaseT X (the 24th article and the 25th article) in IEEE 802.3k.
According to " intelligent substation technology directive/guide ", for each intelligent equipment in transformer station, corresponding requirements and standard are all proposed.Wherein each equipment all obtains supported data and uploads the function of network, this just supports Ethernet to send to each equipment and has proposed rigid requirement, especially electronic mutual inductor and merge cells parameters thereof are had higher requirement, require the part of merge cells to have the requirement of 8 tunnel independence Ethernet output ports at least.In each intelligent telephone systems of transformer station such as transformer substation/power plant complex automatic system, the automatic telephone system of Based Intelligent Control, electrical network/generation comprehensive supervisory control system, automation system for the power network dispatching and intelligent power distribution automated system, all need to arrive corresponding network layer by ethernet standard interface uploading data.
If merge cells 8 road Ethernet outputs adopt MII interface, Hardware I/O of FPGA can reach more than 100 so, has seriously consumed the hardware resource of FPGA, and to the hardware arrangement sizable difficulty brought that connects up, upgrading for merge cells causes obstacle, has strengthened the cost of merge cells.
[summary of the invention]
The object of the present invention is to provide a kind of Ethernet RMII interface and implementation method based on programmable gate array, simplify existing MII interface, solve the problem of the FPGA pin wasting of resources that in MII standard interface, holding wire too much causes.
To achieve these goals, the present invention adopts following technical scheme:
An Ethernet RMII interface based on field programmable gate array, comprises field programmable gate array, physical chip; Described field programmable gate array comprises sending module and receiver module; Sending module comprises transmission state machine, first each state counter, CRC generative circuit module and a tandom number generator; Sending module sends Ethernet data according to IEEE802.3 agreement specified standard RMII interface; Receiver module comprises accepting state machine, second each state counter, the 2nd CRC generative circuit module and address detection device; Receiver module receives Ethernet data according to IEEE802.3 agreement specified standard RMII interface.
The model of described physical chip is LXT9785.
The random number generation module of sending module for producing random sending times under clogged conditions; First each state counter comprises the first frame gap counter in process of transmitting, delay counter, collision window counter; The first frame gap counter is in order to ensure the time slot between two frames; Delay counter is for storing the rear time of waiting for the bus free time of transmission that starts; Collision window counter is in order to judge whether current occurred conflict is rear conflict; The one CRC generative circuit is in order to realize the check code sequence of Frame; Whether the address detection device module of receiver module matches with this station address in order to the destination address field (DAF) that checks frame, if do not mated, it is discarded; Second each state counter comprises the second frame gap counter and byte counter; Between the Frame that the second frame gap counter receives in order to detection and former frame, whether meet the requirement of minimum interFrameGap, if do not met, it is abandoned; Receive byte counter in order to store the byte length of received frame, judge that received frame length is whether between minimum frame length and maximum frame size; The 2nd CRC generative circuit is in order to realize the check code sequence of Frame.
After system reset, sending module enters time delay state, and detected carrier is intercepted signal always; When carrier detect signal becomes when invalid, send state machine and enter frame gap state; After this,, after waiting for an interframe gap, send state machine and enter idle condition; If channel busy signal is arrived in front 2/3 cycle detection at interframe gap, send state machine and will come back to time delay state; After state machine enters idle condition, detected carrier is intercepted to signal to sending module and upper strata sends sending request of receiving interface; If upper strata host module request sends, send state machine and will enter the first lead code state, sending module notifies physical chip to send beginning, starts to send preamble simultaneously, then sends SFD; Send state machine and enter after 2 states of the first data, sending module will send the low 2 of a data byte; Enter after 2 states of the second data when sending state machine, sending module sends latter 2 of data byte; Enter after 2 states of the 3rd data when sending state machine, sending module sends latter 2 of data byte; Enter after 2 states of the 4th data when sending state machine, sending module sends the high 2 of data byte; Subsequently, send state machine and between 2 states of first to fourth data, circulate always, until data are sent; In the time also remaining a byte, upper strata host module will be notified sending module by sending frame end signal; If the length of Frame is greater than minimum frame and is less than largest frames, send state machine and just enter check code state, the crc value that now sending module generates a CRC generation module adds in the check code field of frame and sends to physical chip.
After receiver module detects data useful signal, accepting state machine enters the second lead code state from bus idle state, and starts to receive preamble, after this accepting state machine enters start-of-frame state, receive the SFD of a byte, enter different conditions according to the value of the second interframe counter afterwards, if the second determined time of interframe counter was greater than 96 bit times, accepting state machine will enter 2 states of the 5th data to receive the low 2 of byte, then enter latter 2 with reception byte of 2 states of the 6th data, then enter latter 2 with reception byte of 2 states of the 7th data, finally enter 2 states of the 8th data to receive the high 2 of byte, get back to again afterwards 2 states of the 5th data, accepting state machine just circulates always between 2 these one of four states of state of the 5th to the 8th data, until enter idle condition after data receiver, receives new data again to wait for, if while receiving SFD, the second determined time of frame gap counter was less than 96 bit times, and accepting state machine will enter discarding state so, and maintain this state until data useful signal finishes always, afterwards, accepting state machine returns idle waiting and receives new data.
If during receiving preamble, SFD and data, data useful signal is eliminated, accepting state machine will be got back to bus idle state so.
The model of described programmable gate array chip is XC3S500E-4PQ208I.
An implementation method for Ethernet RMII interface based on field programmable gate array, comprises data sending step and data receiver step;
Described data sending step comprises: first sending module enters time delay state, and detected carrier is intercepted signal always; When carrier detect signal becomes when invalid, send state machine and enter frame gap state; After this,, after waiting for an interframe gap, send state machine and enter idle condition; If channel busy signal is arrived in front 2/3 cycle detection at interframe gap, send state machine and will come back to time delay state; After state machine enters idle condition, detected carrier is intercepted sending request of signal and host interface by sending module; If host module request sends, send state machine and will enter the first lead code state, sending module notifies physical chip to send beginning, starts to send preamble simultaneously, then sends SFD; Send state machine and enter after 2 states of the first data, sending module will send the low 2 of a data byte; Enter after 2 states of the second data when sending state machine, sending module sends latter 2 of data byte; Enter after 2 states of the 3rd data when sending state machine, sending module sends latter 2 of data byte; Enter after 2 states of the 4th data when sending state machine, sending module sends the high 2 of data byte; Subsequently, send state machine and between 2 states of first to fourth data, circulate always, until data are sent; In the time also remaining a byte, host module will be notified sending module by sending frame end signal; If the length of Frame is greater than minimum frame and is less than largest frames, send state machine and just enter check code state, the crc value that now sending module generates a CRC generation module adds in the check code field of frame and sends to physical chip;
Described data receiver step comprises: after receiver module detects data useful signal, accepting state machine enters the second lead code state from bus idle state, and starts to receive preamble, after this accepting state machine enters start-of-frame state, receive the SFD of a byte, enter different conditions according to the value of the second interframe counter afterwards, if the second determined time of interframe counter was more than or equal to 96 bit times, accepting state machine will enter 2 states of the 5th data to receive the low 2 of byte, then enter latter 2 with reception byte of 2 states of the 6th data, then enter latter 2 with reception byte of 2 states of the 7th data, finally enter 2 states of the 8th data to receive the high 2 of byte, get back to again afterwards 2 states of the 5th data, accepting state machine just circulates always between 2 these one of four states of state of the 5th to the 8th data, until enter idle condition after data receiver, receives new data again to wait for, if while receiving SFD, the second determined time of frame gap counter was less than 96 bit times, and accepting state machine will enter discarding state so, and maintain this state until data useful signal finishes always, afterwards, accepting state machine returns idle waiting and receives new data.
Sending module sends Ethernet data according to IEEE802.3 agreement specified standard RMII interface; Receiver module receives Ethernet data according to IEEE802.3 agreement specified standard RMII interface.
Sending module and receiver module are realized in programmable gate array at the scene; The model of described field programmable gate array is XC3S500E-4PQ208I; The model of described physical chip is LXT9785.
The invention solves following technical problem:
1. solved and there is independent data controller (MAC) more than 8 tunnels and meet IEC61850-9-2 protocol massages output.
2. solve in merge cells the consumption of FPGA Hardware I/O mouth too much, caused FPGA hardware resource waste problem.
3. solve the narrow and small problem of merge cells hardware pcb board arrangement space, and reduced the power consumption of merge cells, left larger upgrading space to merge cells.
4. by IEEE802.3 agreement regulation, RMII interface is designed, realized the standard ethernet output interface of scaled-down version.
With respect to prior art, the present invention has the following advantages: the present invention directly realizes RMII interface in FPGA, and external physical layer is selected LXT9785 chip; So just well save FPGA Hardware I/O mouth; Reserve more space to hardware PCB version and carry out the upgrading of merge cells.
[brief description of the drawings]
Fig. 1 is the schematic diagram of realizing of RMII interface of the present invention; Wherein Mtx_En is for sending enable port; MtxD[1::0] for sending FPDP; Ref_Clk is reference clock port; Crx_Dv is carrier sense and the effective port of data; Mrx_Err: the invalid port of data; MrxD[1::0] for receiving FPDP.
Fig. 2 is the schematic diagram of the sending module in RMII interface of the present invention.
Fig. 3 is the transmission state machine diagram in RMII interface of the present invention.
Fig. 4 is the schematic diagram of the receiver module in RMII interface of the present invention.
Fig. 5 is the accepting state machine schematic diagram in RMII interface of the present invention.
Fig. 6 is that RMII interface of the present invention sends emulation synthesis result figure.
[embodiment]
Below in conjunction with accompanying drawing, the present invention is described in further detail:
Referring to Fig. 1-6, a kind of Ethernet RMII interface based on field programmable gate array of the present invention, comprises field programmable gate array (FPGA) and physical chip (LXT9785); RMII Interface realization principle comprises sending module, receiver module.
Refer to shown in Fig. 2, sending module includes transmission state machine, each state counter, CRC generative circuit and tandom number generator.Wherein send state machine and belong to core, for managing each function sub-modules, according to certain sequential working, finally send Ethernet data according to IEEE802.3 agreement specified standard RMII interface.
Refer to shown in Fig. 4, receiver module includes accepting state machine, each state counter, CRC generative circuit and address detection device.This module receives 2 Bit datas according to accepting state machine, and the data that convert thereof into taking byte as unit are kept at data buffer area.This module interface receives Ethernet data according to IEEE802.3 agreement specified standard RMII interface.
With reference to Fig. 1, the hardware selection in this programme is as follows:
FPGA:XC3S500E-4PQ208I; Physical chip: LXT9785.
Ethernet RMII interface is mainly used in MAC and physical layer (PHY) interconnection technique, and this interface is supported the message transmission rate of 10Mb/s and 100Mb/s, has simplified greatly MII interface.Its sending module and receiver module provide the sending and receiving function of mac frame, and it mainly operates the encapsulation of mac frame and unpacks and error detection.
In FPGA, directly design RMII interface, realized sending module and receiver module, and the parallel data grabbing card of external physical layer is provided, meet IEEE802.3 Ethernet protocol, realize the seamless link with MAC layer and physical layer.In FPGA, carry out parsing and the packing of data, and realize the transmission-receiving function of data, be directly connected with outside LXT9785.
With reference to Fig. 2, sending module is mainly realized CSMA/CD agreement, and this module becomes 2 bits to send ethernet physical layer chip to the data transaction of receiving from MAC layer.Random number generation module is mainly used in producing random sending times under clogged conditions.Each state counter has been realized the frame gap counter in process of transmitting, delay counter, and collision window counter, delay counter is for storing the rear time of waiting for the bus free time of transmission that starts.Frame gap counter is in order to ensure the time slot between two frames.Collision window counter is in order to judge whether current occurred conflict is rear conflict.CRC generative circuit is in order to realize the check code sequence of Frame.
With reference to Fig. 3, the present invention sends the core that state machine is whole process of transmitting, for managing each module according to certain sequential working.After system reset, sending module enters time delay state, and send state machine always detected carrier intercept (CarrierSense) signal.In the time that carrier detect signal becomes invalid (expression channel idle), send state machine and enter frame gap state.After this,, after waiting for an interframe gap, send state machine and enter idle condition.Channel busy signal detected if send state machine in front 2/3 cycle of interframe gap, send state machine and will come back to time delay state.After state machine enters idle condition, detected carrier is intercepted to signal to sending module and upper strata sends sending request of receiving interface.If host module request sends, send state machine and will enter lead code state, sending module notifies PHY to send beginning, starts to send preamble (7 0x5) simultaneously, then sends SFD (0xd).State machine enters after 2 (1) states of data, sending module will send the low 2 of a data byte, when it enters after 2 (2) states of data, sending module sends latter 2 of data byte, when it enters after 2 (3) states of data, sending module sends latter 2 of data byte, and when it enters after 2 (4) states of data, sending module sends the high 2 of data byte.Subsequently, state machine circulates always between these four data modes, until data are sent.In the time also remaining a byte, host module will be notified sending module by sending frame end signal.If the length of Frame is greater than minimum frame and is less than largest frames, send state machine and just enter check code state, the crc value that now sending module generates CRC generation module adds in the check code field of frame and sends to physical layer PHY.After frame sends, state machine enters time delay state, is frame gap and idle condition afterwards.After this state machine is got back to again initial condition, again to wait for new sending request.If the length of Frame is less than the shortest frame, state machine just enters occupied state, and according to system, setting determines whether to add filler code after data to sending module.Then, state machine enters verification state.If the length of Frame is greater than largest frames, and system setting supports to send oversized frame, so, state machine just enters verification state; If do not support to send oversized frame, sending module will be abandoned sending, and state machine directly enters time delay state, is then frame gap state, finally gets back to idle condition.In the process of transmission data, sending module can check carrier sense detection signal always.If discovery carrier sense is effective and state machine is in lead code state, state machine will enter blocked state after sending preamble and SFD, and send congested code, then enter fallback state, to wait for retry.Afterwards, state machine is got back to idle condition through state under time delay state and interframe.If now the value of retry counter does not reach rated value, sending module sends frame just now by restarting, and the value of retry counter is added to 1; If find that conflict and state machine are in 2 (1) states of data, 2 (2) states of data, 2 (3) states of data, 2 (4) states of data or verification state, and do not exceed conflict time window, state machine enters blocked state by horse back and sends congested code so, pass through afterwards fallback state, time delay state, frame gap state, get back to idle condition, and determine whether resend Frame just now according to the value of retryCounter; If detect that the time clashing exceeded conflict time window, state machine will enter time delay state, then through frame gap state to idle condition, and abandon retry.Send frame in full-duplex mode time, can not postpone (time delay state), in the process of transmission, also can not produce conflict.Now, sending module will be ignored the carrier detect signal of PHY.Certainly, between frame and frame, still need to observe the rule of interframe gap.Therefore, the transmission state machine under full-duplex mode does not have blocked state, fallback state, three states of time delay state.
With reference to Fig. 4, receiver module mainly completes the reception of Frame, and receiving 2 Bit datas and convert thereof into byte from physical layer is that the data of unit are delivered to MAC layer.Whether address detection device module matches with this station address in order to the destination address field (DAF) that checks frame, if do not mated, explanation be not send to our station and it is discarded; Each state counter comprises interframe counter and byte counter.Between the Frame that frame gap counter receives in order to detection and former frame, whether meet the requirement of minimum interFrameGap, if do not met, it is abandoned; Receive byte counter in order to store the byte length of received frame, judge whether received frame length meets the demands (between minimum frame length and maximum frame size); CRC generative circuit adopt 4 position datawire parallel modes the same as sending module realize, in order to realize the check code sequence of Frame.
With reference to Fig. 5, accepting state machine is the core of receiver module.After receiver module detects data useful signal, accepting state machine will enter lead code, and start to receive preamble.After this state machine enters start-of-frame state, receive the SFD of a byte, enter different conditions according to the value of interframe counter afterwards, if the determined time of interframe counter is more than or equal to 96 bit times, state machine will enter 2 (1) states of data to receive the low 2 of byte, then be latter 2 with reception byte of 2 (2) states of data, then be latter 2 with reception byte of 2 (3) states of data, finally that 2 (4) states of data are to receive the high 2 of byte, get back to again afterwards 2 (1) states of data.Accepting state machine just circulates always between this one of four states, until enter idle condition after data receiver complete (PHY removes Crx_Dv signal), receives new data again to wait for; If while receiving SFD, the determined time of frame gap counter is less than 96 bit times, and state machine will enter discarding state so, and maintains this state until data useful signal finishes (PHY removes Crx_Dv signal) always.Afterwards, state machine returns idle waiting and receives new data.If during receiving preamble, SFD and data, data useful signal is eliminated, state machine will be got back to idle condition so.
With reference to Fig. 6, for the present invention is in rtl simulation oscillogram.
Above content is in conjunction with concrete preferred implementation further description made for the present invention; can not assert that the specific embodiment of the present invention only limits to this; for general technical staff of the technical field of the invention; without departing from the inventive concept of the premise; can also make some simple deduction or replace, all should be considered as belonging to the present invention and determine scope of patent protection by submitted to claims.
Claims (9)
1. the Ethernet RMII interface based on field programmable gate array, is characterized in that:
Comprise field programmable gate array, physical chip; Described field programmable gate array comprises sending module and receiver module;
Sending module comprises transmission state machine, first each state counter, CRC generative circuit module and a tandom number generator; Sending module sends Ethernet data according to IEEE802.3 agreement specified standard RMII interface;
Receiver module comprises accepting state machine, second each state counter, the 2nd CRC generative circuit module and address detection device; Receiver module receives Ethernet data according to IEEE802.3 agreement specified standard RMII interface;
The random number generation module of sending module for producing random sending times under clogged conditions; First each state counter comprises the first frame gap counter in process of transmitting, delay counter, collision window counter; The first frame gap counter is in order to ensure the time slot between two frames; Delay counter is for storing the rear time of waiting for the bus free time of transmission that starts; Collision window counter is in order to judge whether current occurred conflict is rear conflict; The one CRC generative circuit is in order to realize the check code sequence of Frame;
Whether the address detection device module of receiver module matches with this station address in order to the destination address field (DAF) that checks frame, if do not mated, it is discarded; Second each state counter comprises the second frame gap counter and byte counter; Between the Frame that the second frame gap counter receives in order to detection and former frame, whether meet the requirement of minimum interFrameGap, if do not met, it is abandoned; Byte counter is in order to store the byte length of received frame, judges that received frame length is whether between minimum frame length and maximum frame size; The 2nd CRC generative circuit is in order to realize the check code sequence of Frame.
2. the Ethernet RMII interface based on field programmable gate array as claimed in claim 1, is characterized in that: the model of described physical chip is LXT9785.
3. the Ethernet RMII interface based on field programmable gate array as claimed in claim 1, is characterized in that: after system reset, sending module enters time delay state, and detected carrier is intercepted signal always; When carrier detect signal becomes when invalid, send state machine and enter frame gap state; After this,, after waiting for an interframe gap, send state machine and enter idle condition; If channel busy signal is arrived in front 2/3 cycle detection at interframe gap, send state machine and will come back to time delay state;
After state machine enters idle condition, detected carrier is intercepted to signal to sending module and upper strata sends sending request of receiving interface; If host module request sends, send state machine and will enter the first lead code state, sending module notifies physical chip to send beginning, starts to send preamble simultaneously, then sends SFD; Send state machine and enter after 2 states of the first data, sending module will send the low 2 of a data byte; Enter after 2 states of the second data when sending state machine, sending module sends latter 2 of data byte; Enter after 2 states of the 3rd data when sending state machine, sending module sends latter 2 of data byte; Enter after 2 states of the 4th data when sending state machine, sending module sends the high 2 of data byte; Subsequently, send state machine and between 2 states of first to fourth data, circulate always, until data are sent; In the time also remaining a byte, host module will be notified sending module by sending frame end signal; If the length of Frame is greater than minimum frame and is less than largest frames, send state machine and just enter check code state, the crc value that now sending module generates a CRC generation module adds in the check code field of frame and sends to physical chip.
4. the Ethernet RMII interface based on field programmable gate array as claimed in claim 1, it is characterized in that: after receiver module detects data useful signal, accepting state machine enters the second lead code state from bus idle state, and starts to receive preamble, after this accepting state machine enters start-of-frame state, receive the SFD of a byte, enter different conditions according to the value of the second frame gap counter afterwards, if the second determined time of frame gap counter was greater than 96 bit times, accepting state machine will enter 2 states of the 5th data to receive the low 2 of byte, then enter latter 2 with reception byte of 2 states of the 6th data, then enter latter 2 with reception byte of 2 states of the 7th data, finally enter 2 states of the 8th data to receive the high 2 of byte, get back to again afterwards 2 states of the 5th data, accepting state machine just circulates always between 2 these one of four states of state of the 5th to the 8th data, until enter idle condition after data receiver, receives new data again to wait for, if while receiving SFD, the second determined time of frame gap counter was less than 96 bit times, and accepting state machine will enter discarding state so, and maintain this state until data useful signal finishes always, afterwards, accepting state machine returns idle waiting and receives new data.
5. the Ethernet RMII interface based on field programmable gate array as claimed in claim 4, it is characterized in that: if during receiving preamble, SFD and data, data useful signal is eliminated, and accepting state machine will be got back to bus idle state so.
6. the Ethernet RMII interface based on field programmable gate array as claimed in claim 1, is characterized in that: the model of described programmable gate array chip is XC3S500E-4PQ208I.
7. an implementation method for the Ethernet RMII interface based on field programmable gate array, is characterized in that, comprises data sending step and data receiver step;
Described data sending step comprises: first sending module enters time delay state, and detected carrier is intercepted signal always; When carrier detect signal becomes when invalid, send state machine and enter frame gap state; After this,, after waiting for an interframe gap, send state machine and enter idle condition; If channel busy signal is arrived in front 2/3 cycle detection at interframe gap, send state machine and will come back to time delay state; After state machine enters idle condition, detected carrier is intercepted sending request of signal and host interface by sending module; If host module request sends, send state machine and will enter the first lead code state, sending module notifies physical chip to send beginning, starts to send preamble simultaneously, then sends SFD; Send state machine and enter after 2 states of the first data, sending module will send the low 2 of a data byte; Enter after 2 states of the second data when sending state machine, sending module sends latter 2 of data byte; Enter after 2 states of the 3rd data when sending state machine, sending module sends latter 2 of data byte; Enter after 2 states of the 4th data when sending state machine, sending module sends the high 2 of data byte; Subsequently, send state machine and between 2 states of first to fourth data, circulate always, until data are sent; In the time also remaining a byte, host module will be notified sending module by sending frame end signal; If the length of Frame is greater than minimum frame and is less than largest frames, send state machine and just enter check code state, the crc value that now sending module generates a CRC generation module adds in the check code field of frame and sends to physical chip;
Described data receiver step comprises: after receiver module detects data useful signal, accepting state machine enters the second lead code state from bus idle state, and starts to receive preamble, after this accepting state machine enters start-of-frame state, receive the SFD of a byte, enter different conditions according to the value of the second frame gap counter afterwards, if the second determined time of frame gap counter was more than or equal to 96 bit times, accepting state machine will enter 2 states of the 5th data to receive the low 2 of byte, then enter latter 2 with reception byte of 2 states of the 6th data, then enter latter 2 with reception byte of 2 states of the 7th data, finally enter 2 states of the 8th data to receive the high 2 of byte, get back to again afterwards 2 states of the 5th data, accepting state machine just circulates always between 2 these one of four states of state of the 5th to the 8th data, until enter idle condition after data receiver, receives new data again to wait for, if while receiving SFD, the second determined time of frame gap counter was less than 96 bit times, and accepting state machine will enter discarding state so, and maintain this state until data useful signal finishes always, afterwards, accepting state machine returns idle waiting and receives new data.
8. the implementation method of a kind of Ethernet RMII interface based on field programmable gate array according to claim 7, is characterized in that, sending module sends Ethernet data according to IEEE802.3 agreement specified standard RMII interface; Receiver module receives Ethernet data according to IEEE802.3 agreement specified standard RMII interface.
9. the implementation method of a kind of Ethernet RMII interface based on field programmable gate array according to claim 7, is characterized in that, sending module and receiver module are realized in programmable gate array at the scene; The model of described field programmable gate array is XC3S500E-4PQ208I; The model of described physical chip is LXT9785.
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| CN103747113B (en) * | 2013-12-27 | 2017-05-03 | 珠海全志科技股份有限公司 | Method for automatically recognizing MII (Media Independent Interface) address of PHY (Physical Layer) chip of Ethernet controller |
| CN104702354A (en) * | 2015-03-16 | 2015-06-10 | 毕节供电局 | FPGA-based (field programmable gate array-based) PTN (packet transport network) equipment time delay monitoring device and method |
| CN105897395B (en) * | 2016-04-06 | 2019-02-22 | 济南大学 | The FPGA implementation method of SMV/GOOSE message based on RMII interface |
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