CN102611458A - LDPC (low density parity check) decoding device capable of reducing power consumption and implementation method of LDPC decoding device - Google Patents

Abstract

The invention provides an LDPC (Low Density Parity Check) decoding device capable of reducing power consumption. The LDPC decoding device is composed of a power management unit and a decoder. According to the LDPC decoding device, the implementation method of adjusting power supply voltage by using a dynamic voltage setting signal is adopted, and the power consumption of the decoder is reduced on the premise that the data throughput rate of the system and the decoding performance are guaranteed. The invention also provides an implementation method of the LDPC decoding device capable of reducing the power consumption. With the adoption of the decoding device and the implementation method, the power consumption of the decoder is effectively reduced, therefore, the power consumption of a baseband receiving chip of a CMMB (China Mobile Multimedia Broadcasting) receiver can be reduced, and the application requirements can be met.

Description

A kind of LDPC code translator and implementation method that reduces power consumption

Technical field

The code translator and the implementation method of the CMMB receiver chip in design of communications of the present invention field relate in particular to a kind of LDPC code translator and implementation method that reduces power consumption.

Background technology

China's digital mobile multimedia broadcasting (being called for short " CMMB ") standard is that China national General Bureau of Radio, Film and Television issues the China Mobile multimedia broadcasting industry standard in October, 2006; The CMMB standard fully takes into account the characteristics of mobile multi-media broadcasting service; Require high to the handheld device receiving sensitivity; Mobility and battery powered characteristics adopt state-of-the-art low density parity check code (LDPC) channel error correction coding, have improved antijamming capability and to ambulant support.

The LDPC sign indicating number is a kind of channel coding/decoding method that can approach the excellent performance of Shannon (Shannon) limit.Present research shows that the performance of the LDPC long code of non-rule can be superior to Turbo code.The LDPC sign indicating number has good range performance, little error code mistake, and code check is adjusted easily, and when code length is suitable, does not have error floor.

Nineteen sixty so far, many decoding algorithms of independently researching and proposing various LDPC.For example, sum-product algorithm (SPA), belief propagation algorithm (BPA), message pass-algorithm basic algorithms such as (MPA), and their other algorithms of extending out.These decoding algorithms can be summed up as the message pass-algorithm, and essence is a kind of iterative algorithm.Message is transmitted between variable node and check-node back and forth, thereby brings in constant renewal in.With the BP algorithm is example, and the decode procedure of LDPC sign indicating number is described.With under AWGN (additive white Gaussian noise) channel, when adopting BPSK (binary phase shift keying) modulation, make Y=[y ₁, y ₂, Ly _N] be the soft-decision receiving sequence of receiving terminal matched filter output.Log-likelihood ratio belief propagation (LLR-BP) decoding algorithm of LDPC sign indicating number is following:

(1) initialization:

$L\left(q_{\mathrm{ji}}^0\right)=L\left(P_i\right)=y_i$

And iterations k=1 is set.

(2) the calculation check node is to the external information of variable node:

$L\left(r_{\mathrm{ji}}^k\right)=\left(\underset{i^{\′}\∈R_j\backslash i}{\mathrm{\Π}}{\mathrm{\α}}_{i^{\′}j}^{k-1}\right)\·\mathrm{\φ}\left(\underset{i^{\′}\∈R_j\backslash i}{\mathrm{\Σ}}\mathrm{\φ}\left({\mathrm{\β}}_{i^{\′}j}^{k-1}\right)\right)$

Wherein: $\mathrm{\φ}\left(x\right)=-\mathrm{Log}\left(\mathrm{Tanh}\left(\frac{1}{2}x\right)\right).$

(3) calculate the external information of variable node to check-node:

$L\left(q_{\mathrm{ji}}^k\right)=L\left(P_i\right)+\underset{j^{\′}\∈C_i\backslash j}{\mathrm{\Σ}}L\left(r_{j^{\′}i}^k\right)$

(4) for all i, ask posterior probability:

$L\left(Q_i^k\right)=L\left(P_i\right)+\underset{j\∈C_i}{\mathrm{\Σ}}L\left(r_{\mathrm{ji}}^k\right)$

(5) for all i, carry out hard decision, produce decode results:

$\widehat{c_i}=\left\{\begin{array}{cc}1& \mathrm{ifL}\left(Q_i^k\left(1\right)\right)<0\\ 0& \mathrm{else}\end{array}\right.$

(6) repeating step 2 to 5, k=k+1.Perhaps reach maximum iteration time up to

; Finishing iteration decoding, and select whether to export decode results.

Can find out that from decode procedure decode procedure is divided into initialization, iterative decoding and three key steps of decoding output.The stop condition of iterative decoding is: when iterations reaches maximum iteration time, perhaps know decoding correctly the time through judgement, finishing iteration decoding is the output decode results also.

The error-correcting performance of LDPC sign indicating number is powerful, and its decoding complexity also compares higher.Realize considering that ldpc decoder will consume a large amount of computing units and memory cell from hardware.And this hardware spending can increase along with the code length of LDPC sign indicating number.On CMMB receiver baseband chip, the code length of LDPC sign indicating number is 9216, and ldpc decoder has occupied a very big area of whole baseband chip, and its power consumed also is maximum in all modules simultaneously.Therefore, how to reduce the ldpc decoder power consumption and become the of paramount importance problem of reduction CMMB receiver baseband chip power consumption.

Summary of the invention

The object of the invention provides a kind of LDPC code translator and implementation method that reduces power consumption; Adopt the dynamic electric voltage setting signal; Regulate the implementation of supply power voltage; Under the prerequisite that guarantees system data throughput and decoding performance, effectively reduce the decoder power consumption, thereby reduce the power consumption of CMMB receiver base band receiving chip.

A kind of LDPC code translator that reduces power consumption, this device is made up of PMU and decoder.Wherein decoder comprises initialization unit, iterative decoding unit, decoding output unit and encoded control unit.

Decoder is realized the decoding function of LDPC sign indicating number, and when decoder was in effective enabled, it comprised decoding state and two states of idle condition.

PMU is that decoder provides power supply.According to decoding state and idle condition, decoder provides the dynamic electric voltage setting signal in real time, according to the dynamic electric voltage setting signal of decoder, and PMU dynamic adjustments decoder supply power voltage.

The decoder initialization unit is used for realizing the decoding algorithm information initializing;

The iterative decoding unit be used for the calculation check node to the external information of variable node and variable node to the external information of check-node, calculate posterior probability and decoding judgement;

The decoding output unit is used to judge whether finishing iteration decoding, and the output decode results;

The encoded control unit is used to control initialization unit, iterative decoding unit and decoding output unit, and provides the dynamic electric voltage setting signal in real time according to decoding state and idle condition.

The present invention also provides a kind of LDPC code translator implementation method that reduces power consumption, comprises following content:

(1) when the decoding state, decoder is reading of data from bit deinterleaver;

Decoder is through the data read signal reading of data row decoding of going forward side by side from bit deinterleaver immediately, until with frame data of bit deinterleaver all decoding finish.

(2) when idle condition, calculate the free time of decoder, according to the free time size of decoder, decoder sends the dynamic electric voltage setting signal to PMU;

System is that decoder distributes every frame can use decoding time and time used, can calculate the free time of decoder at each frame.Write down the free time of the individual frame of continuous m (m is a default value), and choose wherein minimum value as free time of decoder.According to the free time size of decoder, decoder sends the dynamic electric voltage setting signal to PMU.

(3) after PMU receives the dynamic electric voltage setting signal, the dynamic adjustments supply power voltage.

When free time becomes big, suitably turn down operating voltage.Otherwise when free time, the time diminished, suitably heighten operating voltage.

Code translator provided by the invention and implementation method can effectively reduce the decoder power consumption under the prerequisite that guarantees system data throughput and decoding performance.

Description of drawings

Fig. 1 LDPC code translator circuit structure diagram that reduces power consumption provided by the invention

Fig. 2 LDPC code translator implementation method flow chart that reduces power consumption provided by the invention

Embodiment

Below in conjunction with each accompanying drawing the content of the present invention's proposition being carried out detailed description: Fig. 1 is the code translator circuit structure diagram, and Fig. 2 is the flow chart of its implementation method.

When decoder is in effective enabled, comprise two states of decoding state and idle condition.Decoder is realized the decoding function of LDPC sign indicating number in the CMMB baseband chip.According to decoding state and idle condition, decoder provides the dynamic electric voltage setting signal in real time.

The decoder initialization unit is accomplished the work of information initializing in the LDPC decoding algorithm.Iterative decoding unit calculation check node to the external information of check-node, calculates posterior probability and decoding judgement to the external information of variable node and variable node.The decoding output unit is used to judge whether finishing iteration decoding, and the output decode results.The encoded control unit is used to control the work of initialization unit, iterative decoding unit and decoding output unit, and provides the dynamic electric voltage setting signal in real time according to decoding state and idle condition.Its implementation process is:

At first calculate the free time of decoder.At the decoding state; Decoder is reading of data from the bit deinterleaver of prime; And after each decoding finished, decoder finished until frame data of bit deinterleaver are all deciphered through " data read signal " the reading of data row decoding of going forward side by side from bit deinterleaver immediately.State between this moment and the next frame data arrives ldpc decoder is called the ldpc decoder idle condition.According to system is that every frame that decoder distributes can be used decoding time and time used, can calculate the free time of decoder at each frame.Write down the free time of the individual frame of continuous m (m is a default value), and choose wherein minimum value as free time of decoder.

Secondly according to the free time size of decoder, decoder is set different dynamic electric voltages.When free time becomes big, suitably turn down operating voltage.Otherwise, when free time, the time diminished, suitably heighten operating voltage.Suppose that current free time is t _i, dynamically setting voltage is Vol_setting, the latter can set numerical value has n+1.With current free time t _iDelimit to n+1 interval, work as t _iWhen being positioned at the different time interval, select corresponding Vol_setting.The corresponding relation of the two as shown in the formula:

$\mathrm{Vol}\_\mathrm{seting}=\left\{\begin{array}{cc}{V}_{s0}& t_0>t_i\\ V_{s1}& t_1>t_i>t_0\\ M& \\ V_{\mathrm{sn}}& t_n>t_i>t_{n-1}\end{array}\right.$

PMU is that decoder provides power supply.Dynamic electric voltage according to decoder is set is regulated supply power voltage, can satisfy the requirement of decoder service behaviour, can reach the purpose of saving power consumption again.The process of code translator implementation method such as above-mentioned code translator circuit implementation procedure.

Claims (7)

1. the LDPC code translator that can reduce power consumption is made up of PMU and decoder, it is characterized in that said decoder provides the dynamic electric voltage setting signal in real time, and PMU is regulated the decoder supply power voltage according to the dynamic electric voltage setting signal.

2. a kind of LDPC code translator that reduces power consumption as claimed in claim 1 is characterized in that said decoder comprises initialization unit, iterative decoding unit, decoding output unit and encoded control unit.

3. a kind of LDPC code translator that reduces power consumption as claimed in claim 1 is characterized in that said decoder comprises decoding state and two states of idle condition when being in effective enabled.

4. according to claim 1 or claim 2 a kind of LDPC code translator that reduces power consumption is characterized in that said encoded control unit provides the dynamic electric voltage setting signal in real time according to decoder for decoding state and idle condition.

5. implementation method that can reduce the LDPC code translator of power consumption is characterized in that comprising following steps:

(1) in decoding during state, decoder reading of data from bit deinterleaver row decoding of going forward side by side, until with frame data of bit deinterleaver all decoding finish;

(2) when idle condition, calculate the free time of decoder, according to the free time size of decoder, decoder sends the dynamic electric voltage setting signal to PMU;

(3) after PMU receives the dynamic electric voltage setting signal, the dynamic adjustments supply power voltage.

6. a kind of implementation method that reduces the LDPC code translator of power consumption as claimed in claim 5; It is characterized in that said PMU dynamically adjusts supply power voltage at decoder and be: turn down the decoder operating voltage according to demand when free time becomes big, heightened the decoder operating voltage according to demand when free time, the time diminished.

7. a kind of implementation method that reduces the LDPC code translator of power consumption as claimed in claim 5; It is characterized in that system is that decoder distributes every frame can use decoding time and time used; Can calculate the free time of decoder at each frame; Write down the free time of a continuous m frame and choose wherein minimum value as free time of decoder, m is a default value.

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