CN102316559A - Low-power-consumption low density parity check code (LDPC) decoding device in China mobile multimedia broadcasting (CMMB) receiving machine and implementation method thereof - Google Patents

Abstract

The invention provides a low-power-consumption low density parity check code (LDPC) decoding device in a China mobile multimedia broadcasting (CMMB) receiving machine, which consists of an LDPC decoder, a power supply control unit and a control register unit, wherein the LDPC decoder consists of an initialization unit, an iterative decoding unit, a decoding output unit and a decoding control unit, and the power supply control unit provides an electricity supply power supply for the LDPC decoder and controls the work state of the LDPC decoder, so the goal of saving dynamic and electricity leakage power consumption is reached. Simultaneously, the control register unit stores and provides the base band chip control information and the internal state information before the dormancy state of the LDPC decoder for the LDPC decoder. Simultaneously, the invention also provides an implementation method of the low-power-consumption LDPC decoding device. Through the device and the method, the decoder electricity leakage power consumption and the dynamic power consumption can be effectively reduced, so the power consumption of a receiving machine chip in the application can be reduced.

Description

Low-power consumption LDPC code translator and implementation method in a kind of CMMB receiver

Technical field

The present invention relates to a kind of code translator and its implementation, relate in particular to low-power consumption LDPC code translator and implementation method in a kind of CMMB receiver.

Background technology

China's digital mobile multimedia broadcasting (being called for short " CMMB ") standard is the China Mobile multimedia broadcasting industry standard of China national General Bureau of Radio, Film and Television in October, 2006 promulgation, and this standard was in formal enforcement on November 1 in 2006.The CMMB standard fully takes into account the characteristics of mobile multi-media broadcasting service; Require high to the handheld device receiving sensitivity; Mobility and battery powered characteristics adopt state-of-the-art LDPC (low density parity check code) channel error correction coding, have improved antijamming capability and to ambulant support.

The LDPC sign indicating number is a kind of channel coding/decoding method that can approach Shannon (Shannon) limit and excellent performance.The LDPC sign indicating number occurred in nineteen sixty, was just paid close attention to widely after 35 years.Present research shows that the performance of the LDPC long code of non-rule can be superior to Turbo code.The LDPC sign indicating number has good range performance, little error code mistake, and code check is adjusted easily, and when code length is suitable, does not have error floor.

From nineteen sixty so far, many decoding algorithms of independently researching and proposing various LDPC.For example, sum-product algorithm (SPA), belief propagation algorithm (BPA), message pass-algorithm basic algorithms such as (MPA), and their other algorithms of extending out.These decoding algorithms can be summed up as the message pass-algorithm, and essence is a kind of iterative algorithm.Message is transmitted between variable node and check-node back and forth, thereby brings in constant renewal in.

With the BP algorithm is the decode procedure that example is explained the LDPC sign indicating number.With under AWGN (additive white Gaussian noise) channel, when adopting BPSK (binary system is shifted to) modulation, make Y=[y ₁, y ₂, L y _N] be the soft-decision receiving sequence of receiving terminal matched filter output.Log-likelihood ratio belief propagation (LLR-BP) decoding algorithm of LDPC sign indicating number is following:

(1) initialization:

$L\left(q_{\mathrm{ji}}^0\right)=L\left(P_i\right)=y_i$

And iterations k=1 is set.

(2) the calculation check node is to the external information of variable node:

$L\left(r_{\mathrm{ji}}^k\right)=\left(\underset{i\∈R_j/i}{\mathrm{\Π}}{\mathrm{\α}}_{\mathrm{ij}}^{k-1}\right)\·\mathrm{\φ}\left(\underset{i\∈R_j/i}{\mathrm{\Σ}}\mathrm{\φ}\left({\mathrm{\β}}_{\mathrm{ij}}^{k-1}\right)\right)$

Wherein:

(3) calculate the external information of variable node to check-node:

$L\left(q_{\mathrm{ji}}^k\right)=L\left(P_i\right)+\underset{j\∈C_i/j}{\mathrm{\Σk}}L\left(r_{\mathrm{ji}}^k\right)$

(4) for all i, ask posterior probability:

$L\left(Q_i^k\right)=L\left(P_i\right)+\underset{j\∈C_i}{\mathrm{\Σ}}L\left(r_{\mathrm{ji}}^k\right)$

(5) for all i, carry out hard decision, produce decode results:

${\hat{c}}_i=\left\{\begin{array}{cc}1& \mathrm{ifL}\left(Q_i^k\left(1\right)\right)<0\\ 0& \mathrm{else}\end{array}\right.$

(6) repeating step 2 to 5, k=k+1.Perhaps reach maximum iteration time up to

; Finishing iteration decoding, and select whether to export decode results.

Can find out that from above-mentioned steps whole decode procedure is divided into initialization, iterative decoding and three key steps of decoding output.The stop condition of iterative decoding is: when iterations reaches maximum iteration time, perhaps know decoding correctly the time through judgement, finishing iteration decoding, and output decode results.

The error-correcting performance of LDPC sign indicating number is powerful, and its decoding complexity also compares higher.Realize considering that ldpc decoder will consume a large amount of computing units and memory cell from hardware.And this hardware spending can increase along with the code length of LDPC sign indicating number.Specific to CMMB receiver baseband chip, the code length of LDPC sign indicating number is 9216, and ldpc decoder has occupied a very big area of whole baseband chip, and its power consumed also is maximum in all modules simultaneously.Therefore, reduction ldpc decoder power consumption is most important to reducing CMMB receiver baseband chip power consumption.

Along with the development of semiconductor process techniques, especially adopt 90nm, 65nm and littler live width technology after, electric leakage has become the subject matter of chip power-consumption.Therefore, to ldpc decoder in the CMMB receiver baseband chip, need to propose effectively to solve the low-power consumption solution of electric leakage problem.

Summary of the invention

The object of the invention provides low-power consumption LDPC code translator and its implementation of a kind of CMMB receiver.This device can effectively reduce decoder electricity leakage power dissipation and dynamic power consumption under the prerequisite that guarantees the system data throughput, thereby reduces the power consumption of base band receiving chip.

Low-power consumption LDPC code translator in a kind of CMMB receiver is made up of ldpc decoder, power control unit and control register unit.

Ldpc decoder, the decoding function of LDPC sign indicating number comprises two states of decoding state and resting state in the realization CMMB baseband chip.

Power control unit is used to ldpc decoder power supply is provided, thereby the operating state of control ldpc decoder reaches and saves dynamically and the purpose of electricity leakage power dissipation.

The control register unit is used for the ldpc decoder preservation and the baseband chip control information is provided, and the internal state information of ldpc decoder before resting state.

Ldpc decoder is made up of initialization unit, iterative decoding unit, decoding output unit and encoded control unit.

The present invention also provides the implementation method of low-power consumption LDPC code translator in a kind of receiver, comprises following content:

(1) power control unit provides power supply to ldpc decoder;

(2) ldpc decoder is through data read signal reading of data from prime bit deinterleaver row decoding of going forward side by side, until with frame data of bit deinterleaver all decoding finish;

(3) ldpc decoder sends this frame coding end signal to power control unit, simultaneously the decoder internal state information is sent to the register controlled unit and preserves;

(4) PMU turn-offs the power supply of ldpc decoder after receiving this frame coding end signal, and ldpc decoder gets into resting state;

(5) receive the next frame index signal that bit deinterleaver sends after, PMU is opened the ldpc decoder power supply, PMU will be deciphered enabling signal and send to the register controlled unit;

(6) receive the decoding enabling signal after, the register controlled unit sends to ldpc decoder with the state information of preserving before the baseband chip control information, resting state, recovers ldpc decoder internal control state, ldpc decoder gets into the decoding state once more.

Realization of the present invention can effectively reduce decoder electricity leakage power dissipation and dynamic power consumption, thereby reduces the power consumption of receiver chip in the application.

Description of drawings

Fig. 1 is the circuit structure diagram of low-power consumption LDPC code translator in a kind of receiver

Fig. 2 is a low-power consumption LDPC code translator implementation method basic flow sheet in a kind of receiver

Specific embodiments

Below in conjunction with each accompanying drawing content provided by the present invention is carried out detailed description.

Fig. 1 is the circuit structure diagram of low-power consumption LDPC code translator according to the invention, and whole code translator is made up of ldpc decoder, power control unit and control register unit.Wherein ldpc decoder comprises initialization unit, iterative decoding unit, decoding output unit and encoded control unit.Ldpc decoder is realized the decoding function of LDPC sign indicating number in the CMMB baseband chip, comprises two states of decoding state and resting state.

Initialization unit is accomplished the work of information initializing in the LDPC decoding algorithm.Iterative decoding unit calculation check node to the external information of check-node, calculates posterior probability and decoding judgement to the external information of variable node and variable node.The decoding output unit is used to judge whether finishing iteration decoding, and the output decode results.The processing of encoded control unit controls initialization unit, iterative decoding unit and decoding output unit, and provide data read signal in real time according to the decoding state.

Power control unit is that ldpc decoder provides power supply, and the operating state of control ldpc decoder is saved dynamically and the purpose of electricity leakage power dissipation thereby reach.Accomplish the decoding of bit interleaver one all data of frame when ldpc decoder after, power control unit turn-offs the power supply of ldpc decoder, makes it get into resting state, has promptly saved dynamic power consumption, has effectively saved electricity leakage power dissipation again.When bit interleaver next frame data arrives, power control unit is opened the power supply of ldpc decoder, makes it get into the decoding state.

The control register unit is that baseband chip control information and the ldpc decoder internal state information before resting state is preserved and provided to ldpc decoder.After ldpc decoder got into resting state, control information that baseband chip provides and ldpc decoder internal state information all can be lost.Therefore ldpc decoder gets into before the resting state accomplishing this frame coding, can its inner thematic information be saved in the control register unit.When ldpc decoder returned to the decoding state, the register controlled unit sent to ldpc decoder with the state information of preserving before baseband chip control information, the resting state, recovered ldpc decoder internal control state.

The implementation method of the low-power consumption LDPC code translator that proposes below in conjunction with the 2 couples of the present invention of accompanying drawing is carried out detailed description.

At first power control unit provides power supply to ldpc decoder, and this moment, the operating state of ldpc decoder had two kinds, decoding state and resting state.

In the decoding state, ldpc decoder is reading of data from the bit deinterleaver of prime.After each decoding finished, ldpc decoder was through the data read signal reading of data row decoding of going forward side by side from bit deinterleaver immediately, until with frame data of bit deinterleaver all decoding finish.At this moment, ldpc decoder sends " this frame coding end signal " to power control unit, simultaneously the decoder internal state information is sent to the register controlled unit and preserves.

PMU turn-offs the power supply of ldpc decoder after receiving this frame coding end signal, to save dynamically and electricity leakage power dissipation, this moment, ldpc decoder got into resting state.

After the next frame index signal that receives the bit deinterleaver transmission, PMU can be opened the ldpc decoder power supply.This moment, the register controlled unit sent to ldpc decoder with the state information of preserving before baseband chip control information, the resting state, recovered ldpc decoder internal control state.Ldpc decoder gets into the decoding state again.

Claims (6)

1. low-power consumption LDPC code translator in the CMMB receiver is made up of ldpc decoder, power control unit and control register unit.

2. low-power consumption code translator in a kind of CMMB receiver as claimed in claim 1 is characterized in that: said ldpc decoder is made up of initialization unit, iterative decoding unit, decoding output unit and encoded control unit.

3. low-power consumption code translator in according to claim 1 or claim 2 a kind of CMMB receiver, it is characterized in that: said ldpc decoder has decoding state and two kinds of operating states of resting state.

4. low-power consumption code translator in a kind of CMMB receiver as claimed in claim 1 is characterized in that: said power control unit is controlled the operating state of ldpc decoder through power supply is provided for ldpc decoder.

5. low-power consumption code translator in a kind of CMMB receiver as claimed in claim 1 is characterized in that: said encoded control unit is that control information and the ldpc decoder internal state information before resting state is preserved and provided to ldpc decoder.

6. the implementation method of low-power consumption LDPC code translator in the CMMB receiver is characterized in that: comprise following performing step:

(1) power control unit provides power supply to ldpc decoder;

(2) ldpc decoder is through data read signal reading of data from prime bit deinterleaver row decoding of going forward side by side, until with frame data of bit deinterleaver all decoding finish;

(3) ldpc decoder sends this frame coding end signal to power control unit, simultaneously the decoder internal state information is sent to the register controlled unit and preserves;

(4) PMU turn-offs the power supply of ldpc decoder after receiving this frame coding end signal, and ldpc decoder gets into resting state;

(5) receive the next frame index signal that bit deinterleaver sends after, PMU is opened the ldpc decoder power supply, PMU will be deciphered enabling signal and send to the register controlled unit;

(6) receive the decoding enabling signal after, the register controlled unit sends to ldpc decoder with the state information of preserving before the baseband chip control information, resting state, recovers ldpc decoder internal control state, ldpc decoder gets into the decoding state once more.

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