CN102316559B - Low-power-consumption low density parity check code (LDPC) decoding device in China mobile multimedia broadcasting (CMMB) receiving machine and implementation method thereof - Google Patents

Abstract

The invention provides a low-power-consumption low density parity check code (LDPC) decoding device in a China mobile multimedia broadcasting (CMMB) receiving machine, which consists of an LDPC decoder, a power supply management unit and a control register unit, wherein the LDPC decoder consists of an initialization unit, an iterative decoding unit, a decoding output unit and a decoding control unit, and the power supply management unit provides an electricity supply power supply for the LDPC decoder and controls the work state of the LDPC decoder, so the goal of saving dynamic and electricity leakage power consumption is reached. Simultaneously, the control register unit stores and provides the base band chip control information and the internal state information before the dormancy state of the LDPC decoder for the LDPC decoder. Simultaneously, the invention also provides an implementation method of the low-power-consumption LDPC decoding device. Through the device and the method, the decoder electricity leakage power consumption and the dynamic power consumption can be effectively reduced, so the power consumption of a receiving machine chip in the application can be reduced.

Description

The implementation method of low-power consumption LDPC code translator in a kind of CMMB receiver

Technical field

The present invention relates to a kind of implementation method of code translator, relate in particular to the implementation method of the low-power consumption LDPC code translator in a kind of CMMB receiver.

Background technology

Chinese Digital Mobile Multimedia Broadcasting (being called for short " CMMB ") standard is the China Mobile multimedia broadcasting industry standard that China national General Bureau of Radio, Film and Television promulgated in October, 2006, and this standard is formal enforcement in 1 day November in 2006.CMMB standard fully takes into account the feature of mobile multi-media broadcasting service, for handheld device receiving sensitivity, require high, mobility and battery powered feature, adopt state-of-the-art LDPC (low density parity check code) channel error correction coding, improved antijamming capability and to ambulant support.

LDPC code is a kind of channel coding/decoding method that can approach Shannon (Shannon) limit and excellent performance.LDPC code occurred in nineteen sixty, after 35 years, was just paid close attention to widely.Current research shows, the performance of irregular LDPC long code can be better than Turbo code.LDPC code has good range performance, little error code mistake, and code check is easily adjusted, and does not have error floor when code length is suitable.

From nineteen sixty so far, many decoding algorithms of independently researching and proposing various LDPC.For example, the basic algorithms such as sum-product algorithm (SPA), belief propagation algorithm (BPA), message pass-algorithm (MPA), and their other algorithms of extending out.These decoding algorithms can be summed up as message pass-algorithm, and essence is a kind of iterative algorithm.Message is transmitted back and forth between variable node and check-node, thereby constantly updates.

The BP algorithm of take illustrates the decode procedure of LDPC code as example.With under AWGN (additive white Gaussian noise) channel, when adopting BPSK (binary system is shifted to) modulation, make Y=[y ₁, y ₂, L y _n] be the soft-decision receiving sequence of receiving terminal matched filter output.Log-likelihood ratio belief propagation (LLR-BP) decoding algorithm of LDPC code is as follows:

(1) initialization:

$L\left(q_{\mathrm{ji}}^0\right)=L\left(P_i\right)=y_i$

And iterations k=1 is set.

(2) calculation check node is to the external information of variable node:

$L\left(r_{\mathrm{ji}}^k\right)=\left(\underset{i^{\′}\∈R_j\backslash i}{\mathrm{\Π}}{\mathrm{\α}}_{i^{\′}j}^{k-1}\right)\·\mathrm{\φ}\left(\underset{i^{\′}\∈R_j\backslash i}{\mathrm{\Σ}}\mathrm{\φ}\left({\mathrm{\β}}_{i^{\′}j}^{k-1}\right)\right)$

Wherein: $\mathrm{\φ}\left(x\right)=-\log \left(\tanh \left(\frac{1}{2}x\right)\right).$

(3) calculate variable node to the external information of check-node:

$L\left(q_{\mathrm{ji}}^k\right)=L\left(P_i\right)+\underset{j^{\′}\∈C_i\backslash j}{\mathrm{\Σ}}L\left(r_{j^{\′}i}^k\right)$

(4) for all i, ask posterior probability:

$L\left(Q_i^k\right)=L\left(P_i\right)+\underset{j\∈C_i}{\mathrm{\Σ}}L\left(r_{\mathrm{ji}}^k\right)$

(5) for all i, carry out hard decision, produce decode results:

${\hat{c}}_i=\left\{\begin{array}{cc}1& \mathrm{ifL}\left(Q_i^k\left(1\right)\right)<0\\ 0& \mathrm{else}\end{array}\right.$

(6) repeating step 2 is to 5, k=k+1.Until or reach maximum iteration time, finishing iteration decoding, and select whether to export decode results.

From above-mentioned steps, can find out, whole decode procedure is divided into initialization, iterative decoding and three key steps of decoding output.The stop condition of iterative decoding is: when iterations reaches maximum iteration time, or know that by judgement decoding is correctly time, and finishing iteration decoding, and export decode results.

The error-correcting performance of LDPC code is powerful, and its decoding complexity is also relatively high.From hardware, realize and considering, ldpc decoder will consume a large amount of computing units and memory cell.And this hardware spending can increase along with the code length of LDPC code.Specific to CMMB receiver baseband chip, the code length of LDPC code is 9216, and ldpc decoder has occupied the area that whole baseband chip is very large, and the power consumption of its consumption is simultaneously also maximum in all modules.Therefore, reduction ldpc decoder power consumption is most important to reducing CMMB receiver baseband chip power consumption.

Along with the development of semiconductor process techniques, especially adopt after 90nm, 65nm and less live width technique, electric leakage has become the subject matter of chip power-consumption.Therefore,, for ldpc decoder in CMMB receiver baseband chip, need to propose effectively to solve the low-power consumption solution of electric leakage problem.

Summary of the invention

The object of the invention provides low-power consumption LDPC code translator and its implementation of a kind of CMMB receiver.This device can guarantee, under the prerequisite of system data throughput, effectively to reduce decoder electricity leakage power dissipation and dynamic power consumption, thereby reduces the power consumption of base band receiving chip.

A low-power consumption LDPC code translator in CMMB receiver, by ldpc decoder, Power Management Unit and control register cell formation.

Ldpc decoder, realizes the decoding function of LDPC code in CMMB baseband chip, comprises two states of decoding state and resting state.

Power Management Unit, is used to ldpc decoder that power supply is provided, thereby controls the operating state of ldpc decoder, reaches and saves dynamically and the object of electricity leakage power dissipation.

Control register unit, preserves and baseband chip control information is provided for ldpc decoder, and the internal state information of ldpc decoder before resting state.

Ldpc decoder is by initialization unit, iterative decoding unit, decoding output unit and encoded control cell formation.

The present invention also provides the implementation method of low-power consumption LDPC code translator in a kind of receiver, comprises following content:

(1) Power Management Unit provides power supply to ldpc decoder;

(2) ldpc decoder is by data read signal reading out data from prime bit deinterleaver row decoding of going forward side by side, until the whole decoding of frame data of bit deinterleaver is complete;

(3) ldpc decoder sends this frame coding end signal to Power Management Unit, decoder internal state information is sent to register control unit simultaneously and preserves;

(4) Power Management Unit, after receiving this frame coding end signal, is turn-offed the power supply of ldpc decoder, and ldpc decoder enters resting state;

(5) receive after the next frame index signal of bit deinterleaver transmission, Power Management Unit is opened ldpc decoder power supply, and Power Management Unit sends to register control unit by decoding enabling signal;

(6) receive after decoding enabling signal, register control unit sends to ldpc decoder by the state information of preserving before baseband chip control information, resting state, recovers ldpc decoder internal control state, and ldpc decoder enters decoding state again.

Realization of the present invention, can effectively reduce decoder electricity leakage power dissipation and dynamic power consumption, thereby reduces the power consumption of receiver chip in application.

Accompanying drawing explanation

Fig. 1 is the circuit structure diagram of low-power consumption LDPC code translator in a kind of receiver

Fig. 2 is low-power consumption LDPC code translator implementation method basic flow sheet in a kind of receiver

Specific embodiments

Below in conjunction with each accompanying drawing, content provided by the present invention is described in detail.

Fig. 1 is the circuit structure diagram of low-power consumption LDPC code translator of the present invention, and whole code translator is by ldpc decoder, Power Management Unit and control register cell formation.Wherein ldpc decoder comprises initialization unit, iterative decoding unit, decoding output unit and encoded control unit.Ldpc decoder is realized the decoding function of LDPC code in CMMB baseband chip, comprises two states of decoding state and resting state.

Initialization unit completes the work of information initializing in LDPC decoding algorithm.Iterative decoding unit calculation check node, to the external information of variable node and variable node to the external information of check-node, calculates posterior probability decoding judgement.Decoding output unit is used for judging whether finishing iteration decoding, and exports decode results.The processing of encoded control unit controls initialization unit, iterative decoding unit and decoding output unit, and provide in real time data read signal according to decoding state.

Power Management Unit provides power supply for ldpc decoder, controls the operating state of ldpc decoder, thereby reach, saves dynamically and the object of electricity leakage power dissipation.When ldpc decoder completes after the decoding of all data of bit interleaver one frame, Power Management Unit is turn-offed the power supply of ldpc decoder, makes it enter resting state, has saved dynamic power consumption, has effectively saved again electricity leakage power dissipation.When bit interleaver next frame data arrive, Power Management Unit is opened the power supply of ldpc decoder, makes it enter decoding state.

Control register unit is for ldpc decoder preservation and baseband chip control information and the ldpc decoder internal state information before resting state is provided.At ldpc decoder, enter after resting state, the control information that baseband chip provides and ldpc decoder internal state information all can be lost.Therefore ldpc decoder completes this frame coding, before entering resting state, its inner thematic information can be saved in control register unit.When ldpc decoder returns to decoding state, register control unit sends to ldpc decoder by the state information of preserving before baseband chip control information, resting state, recovers ldpc decoder internal control state.

The implementation method of the low-power consumption LDPC code translator proposing below in conjunction with 2 couples of the present invention of accompanying drawing is described in detail.

First Power Management Unit provides power supply to ldpc decoder, and now the operating state of ldpc decoder has two kinds, decoding state and resting state.

In decoding state, ldpc decoder is reading out data from the bit deinterleaver of prime.After each decoding finishes, ldpc decoder is by the data read signal reading out data row decoding of going forward side by side from bit deinterleaver immediately, until the whole decoding of frame data of bit deinterleaver is complete.Now, ldpc decoder sends " this frame coding end signal " to Power Management Unit, decoder internal state information is sent to register control unit simultaneously and preserves.

Power Management Unit, after receiving this frame coding end signal, is turn-offed the power supply of ldpc decoder, and to save dynamically and electricity leakage power dissipation, now ldpc decoder enters resting state.

After receiving the next frame index signal of bit deinterleaver transmission, Power Management Unit can be opened ldpc decoder power supply.Now register control unit sends to ldpc decoder by the state information of preserving before baseband chip control information, resting state, recovers ldpc decoder internal control state.Ldpc decoder reenters decoding state.

Claims (1)

1. an implementation method for low-power consumption LDPC code translator in CMMB receiver, is characterized in that: comprise following performing step:

(1) Power Management Unit provides power supply to ldpc decoder;

(2) ldpc decoder is by data read signal reading out data from prime bit deinterleaver row decoding of going forward side by side, until the whole decoding of frame data of bit deinterleaver is complete;

(3) ldpc decoder sends this frame coding end signal to Power Management Unit, decoder internal state information is sent to register control unit simultaneously and preserves;

(4) Power Management Unit, after receiving this frame coding end signal, is turn-offed the power supply of ldpc decoder, and ldpc decoder enters resting state;

(5) receive after the next frame index signal of bit deinterleaver transmission, Power Management Unit is opened ldpc decoder power supply, and Power Management Unit sends to register control unit by decoding enabling signal;

(6) receive after decoding enabling signal, register control unit sends to ldpc decoder by the state information of preserving before baseband chip control information, resting state, recovers ldpc decoder internal control state, and ldpc decoder enters decoding state again.