CN102610556A - Method for reducing cracking phenomenon of double-layer front metal dielectric layer - Google Patents
Method for reducing cracking phenomenon of double-layer front metal dielectric layer Download PDFInfo
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- CN102610556A CN102610556A CN2012100148052A CN201210014805A CN102610556A CN 102610556 A CN102610556 A CN 102610556A CN 2012100148052 A CN2012100148052 A CN 2012100148052A CN 201210014805 A CN201210014805 A CN 201210014805A CN 102610556 A CN102610556 A CN 102610556A
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Abstract
The invention provides a method for reducing the cracking phenomenon of a double-layer front metal dielectric layer and an MOS (Metal-Oxide Semiconductor) device prepared by the method. A transition layer is formed between a first metal dielectric layer and a second metal dielectric layer, wherein the cohesiveness between the material of the transition layer and the material of the second metal dielectric layer is better than that between the material of the transition layer and the material of the first metal dielectric layer; as the transition layer is arranged on the first metal dielectric layer through in-situ growth without vacuum breaking, good cohesiveness is generated between the transition layer and the first metal dielectric layer; and meanwhile, the nature of the transition layer is close to that of the second metal dielectric layer, and excellent cohesiveness exists between the transition layer and the second metal dielectric layer, so that the cracking between two layers of membranes of the double-layer front metal dielectric layer is alleviated or eliminated.
Description
Technical field
The present invention relates to a kind of method of improving performance of semiconductor device, relate in particular to the method for double-deck preceding metal and dielectric matter layer cracking in a kind of MOS of preventing device.
Background technology
Along with the CMOS technology is pressed the mole law and high speed development, after the critical size of device had been contracted under the 90nm, deposition PMD need adopt high density plasma CVD (HDP CVD) to form usually.This method is that deposition and etching are carried out simultaneously, and it needs higher plasma density and more powerful radio-frequency power supply, and used radio-frequency power is more than 5000 watts usually.
Chinese patent CN1216407C has disclosed the manufacturing approach that a kind of dielectric layer between metal layers uniformity of improving high density plasma CVD method formed thereby is controlled not good situation; At first be to be manufactured with at the semiconductor-based end of a plurality of internal connecting lines, form all good thin PE-TEOS of a uniformity and tack altogether.Then, on first oxide layer, form second oxide layer with the high-density plasma chemical vapor phase method, and insert the gap between those internal connecting lines.At last, on second oxide layer, form the 3rd oxide layer with the plasma enhanced chemical vapor deposition method again.According to the method for this invention, not only can reach splendid gap filling effect, also can improve the situation of dielectric layer bad.
Chinese patent CN100454497C relates to a kind of method of blind in the semiconductor-based end.Substrate is provided in reative cell and contains the admixture of gas of at least a deuteride.Make the reaction of this admixture of gas and through the layer deposition of carrying out simultaneously be etched in and form material layer in the substrate.This material layer blind makes that the material in the slit is very close to each other basically.This invention comprises providing and improves the inhomogeneity method of deposition rate.Material is at least a D that is selected from
2, HD, DT, T
2With the existence condition deposit of the gas of TH from the teeth outwards.Under the substantially the same in other respects condition of the extent of deviation that net deposition rate between depositional stage has across the surface with respect to using H
2The extent of deviation that deposition takes place has obtained detectable improvement.
Chinese patent CN1299358C provides a kind of embedded with metal internal connection-wire structure with double shielding layer, includes semiconductor wafer; One dielectric layer is located on this semiconductor wafer, is formed with one in this dielectric layer and inlays pothole; One bronze medal plain conductor is located at this and is inlayed in the pothole, and this copper plain conductor has the upper surface that a process CMP ground, and this upper surface is flushed with this dielectric layer approximately; And the pair of lamina protective layer, comprise that a HDPCVD silicon nitride layer and a doped silicon carbide (doped silicon carbide) upper strata is overlying on the upper surface of this copper plain conductor.This upper surface of this copper metal carbonyl conducting layer is after CMP grinds, with hydrogen gas plasma or the preliminary treatment of ammonia (ammonia) plasma.This high density plasma CVD silicon nitride layer is that high density plasma CVD (HDPCVD) the method deposition that is utilized under 350 ℃ forms.
But utilize the HDP method when forming PMD,, in actual production process, can cause damage, make its leakage current increase the reliability decrease of device grid oxic horizon because its plasma density is high, power is big and time growth is long.
In order to reduce before the deposition during metal and dielectric matter layer plasma to the damage of grid oxic horizon; Can adopt double-deck preceding layer metal deposition method; For example, ground floor is the PSG (phosphorosilicate glass) of HDP method deposition, and the second layer is the SiO of plasma enhanced chemical vapor deposition method (PECVD) deposition
2, wherein the P among the HDP PSG mainly is used for catching the metal ion that is free in the device.
Yet this first metal dielectric layer and two kinds of films of different nature of second metal dielectric layer are bad at its interfacial bond property, in follow-up procedure of processing process, are easy to generate the phenomenon of cracking.
Summary of the invention
For alleviate or eliminate double-deck before cracking phenomena between the metal level dielectric layer; The invention provides a kind of method that reduces double-deck preceding metal and dielectric matter layer cracking phenomena; The present invention is after the plated metal dielectric layer is accomplished; Growth in situ one deck transition zone utilizes this method, can eliminate the phenomenon that double-deck preceding metal and dielectric matter layer ftractures between double-layer films.
Therefore, first purpose of the present invention provides a kind of method that reduces double-deck preceding metal and dielectric matter layer cracking phenomena, and particularly, this method step comprises:
Step 1 provides the substrate with NMOS and/or PMOS zone, deposition etch barrier layer on said substrate;
Step 2, deposition first metal dielectric layer on said barrier layer;
Step 3, in-situ deposition one deck transition zone on first metal dielectric layer;
Step 4, deposition second metal dielectric layer on said transition zone;
Step 5, the thickness that second metal dielectric layer is carried out cmp to designing requirement;
Wherein, the caking property between the transition zone material and the second metal dielectric layer material is greater than the caking property between the transition zone and the first metal dielectric layer material.
Second purpose of the present invention provides a kind of MOS device; Comprise substrate; Comprise NMOS and/or PMOS zone in the said substrate; On said substrate, deposit etch stop layer, first metal dielectric layer successively, the transition zone of one deck growth in situ is arranged on said first metal dielectric layer, above said transition zone, deposit second metal dielectric layer; Wherein, the caking property between the transition zone material and the second metal dielectric layer material is greater than the caking property between the transition zone and the first metal dielectric layer material.
In method that the present invention is above-mentioned and the MOS device, the said first metal dielectric layer material is preferably the phosphoric acid silex glass, especially the phosphorosilicate glass of high-density plasma prepared (HDP-PSG).Wherein, P content is preferably 2 ~ 8%.
Wherein, the first metal dielectric layer depositing temperature be preferably≤500 ℃.
In method that the present invention is above-mentioned and the MOS device, said transition zone material is preferably silicon dioxide, and said first metal and dielectric layer thickness and said transition region thickness ratio are preferably 800 ~ 2000:50 ~ 500, and are preferably 800 ~ 2000 and 50 ~ 500 respectively.
Transition zone in-situ deposition condition optimization according to the invention is for comprising:
Bottom radio-frequency power (LF Power) 3000 ~ 5000W;
Middle part radio-frequency power (MF Power) 1000 ~ 2000W;
High portion radio-frequency power (HF Power) 4000 ~ 6000W;
Silane flow rate (Silane Flow) 200 ~ 300sccm;
Helium gas flow (Helium Flow) 200 ~ 300sccm;
Top oxygen throughput (O2-top Flow) 300 ~ 600sccm;
Sidepiece oxygen flow (O2-side Flow) 100 ~ 300sccm.
In method that the present invention is above-mentioned and the MOS device, the said second metal dielectric layer material is preferably silicon dioxide, and the deposition process on transition zone is preferably CVD, and better deposition process is PECVD.
Wherein, the second metal dielectric layer depositing temperature is preferably 300 ~ 500 ℃.
Wherein, the ratio between the second metal dielectric layer deposit thickness and the first metal dielectric layer deposit thickness is preferably 3000 ~ 10000:800 ~ 2000, the second metal dielectric layer deposit thickness and is preferably 3000 ~ 10000.
In method that the present invention is above-mentioned and the MOS device, said etch stop layer can be silicon nitride, carborundum, carbonitride of silicium, polymer barrier layer, TEOS barrier layer etc.
The method of double-deck preceding metal and dielectric matter layer cracking phenomena and the MOS device of said method preparation of reducing provided by the invention; Between first metal dielectric layer and second metal dielectric layer; Be formed with transition zone; Through good adhesive property between transition zone and first metal dielectric layer and second metal dielectric layer, first metal dielectric layer is connected with second metal dielectric layer, can prevent or alleviate double-deck preceding metal and dielectric matter layer cracking phenomena effectively.
Description of drawings
Fig. 1 reduces the schematic flow sheet of the method for double-deck preceding metal and dielectric matter layer cracking phenomena for the present invention;
Fig. 2 is a MOS device architecture sketch map of the present invention.
Embodiment
The invention provides a kind of method of double-deck preceding metal and dielectric matter layer cracking phenomena and MOS device of said method preparation of reducing; Between first metal dielectric layer and second metal dielectric layer; Be formed with transition zone; Wherein, the caking property between the transition zone material and the second metal dielectric layer material is greater than the caking property between the transition zone and the first metal dielectric layer material.
Though between the transition zone and the first metal dielectric layer material adhesive property not as and the second metal dielectric layer material between caking property; But because the transition zone growth in situ is on first metal dielectric layer; Do not have vacuum breaker, institute is so that produced advantages of good caking property between the transition zone and first metal dielectric layer; Simultaneously transition zone is approaching with the second metal dielectric layer character, also has good caking property between transition zone and second metal dielectric layer, thus alleviation or eliminated the cracking between the double-deck preceding metal dielectric layer double-layer films.
See figures.1.and.2 below; Through specific embodiment to the present invention reduce double-deck before method and the MOS device of said method preparation of metal and dielectric matter layer cracking phenomena carry out detailed introduction and description; So that better understand the present invention; But should be understood that following embodiment does not limit the scope of the invention.
Embodiment 1
Step 1 provides the substrate that contains NMOS and/or PMOS zone, and deposited barrier layer
A kind of substrate 1 of cmos device is provided, includes NMOS and PMOS zone in the substrate.
Adopt the method for chemical vapor deposition (CVD), deposition one deck silicon nitride barrier 2 on substrate 1.
Step 2, deposition first metal dielectric layer above the barrier layer
Under 400 ℃ of conditions, deposition one deck material is first metal dielectric layer 3 of HDP PSG above silicon nitride barrier, and to control first metal dielectric layer 3 be that thickness is 800.
Wherein, P content is 5% among the HDP PSG.
Step 3, in-situ deposition transition zone on first metal dielectric layer
After the first metal layer growth is accomplished, the not phosphorous silicon dioxide transition zone 4 of in-situ deposition on the first metal layer, the in-situ deposition condition of silicon dioxide transition zone 4 is following:
Bottom radio-frequency power (LF Power) 4000W;
Middle part radio-frequency power (MF Power) 2000W;
High portion radio-frequency power (HF Power) 5000W;
Silane flow rate (Silane Flow) 200sccm;
Helium gas flow (Helium Flow) 200sccm;
Top oxygen throughput (O2-top Flow) 600sccm;
Sidepiece oxygen flow (O2-side Flow) 200sccm.
The thickness of control silicon dioxide transition zone 4 is 200.
Step 4, deposition second metal dielectric layer on transition zone
Adopt the PECVD method, under 350 ℃ of conditions, the deposition material is second metal dielectric layer 5 of silicon dioxide on transition zone 4.Because also need carry out planarization in the subsequent handling, therefore, the thickness of second metal dielectric layer 5 should be bigger, in the present embodiment, the thickness of controlling second metal dielectric layer 5 is 3000.
Step 5 is carried out cmp to second metal dielectric layer, until the thickness that reaches designing requirement
Cmp is a state of the art, therefore, repeats no more in the present embodiment.
With reference to Fig. 2, the MOS device of present embodiment preparation is a cmos device, comprises substrate 1, and substrate contains PMOS zone 11 and nmos area territory 12, and PMOS zone 11 is separated by shallow trench 13 with nmos area territory 12.
Etch stop layer 2 is arranged on substrate 1, and barrier layer 2 covers substrate 1 (comprising PMOS zone 11 and nmos area territory), is that the thickness of first metal dielectric layer, 3, the first metal dielectric layers 3 of HDP HSG material is 800 on the barrier layer 2, and P content is 5%.
The silicon dioxide transition zone 4 that one deck in-situ deposition is arranged on first metal dielectric layer 3, the thickness of transition zone 4 are 200, are second metal dielectric layer 5 of silicon dioxide material on the transition zone 4.
Because transition zone 4 in-situ depositions on HDP PSG, do not have vacuum breaker, and are better with the adhesive property of first metal dielectric layer 3, transition zone 4 is identical material with second metal level 5 simultaneously, so performance is identical, has good adhesive property.
Side in nmos area territory 12 also is provided with tungsten plug 14.
Embodiment 2
Step 1 provides the substrate that contains NMOS and/or PMOS zone, and deposited barrier layer
This step is implemented with reference to the said method of step 1 among the embodiment 1.
Step 2, deposition first metal dielectric layer above the barrier layer
Under 480 ℃ of conditions, deposition one deck material is first metal dielectric layer 3 of HDP PSG above silicon nitride barrier, and to control first metal dielectric layer 3 be that thickness is 1800.
Wherein, P content is 3% among the HDP PSG.
Step 3, in-situ deposition transition zone on first metal dielectric layer
After the first metal layer growth is accomplished, the not phosphorous silicon dioxide transition zone 4 of in-situ deposition on the first metal layer, the in-situ deposition condition of silicon dioxide transition zone 4 is following:
Bottom radio-frequency power (LF Power) 4700W;
Middle part radio-frequency power (MF Power) 1500W;
High portion radio-frequency power (HF Power) 4000W;
Silane flow rate (Silane Flow) 200sccm;
Helium gas flow (Helium Flow) 250sccm;
Top oxygen throughput (O2-top Flow) 400sccm;
Sidepiece oxygen flow (O2-side Flow) 230sccm.
The thickness of control silicon dioxide transition zone 4 is 60.
Step 4, deposition second metal dielectric layer on transition zone
Adopt the PECVD method, under 300 ℃ of conditions, the deposition material is second metal dielectric layer 5 of silicon dioxide on transition zone 4.Because also need carry out planarization in the subsequent handling, therefore, the thickness of second metal dielectric layer 5 should be bigger, in the present embodiment, the thickness of controlling second metal dielectric layer 5 is 8000.
Step 5 is carried out cmp to second metal dielectric layer, until the thickness that reaches designing requirement
Cmp is a state of the art, therefore, repeats no more in the present embodiment.
With reference to Fig. 2, the MOS device of present embodiment preparation is a cmos device, and the thickness of first metal dielectric layer 3 is 1800, and P content is 3%.
The silicon dioxide transition zone 4 that one deck in-situ deposition is arranged on first metal dielectric layer 3, the thickness of transition zone 4 are 60, are second metal dielectric layer 5 of silicon dioxide material on the transition zone 4.
Embodiment 3
Step 1 provides the substrate that contains NMOS and/or PMOS zone, and deposited barrier layer
This step is implemented with reference to the said method of step 1 among the embodiment 1.
Step 2, deposition first metal dielectric layer above the barrier layer
Under 450 ℃ of conditions, deposition one deck material is first metal dielectric layer 3 of HDP PSG above silicon nitride barrier, and to control first metal dielectric layer 3 be that thickness is 1000.
Wherein, P content is 6% among the HDP PSG.
Step 3, in-situ deposition transition zone on first metal dielectric layer
After the first metal layer growth is accomplished, the not phosphorous silicon dioxide transition zone 4 of in-situ deposition on the first metal layer, the in-situ deposition condition of silicon dioxide transition zone 4 is following:
Bottom radio-frequency power (LF Power) 3300W;
Middle part radio-frequency power (MF Power) 2000W;
High portion radio-frequency power (HF Power) 6000W;
Silane flow rate (Silane Flow) 300sccm;
Helium gas flow (Helium Flow) 200sccm;
Top oxygen throughput (O2-top Flow) 600sccm;
Sidepiece oxygen flow (O2-side Flow) 100sccm.
The thickness of control silicon dioxide transition zone 4 is 300.
Step 4, deposition second metal dielectric layer on transition zone
Adopt the PECVD method, under 400 ℃ of conditions, the deposition material is second metal dielectric layer 5 of silicon dioxide on transition zone 4.Because also need carry out planarization in the subsequent handling, therefore, the thickness of second metal dielectric layer 5 should be bigger, in the present embodiment, the thickness of controlling second metal dielectric layer 5 is 10000.
Step 5 is carried out cmp to second metal dielectric layer, until the thickness that reaches designing requirement
With reference to Fig. 2, the MOS device of present embodiment preparation is a cmos device, and the thickness of first metal dielectric layer 3 is 1000, and P content is 6%.
The silicon dioxide transition zone 4 that one deck in-situ deposition is arranged on first metal dielectric layer 3, the thickness of transition zone 4 are 300, are second metal dielectric layer 5 of silicon dioxide material on the transition zone 4.
Embodiment 4
Step 1 provides the substrate that contains NMOS and/or PMOS zone, and deposited barrier layer
Step 2, deposition first metal dielectric layer above the barrier layer
Under 480 ℃ of conditions, deposition one deck material is first metal dielectric layer 3 of HDP PSG above silicon nitride barrier, and to control first metal dielectric layer 3 be that thickness is 900.
Wherein, P content is 8% among the HDP PSG.
Step 3, in-situ deposition transition zone on first metal dielectric layer
After the first metal layer growth is accomplished, the not phosphorous silicon dioxide transition zone 4 of in-situ deposition on the first metal layer, the in-situ deposition condition of silicon dioxide transition zone 4 is following:
Bottom radio-frequency power (LF Power) 5000W;
Middle part radio-frequency power (MF Power) 1000W;
High portion radio-frequency power (HF Power) 6000W;
Silane flow rate (Silane Flow) 200sccm;
Helium gas flow (Helium Flow) 300sccm;
Top oxygen throughput (O2-top Flow) 500sccm;
Sidepiece oxygen flow (O2-side Flow) 300sccm.
The thickness of control silicon dioxide transition zone 4 is 500.
Step 4, deposition second metal dielectric layer on transition zone
Adopt the PECVD method, under 500 ℃ of conditions, the deposition material is second metal dielectric layer 5 of silicon dioxide on transition zone 4.Because also need carry out planarization in the subsequent handling, therefore, the thickness of second metal dielectric layer 5 should be bigger, in the present embodiment, the thickness of controlling second metal dielectric layer 5 is 10000.
Step 5 is carried out cmp to second metal dielectric layer, until the thickness that reaches designing requirement
With reference to Fig. 2, the MOS device of present embodiment preparation is a cmos device, and the thickness of first metal dielectric layer 3 is 900, and P content is 8%.
The silicon dioxide transition zone 4 that one deck in-situ deposition is arranged on first metal dielectric layer 3, the thickness of transition zone 4 are 500, are second metal dielectric layer 5 of silicon dioxide material on the transition zone 4.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (10)
1. a method that reduces double-deck preceding metal and dielectric matter layer cracking phenomena is characterized in that,
Step 1 provides the substrate with NMOS and/or PMOS zone, deposition etch barrier layer on said substrate;
Step 2, deposition first metal dielectric layer on said barrier layer;
Step 3, growth in situ one deck transition zone on first metal dielectric layer;
Step 4, deposition second metal dielectric layer on said transition zone;
Step 5, the thickness that second metal dielectric layer is carried out cmp to designing requirement;
Wherein, the caking property between the transition zone material and the second metal dielectric layer material is greater than the caking property between the transition zone and the first metal dielectric layer material.
2. the method that reduces double-deck preceding metal and dielectric matter layer cracking phenomena according to claim 1 is characterized in that the first metal and dielectric layer thickness, transition region thickness ratio are 800 ~ 2000:50 ~ 500.
3. the method that reduces double-deck preceding metal and dielectric matter layer cracking phenomena according to claim 1 is characterized in that the said first metal dielectric layer material is the phosphoric acid silex glass.
4. the method that reduces double-deck preceding metal and dielectric matter layer cracking phenomena according to claim 1 is characterized in that P content is 2 ~ 8% in said first metal dielectric layer.
5. according to any described method that reduces double-deck preceding metal and dielectric matter layer cracking phenomena in the claim 1 ~ 4, it is characterized in that the said transition zone and/or the second dielectric layer material are silicon dioxide.
6. the method that reduces double-deck preceding metal and dielectric matter layer cracking phenomena according to claim 5 is characterized in that said transition zone in-situ deposition condition comprises:
Bottom radio-frequency power 3000 ~ 5000W;
Middle part radio-frequency power 1000 ~ 2000W;
The high radio-frequency power 4000 ~ 6000W of portion;
Silane flow rate 200 ~ 300sccm;
Helium gas flow 200 ~ 300sccm;
Top oxygen throughput 300 ~ 600sccm;
Sidepiece oxygen flow 100 ~ 300sccm.
7. MOS device; It is characterized in that; Comprise substrate, comprise NMOS and/or PMOS zone in the said substrate, on said substrate, deposit etch stop layer, first metal dielectric layer successively; The transition zone that one deck growth in situ is arranged on said first metal dielectric layer deposits second metal dielectric layer above said transition zone;
Wherein, the caking property between the transition zone material and the second metal dielectric layer material is greater than the caking property between the transition zone and the first metal dielectric layer material.
8. MOS device according to claim 7 is characterized in that, said second metal dielectric layer and/or transition zone material are silicon dioxide.
9. MOS device according to claim 7 is characterized in that, said first metal dielectric layer is the phosphoric acid silex glass.
10. according to any described MOS device in the claim 7 ~ 9, it is characterized in that said first metal dielectric layer and transition region thickness ratio are 800 ~ 2000:50 ~ 500.
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| CN1377062A (en) * | 2001-03-27 | 2002-10-30 | 华邦电子股份有限公司 | Process for preparing dielectric layer between metal layers |
| US20060003572A1 (en) * | 2004-07-03 | 2006-01-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for improving a semiconductor device delamination resistance |
| CN101393868A (en) * | 2007-09-18 | 2009-03-25 | 上海华虹Nec电子有限公司 | Medium stuffing method between metal in process of semi-conductor wafer production |
| US20110089572A1 (en) * | 2008-03-19 | 2011-04-21 | Imec | Method for fabricating through substrate vias |
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- 2012-01-18 CN CN2012100148052A patent/CN102610556A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1377062A (en) * | 2001-03-27 | 2002-10-30 | 华邦电子股份有限公司 | Process for preparing dielectric layer between metal layers |
| US20060003572A1 (en) * | 2004-07-03 | 2006-01-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for improving a semiconductor device delamination resistance |
| CN101393868A (en) * | 2007-09-18 | 2009-03-25 | 上海华虹Nec电子有限公司 | Medium stuffing method between metal in process of semi-conductor wafer production |
| US20110089572A1 (en) * | 2008-03-19 | 2011-04-21 | Imec | Method for fabricating through substrate vias |
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Application publication date: 20120725 |