CN1377062A - Process for preparing dielectric layer between metal layers - Google Patents
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- CN1377062A CN1377062A CN 01110119 CN01110119A CN1377062A CN 1377062 A CN1377062 A CN 1377062A CN 01110119 CN01110119 CN 01110119 CN 01110119 A CN01110119 A CN 01110119A CN 1377062 A CN1377062 A CN 1377062A
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Abstract
The invention discloses a preparing method for improving control of evenness of the dielectric layers between metal layers that are formed by using the chemical gas phase deposition method in high-density plasma. First, a thin PE-TEOS with good eveness and adhesiveness is formed on the semicondcutor substrate where there are multiple interconnected wires are prepared. Then, the second layer of oxide is formed on the first layer of oxide by using the said chemical gas phase deposition method, with gaps between the interconnected wires filled by the second layer of oxide. Finally, third layer of oxide is formed on the second layer of oxide by using the enhanced chemical gas phase deposition method in plasma. The invented method obtains very good effect on filling the said gas and improves quality of the dielectric layers.
Description
The present invention relates to semiconductor fabrication, and the manufacture method that relates to a kind of dielectric layer between metal layers is particularly arranged.
At present, because the manufacture method of integrated circuit develops towards ULSI, therefore inner current densities more and more increases, along with the quantity of contained assembly in the chip constantly increases, the size of assembly is also constantly dwindled with the lifting of integration, and the surface of chip can't provide enough areas to make required internal connecting line gradually.In order to adapt to new demand, two-layer above plain conductor design, just become gradually many integrated circuits the mode that must adopt, particularly some functions are than complicated product, as microprocessor (microprocessor) etc., even the plain conductor of needs more than four layers or five layers, just can make each assembly bring into play due effect.Therefore, the manufacture method of multiple internal connecting line (multilevel interconnects) has become one of important technology indispensable in manufacture of semiconductor today.
In multiple internal connecting line manufacturing process, no doubt each assembly needs to come connected to each other with internal connecting line, but not directly contact between each internal connecting line and be short-circuited, must utilize insulating barrier to be isolated, generally be referred to as dielectric layer between metal layers (inter-metal dielectric, IMD), wherein silica, silicon nitride layer and tetraethoxysilane (TEOS) oxide etc. is the normal dielectric material that uses.But after the semiconductor manufacturing enters deep-submicron live width size field, requirement for the gap filling ability (gap fill) of high the ratio of width to height (aspect ratio) is also strict more, above-mentioned dielectric material is because clearance filling capability is not good, and can't provide required insulating property (properties), therefore many improved manufacturing technologies are arisen at the historic moment, wherein come deposition of dielectric materials with high density plasma CVD method (HDPCVD), can reach splendid gap filling effect, be often to be used to one of technology of making dielectric layer between metal layers (IMD) on the present production line therefore.
Yet, although the oxide layer that high density plasma CVD method (HDPCVD) forms has preferable gap filling property, but the uniformity of its deposition technique control at present is not good, uniformity control influence for subsequent chemistry mechanical lapping (CMP) is very big, and the membrane quality that it deposited is not good, cause film and bottom (underlayer) tack poor, in follow-up high-temperature plasma formed film process, having bubble between film and film produces, even cause peeling off of HDPCVD film, become the source of micronic dust (particle), drop on product, and then influence the qualification rate of product.Below promptly scheme, this manufacturing process is described with reference to 1A to 1B.
See also 1A figure, semiconductor substrate 10 is provided, its top can form any required semiconductor subassembly, but herein for simplicity of illustration, only with smooth substrate 10 expressions.On the semiconductor-based end 10, form a plurality of plain conductors 12, it for example is first depositing metal layers, define its pattern (pattern) through etching lithography process (lithography process) technology and etch process again, wherein metal level can more comprise a diffused barrier layer and an anti-reflecting layer up and down.Secondly, on the surface of the semiconductor-based end 10 and plain conductor 12, with high density plasma CVD (HDPCVD) manufacturing technology, deposition forms one silica layer 16, and inserts in the gap of plain conductor 12, forms structure as shown in FIG..
Then, see also 1B figure, with plasma enhanced chemical vapor deposition (PECVD) form a PE-TEOS as top layer 18 to cover on above-mentioned silicon oxide layer 16 surfaces, the common dielectric layer between metal layers that forms as shown in the figure is to provide the isolated effect of internal connecting line 12 with another metal level (not shown) of top.
Though the above-mentioned method that is used for making dielectric layer between metal layers has splendid clearance filling capability, the membrane quality that it deposited is not good, causes film and bottom (underlayer) tack poor, and then influences yield.Therefore, more reach perfection, be necessary to seek the road of improvement at the problems referred to above in order to make the dielectric layer between metal layers The Application of Technology.
In order to overcome the deficiencies in the prior art, main purpose of the present invention is to provide a kind of dielectric layer between metal layers (IMD) uniformity of improving high density plasma CVD method (HDPCVD) formed thereby to control the manufacture method of not good situation, the method according to this invention, not only can reach splendid gap filling effect, can improve situation simultaneously with the dielectric layer bad of known technology made.
For reaching above-mentioned purpose, the invention provides a kind of manufacture method of dielectric layer between metal layers, it is characterized in that with before high density plasma CVD (HDPCVD) film, elder generation's compliance (conformal) forms a uniformity and all good about 500 dusts of thin PE-TEOS of tack, with preceding sedimentary deposit as the HDPCVD film, again with high density plasma CVD (HDPCVD) deposit the film of palpus thickness.The good characteristic of the high evenness of the existing PE-TEOS technology of utilization and tack is improved the not good problem of oxide layer quality of high density plasma CVD (HDPCVD).
The manufacture method of dielectric layer between metal layers of the present invention at first is to be manufactured with at the semiconductor-based end of a plurality of internal connecting lines, and compliance (conformal) forms a uniformity and the good thin PE-TEOS of tack.Then, on first oxide layer, form second oxide layer, and insert the gap between those internal connecting lines with high-density plasma chemical vapor phase method (HDPCVD).At last, on second oxide layer, form the 3rd oxide layer with plasma enhanced chemical vapor deposition method (PECVD) again.
Dielectric layer between metal layers according to manufacture method formed thereby of the present invention, because of the film that is deposited by the PE-TEOS technology has high evenness and the good speciality of tack, so except possessing good clearance filling capability, and can improve the membrane quality of high density plasma CVD (HDPCVD).
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below:
1A to the 1B figure shows the profile of traditional making dielectric layer between metal layers method.
2A to the 2C figure represents the profile of the dielectric layer between metal layers method of embodiment of the invention made.
3A and 3B figure show the photo with the film of the light microscope check embodiment of the invention and conventional method formed thereby respectively.The figure number explanation
10, the 50 ~ semiconductor-based end; 12,52 ~ plain conductor; 16 ~ bottom oxide; 18 ~ top oxide; 54 ~ the first oxide layers; 56 ~ the second oxide layers; 58 ~ the 3rd oxide layers.
See also 2A to 2I and scheme, it is one embodiment of the present of invention, wherein, utilizes the high evenness and the good characteristic of tack of existing PE-TEOS technology, improves the not good situation of oxide layer quality of high density plasma CVD (HDPCVD).
At first according to 2A figure, present embodiment is applicable to the semiconductor substrate, can form any required semiconductor subassembly in substrate, as MOS transistor, resistance, logic module etc., but herein for for the purpose of simplifying accompanying drawing, only with smooth substrate 50 expressions.The manufacture method of dielectric layer between metal layers of the present invention is applicable to the semiconductor-based end 50 that is manufactured with a plurality of internal connecting lines 52, internal connecting line 52 in substrate 50, usually can first depositing metal layers, define its pattern through etching lithography process (lithography process) and etching technique again, its material generally can be tungsten, aluminium, Al-Si-Cu alloy, aluminium copper or copper.In addition, in order to increase adhesive ability and to avoid metal diffusing, can select to deposit one deck barrier layer (not shown), as titanium nitride layer (TiN), tantalum (Ta), tantalum nitride (TaN) etc.Moreover, also can on metal level, select deposition one anti-reflecting layer (not shown), for example titanium nitride layer (TiN).
According to the manufacture method of dielectric layer between metal layers of the present invention, at first, carry out committed step of the present invention, in substrate,, form first oxide layer 54 that a compliance covers (conformal) according to the profile of internal connecting line 52 with the semiconductor-based end.This first oxide layer be with plasma enhanced chemical vapor deposition method (PECVD) in the oxide layer that is lower than 400 ℃ of about 400 to 600 dusts of deposit one thickness, for example, be to be the PE-TEOS oxide layer that reactant deposited with TEOS.
Secondly, see also 2B figure,, on first oxide layer 54, form second oxide layer 56 of about 3000 to 4000 dusts of a thickness, and insert the gap of 52 of internal connecting lines with high density plasma CVD method (HDPCVD).For example, use oxygen (O
2) and silicomethane (SiH
4) be used as reactant, to form one silica layer 56.
Afterwards, see also 2C figure, the 3rd oxide layer 56 of about 6000 to 7000 dusts of comprehensive formation one thickness can utilize plasma enhanced chemical vapor deposition method (PECVD) to deposit to cover second oxide layer 54, for example is to be the PE-TEOS oxide layer or the SiH of main reaction thing with TEOS
4The PE-SiH that is deposited for the main reaction thing
4Oxide layer is to form silicon monoxide top layer 58, with beneath second oxide layer 56, first oxide layer, 54 common formation one dielectric layer between metal layers.Afterwards, with chemical mechanical milling method (CMP) with the top oxide planarization after, just can proceed follow-up metallization process.Measure the film equality that instrument compares the embodiment of the invention and traditional method for making formed thereby by OP-2000 thickness, its result is as shown in table 1: table 1 thickness of sample maximum ga(u)ge uniformity %
Difference PE-TEOS 500 dusts+HDPCVD 3,500 3,948 286 3.62 dust HDPCVD 4000 dusts 3,984 414 5.20
By the test result of table 1 film of embodiment of the invention formed thereby as can be known, its uniformity is 3.62%, is better than 5.20% (uniformity %=(maximum ga(u)ge-minimum thickness)/(thickness * 2)) of traditional method for making.
By the film of light microscope and the KLA fault detection instrument check embodiment of the invention and traditional method for making formed thereby, its result is presented at the 3rd figure and table 2.3A and 3B figure system show the photo with the film of the light microscope check embodiment of the invention and traditional method for making formed thereby respectively.Table 2
Sample for the second time for the first time
PE-TEOS 500 dusts+HDPCVD 88
3500 dusts
HDPCVD?4000 127 150
By the 3rd figure and the shown result of table 2 film of embodiment of the invention formed thereby as can be known, can significantly reduce the situation of peeling off of HDPCVD formed thereby film, make amounts of particles be reduced to several by over one hundred.
In sum, manufacture method of the present invention by the high evenness and the good characteristic of tack of PE-TEOS technology, can be improved the quality of high density plasma CVD (HDPCVD) film except possessing good clearance filling capability.
Though the present invention discloses as above with preferred embodiment; singly be not in order to limit the present invention; anyly know art technology person; without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is when looking claims and being as the criterion in conjunction with the scope person of defining of specification and accompanying drawing.
Claims (15)
1. the manufacture method of a dielectric layer between metal layers is applicable to that this manufacture method comprises the following steps: at the semiconductor-based end that is manufactured with many internal connecting lines
On the above-mentioned semiconductor-based end and internal connecting line, form first oxide layer that a compliance covers (conformal);
On this first oxide layer, form second oxide layer with high density plasma CVD method (HDPCVD); And
On this second oxide layer, form the 3rd oxide layer.
2. the method for claim 1 is characterized in that this first oxide layer is the formed oxide layer of plasma enhanced chemical vapor deposition method (PECVD).
3. the method for claim 1 is characterized in that about 400 to 600 dusts of this first thickness of oxide layer.
4. the method for claim 1 is characterized in that about 3000 to 4000 dusts of this second thickness of oxide layer.
5. the method for claim 1 is characterized in that the 3rd oxide layer is the formed oxide layer of plasma enhanced chemical vapor deposition method (PECVD).
6. the method for claim 1 is characterized in that about 6000 to 7000 dusts of the 3rd thickness of oxide layer.
7. the method for claim 1 is characterized in that also comprising: with the 3rd oxide layer planarization.
8. the method for claim 1 is characterized in that the material of those metal internal connecting lines is selected from: tungsten, aluminium, Al-Si-Cu alloy, aluminium copper, and copper.
9. the manufacture method of a dielectric layer between metal layers is applicable to that this manufacture method comprises the following steps: at the semiconductor-based end that is manufactured with many internal connecting lines
On the above-mentioned semiconductor-based end and internal connecting line, form first oxide layer that a compliance covers (conformal);
On this first oxide layer, form second oxide layer with high density plasma CVD method (HDPCVD); And
On this second oxide layer, form the 3rd oxide layer; And
With chemical mechanical milling method with the 3rd oxide layer planarization.
10. method as claimed in claim 9 is characterized in that this first oxide layer is the formed oxide layer of plasma enhanced chemical vapor deposition method (PECVD).
11. method as claimed in claim 9 is characterized in that about 400 to 600 dusts of this first oxidated layer thickness.
12. method as claimed in claim 9 is characterized in that about 3000 to 4000 dusts of this second thickness of oxide layer.
13. method as claimed in claim 9 is characterized in that the 3rd oxide layer is the formed oxide layer of plasma enhanced chemical vapor deposition method (PECVD).
14. method as claimed in claim 9 is characterized in that about 6000 to 7000 dusts of the 3rd thickness of oxide layer.
15. method as claimed in claim 9 is characterized in that the material of those metal internal connecting lines is selected from tungsten, aluminium, Al-Si-Cu alloy, aluminium copper, reaches copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01110119 CN1216407C (en) | 2001-03-27 | 2001-03-27 | Process for preparing dielectric layer between metal layers |
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| CN 01110119 CN1216407C (en) | 2001-03-27 | 2001-03-27 | Process for preparing dielectric layer between metal layers |
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| CN1377062A true CN1377062A (en) | 2002-10-30 |
| CN1216407C CN1216407C (en) | 2005-08-24 |
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| CN 01110119 Expired - Lifetime CN1216407C (en) | 2001-03-27 | 2001-03-27 | Process for preparing dielectric layer between metal layers |
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Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1310294C (en) * | 2003-11-03 | 2007-04-11 | 旺宏电子股份有限公司 | Method for filling gap and producing method for shallow kennel separated structure |
| CN100339956C (en) * | 2004-03-09 | 2007-09-26 | 联华电子股份有限公司 | Trench method for metal wires |
| CN100380624C (en) * | 2005-02-24 | 2008-04-09 | 台湾积体电路制造股份有限公司 | Hdp-cvd methodology for forming pmd layer |
| CN1716546B (en) * | 2004-06-30 | 2012-01-04 | 台湾积体电路制造股份有限公司 | Dielectric layer and integrated circuit |
| CN102446745A (en) * | 2011-10-13 | 2012-05-09 | 上海华力微电子有限公司 | Method for reducing cracking of dual-layer front metal dielectric substance layer |
| CN102487057A (en) * | 2010-12-03 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Metal front dielectric layer and preparation method thereof |
| CN102610556A (en) * | 2012-01-18 | 2012-07-25 | 上海华力微电子有限公司 | Method for reducing cracking phenomenon of double-layer front metal dielectric layer |
| CN104576497A (en) * | 2013-10-18 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for integrated passive device |
| CN105355551A (en) * | 2015-11-12 | 2016-02-24 | 扬州杰利半导体有限公司 | Wafer passivation technology |
| CN107199337A (en) * | 2016-03-16 | 2017-09-26 | 华邦电子股份有限公司 | The forming method of metallic conducting wire structure |
| CN105575886B (en) * | 2014-10-14 | 2019-01-08 | 中芯国际集成电路制造(上海)有限公司 | Production method, the production method of connected medium layer and interconnection layer of connected medium layer |
| CN110034122A (en) * | 2017-11-29 | 2019-07-19 | 台湾积体电路制造股份有限公司 | Bonding pad structure and its manufacturing method in semiconductor devices |
| CN110246855A (en) * | 2012-12-27 | 2019-09-17 | 台湾积体电路制造股份有限公司 | Surface treatment for BSI imaging sensor |
| CN112582533A (en) * | 2020-11-20 | 2021-03-30 | 上海矽睿科技有限公司 | Preparation method of 3D shape of chip |
-
2001
- 2001-03-27 CN CN 01110119 patent/CN1216407C/en not_active Expired - Lifetime
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1310294C (en) * | 2003-11-03 | 2007-04-11 | 旺宏电子股份有限公司 | Method for filling gap and producing method for shallow kennel separated structure |
| CN100339956C (en) * | 2004-03-09 | 2007-09-26 | 联华电子股份有限公司 | Trench method for metal wires |
| CN1716546B (en) * | 2004-06-30 | 2012-01-04 | 台湾积体电路制造股份有限公司 | Dielectric layer and integrated circuit |
| CN100380624C (en) * | 2005-02-24 | 2008-04-09 | 台湾积体电路制造股份有限公司 | Hdp-cvd methodology for forming pmd layer |
| CN102487057A (en) * | 2010-12-03 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Metal front dielectric layer and preparation method thereof |
| CN102487057B (en) * | 2010-12-03 | 2014-03-12 | 中芯国际集成电路制造(北京)有限公司 | Metal front dielectric layer and preparation method thereof |
| CN102446745A (en) * | 2011-10-13 | 2012-05-09 | 上海华力微电子有限公司 | Method for reducing cracking of dual-layer front metal dielectric substance layer |
| CN102610556A (en) * | 2012-01-18 | 2012-07-25 | 上海华力微电子有限公司 | Method for reducing cracking phenomenon of double-layer front metal dielectric layer |
| CN110246855A (en) * | 2012-12-27 | 2019-09-17 | 台湾积体电路制造股份有限公司 | Surface treatment for BSI imaging sensor |
| CN104576497A (en) * | 2013-10-18 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for integrated passive device |
| CN104576497B (en) * | 2013-10-18 | 2017-09-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of preparation method of integrated passive devices |
| CN105575886B (en) * | 2014-10-14 | 2019-01-08 | 中芯国际集成电路制造(上海)有限公司 | Production method, the production method of connected medium layer and interconnection layer of connected medium layer |
| CN105355551B (en) * | 2015-11-12 | 2018-05-15 | 扬州杰利半导体有限公司 | A kind of wafer passivation technique |
| CN105355551A (en) * | 2015-11-12 | 2016-02-24 | 扬州杰利半导体有限公司 | Wafer passivation technology |
| CN107199337A (en) * | 2016-03-16 | 2017-09-26 | 华邦电子股份有限公司 | The forming method of metallic conducting wire structure |
| CN110034122A (en) * | 2017-11-29 | 2019-07-19 | 台湾积体电路制造股份有限公司 | Bonding pad structure and its manufacturing method in semiconductor devices |
| CN110034122B (en) * | 2017-11-29 | 2021-07-27 | 台湾积体电路制造股份有限公司 | Pad structure in semiconductor device and method of manufacturing the same |
| CN112582533A (en) * | 2020-11-20 | 2021-03-30 | 上海矽睿科技有限公司 | Preparation method of 3D shape of chip |
| CN112582533B (en) * | 2020-11-20 | 2023-08-08 | 上海矽睿科技股份有限公司 | Chip 3D morphology preparation method |
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| CN1216407C (en) | 2005-08-24 |
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