CN102593039A - Manufacturing method for mechanically actuated uniaxial strain GeOI wafer based on AlN embedded insulating layer - Google Patents
Manufacturing method for mechanically actuated uniaxial strain GeOI wafer based on AlN embedded insulating layer Download PDFInfo
- Publication number
- CN102593039A CN102593039A CN2011103615235A CN201110361523A CN102593039A CN 102593039 A CN102593039 A CN 102593039A CN 2011103615235 A CN2011103615235 A CN 2011103615235A CN 201110361523 A CN201110361523 A CN 201110361523A CN 102593039 A CN102593039 A CN 102593039A
- Authority
- CN
- China
- Prior art keywords
- wafer
- geoi
- geoi wafer
- annealing
- geio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Recrystallisation Techniques (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
The invention discloses a manufacturing method for a mechanically actuated uniaxial strain GeOI wafer based on an AlN embedded insulating layer. The manufacturing method includes the following steps: firstly, placing a Ge layer surface on the top layer of the GeOI wafer on an arced bent table upwards or downwards; secondly, respectively and horizontally placing two cylindrical stainless steel pressure levers at the positions of two ends of the GeIO wafer, which are away from the edge of the GeIO wafer by 1cm; thirdly, slowly screwing a screw cap which is connected with the pressure lever to enable the GeIO wafer to be gradually bent along an arced tabletop until the GeIO wafer is completely attached to the arced tabletop; fourthly, placing the arced tabletop carrying the GeIO wafer in an annealing furnace for annealing; fifthly, after annealing, slowing cooling to room temperature and taking out the arced bent table carrying the GeIO wafer; and sixthly, screwing the screw cap connected with the connecting rod and slowly lifting the pressure lever until the bent GeIO wafer restores to the original shape. The manufacturing method disclosed by the invention has the advantages of high strain degree, excellent thermal performance, high finished product rate, wide annealing temperature range, simple manufacturing process as well as less manufacturing equipment and tailor availability.
Description
Technical field
The invention belongs to microelectronics technology, relate to the semi-conducting material manufacturing technology.Uniaxial strain GeOI (Germanium On Insulater on a kind of specifically manufacturing AlN (aluminium nitride) enterree; Germanium on the insulating barrier) new method of wafer; Can significantly strengthen the electron mobility and the hole mobility of GeOI wafer, improve the electric property of GeOI MOS device and GeOI cmos circuit.
Background technology
The electronics of semiconductor Ge and hole mobility are respectively 2.8 times and 4.2 times of Si, and its hole mobility is the highest in all semiconductors.Si is similar with strain, and the carrier mobility of strain Ge also has bigger lifting, and the hole mobility of buried channel strain Ge can improve 6-8 doubly.Therefore, Ge and strain Ge will be the best channel material of 16 nanometers and following technology Si based CMOS devices and integrated circuit.Ge still is a utmost point excellent photoelectric material, has very widely at detector (visible light is to near-infrared), modulator, fiber waveguide, optical transmitting set, solar cell etc. and uses.
Because energy gap has only 0.67eV, the greatest weakness of Ge device and circuit is that the electric leakage of substrate is bigger.And GeOI develops for the solution substrate leakage currents just, be widely used in the manufacturing of semiconductor device and integrated circuit at present.
In conjunction with the strain GeOI of strain Ge and GeOI advantage for novel ultrahigh speed, low-power consumption, radioresistance, high integration silicon-based devices and the chip of research and development a kind of new solution is provided, there is important application prospects aspects such as, system level chip integrated at photoelectricity.
The enterree of GeOI wafer is SiO normally
2(silicon dioxide), its thermal conductivity is merely one of percentage of silicon, hindered GeOI in high temperature, application aspect high-power; Its dielectric constant is merely 3.9, is prone to cause the signal transmission to lose, and has also hindered the application of GeOI in high density, high power integrated circuit.And AlN has the thermal conductivity height (is SiO
2200 times), high, the chemistry of resistivity big (320W/mK), disruptive field intensity and excellent properties such as thermal stability is good, thermal coefficient of expansion is close with Si, be a kind of dielectric and insulating material of excellence more.Replace SiO with AlN
2GeOI have better insulating properties and thermal diffusivity, be widely used in high temperature, big power consumption, the high power integrated circuit.
Traditional strain GeOI is based on the twin shaft compressive strain of SOI wafer; Promptly at SOI (Silicon On Insulater; Silicon on the insulating barrier) direct growth strain Ge on the wafer; Or earlier on the SOI wafer SiGe layer of growth Ge content gradually variational make empty substrate, the required strain Ge layer of epitaxial growth on this SiGe layer again.The major defect of tradition strain GeOI is that dislocation density is high, can only to be that twin shaft compressive strain, mobility promote not high, the empty substrate of SiGe has increased hot expense and cost of manufacture, the empty substrate of SiGe have had a strong impact on device and circuit heat radiation, strain Ge layer critical thickness receive that the Ge component limits, the hole mobility lifting under the High-Field can be degenerated etc.
C.Himcinschi has proposed the manufacturing technology of uniaxial strain SOI wafer in 2007, referring to [1] C.Himcinschi., I.Radu; F.Muster, R.AlNgh, M.Reiche; M.Petzold, U.Go ¨ sele, S.H.Christiansen; Uniaxially strained silicon by wafer bonding and layer transfer, Solid-State electronics, 51 (2007) 226-230; [2] C.Himcinschi; M.Reiche; R.Scholz; S.H.Christiansen; And U.
Compressive uniaxially strained silicon on insulator by prestrained wafer bonding and layer transferAPPLIeD, PHYSICS LeTTeRS 90,231909 (2007).Technological principle and step that this is technological are as depicted in figs. 1 and 2, and the manufacturing process steps of its single shaft tensile strain GeOI is described below:
1. earlier with 4 inches Si sheet 1 thermal oxidations, again this oxidation sheet 1 is injected H
+(hydrogen ion).
2. will annotate H
+Oxidation sheet 1 be placed on the arc-shaped bend platform,, fit tightly its bending through outer depression bar with the arc table top; Subsequently 3 inches Si sheets 2 are placed on 4 inches crooked notes H along the same flex direction
+On the oxidation sheet 1, with its bending, and annotate H through interior depression bar
+Oxidation sheet 1 fits tightly;
3. crooked platform is placed in the annealing furnace, annealed 15 hours down at 200 ℃.
4. take off crooked and two Si wafers of bonding from crooked platform, be reentered in the annealing furnace,, accomplish smart peeling, and finally form uniaxial strain GeOI wafer 500 ℃ of annealing 1 hour down.
This technological major defect is: 1) processing step is complicated: this method must experience thermal oxidation, H
+Ion injects, peels off requisite main technique and correlation step thereof such as annealing.2) flexure temperature is limited: owing to be to close and crooked annealing at the smart peeling line unit that advances, annotated H
+The restriction of exfoliation temperature, its crooked annealing temperature can not be higher than 300 ℃, otherwise will in crooked annealing process, peel off, and makes the Si sheet broken.3) fabrication cycle is long: extra thermal oxidation, H
+Ion injects, peels off the time that processing step such as annealing has increased its making.4) rate of finished products is low: this method is to carry out mechanical bend and bonding with two overlapping silicon wafer, and under case of bending, carries out high temperature again and peel off, and silicon wafer is easy to fragmentation.
Summary of the invention
The objective of the invention is to overcome the deficiency of above-mentioned prior art; The manufacture method that a kind of machinery based on the AlN enterree causes uniaxial strain GeOI wafer is proposed; With the cost of manufacture that reduces strain GeOI wafer, heat dispersion, insulation property and the integrated level that improves strain GeOI device and integrated circuit, satisfy microelectronics technology, particularly ultrahigh speed, low-power consumption, anti-irradiation and high power device and integrated circuit demand to strain GeOI wafer.Adopt following technical scheme:
A kind of machinery based on the AlN enterree causes the manufacture method of uniaxial strain GeOI wafer, may further comprise the steps: 1) GeOI wafer top layer Ge aspect is placed on the arc-shaped bend platform up or down; 2) two cylindrical stainless steel depression bars lie in a horizontal plane in GeOI wafer two ends respectively, apart from GeOI crystal round fringes 1cm; 3) slow turn connects the nut of depression bar, makes the GeOI wafer crooked gradually along the arc table top, the complete and arc table top applying until the GeOI wafer; 4) the arc-shaped bend platform that is loaded with the GeOI wafer is placed in the annealing furnace anneals, and annealing temperature can be selected arbitrarily in 300 ℃ to 900 ℃ scopes.For example, can anneal 10 hours down, also can anneal 5 hours down at 600 ℃ at 300 ℃; 5) annealing slowly is cooled to room temperature after finishing, and takes out the arc-shaped bend platform that is loaded with the GeOI wafer; 6) turn connects the nut of depression bar, depression bar is slowly promoted, until the reinstatement of the GeOI of bending wafer.Being loaded with temperature that the crooked platform of GeOI wafer anneals minimum in annealing furnace is 300 ℃, can surpass its yield strength to guarantee the deformation of AlN enterree in this process in the GeOI wafer, the generation plastic deformation; The highest annealing temperature is 900 ℃, near the fusing point of Ge.But the highest annealing temperature must not be higher than the deformation temperature of mechanical bend platform
Described manufacture method, the radius of curvature of described arc-shaped bend platform can change from 1.2m to 0.35m continuously, the uniaxial strain GeOI wafer of the differently strained amount of its respective production.
Described manufacture method, the annealing process of said step 4) is: annealed 10 hours down at 300 ℃; Perhaps annealed 6 hours down at 600 ℃; Perhaps annealed 3 hours down at 900 ℃.
Described manufacture method, said GeOI wafer are 3 inches, 4 inches, 5 inches, 6 inches, 8 inches GeOI wafer.
Know-why of the present invention:
The GeOI sheet top layer Ge aspect of finished product upwards is placed on carries out mechanical bend, thermal annealing then on the circular arc table top.According to material plastoelasticity principle; Receive the effect of long-time crooked thermomechanical treatment; The AlN layer and the top layer Ge layer that are in GeOI wafer neutral surface top will be along bending direction generation uniaxial tensile deformations, and its lattice constant will become greatly, and so-called single shaft tensile strain promptly takes place.Simultaneously, in GeOI wafer internal reservoir certain elastic potential energy.After annealing finished to remove mechanical external force, under this elastic potential energy effect, resilience can take place in the GeOI wafer, promptly is returned to ortho states by case of bending, and was as shown in Figure 3.
But top layer Ge layer has kept a certain amount of tensile strain in the GeOI wafer that restores.This is because when crooked thermal anneal process, has set suitable annealing temperature and time, guarantees that the mechanical external force that is applied can surpass the yield strength of AlN but less than the yield strength of Si substrate, make AlN generation plastic deformation, and the Si substrate is elastic deformation all the time.The AlN enterree of plastic deformation is resilience fully when the resilience of GeOI wafer is restored, and still keeps a certain amount of tensile strain.And top layer Ge layer receives the effect that pulls and supports of plastic deformation AlN enterree, and resilience fully finally forms single shaft tensile strain GeOI wafer.
In like manner; Circular arc table top on carry out mechanical bend and thermal annealing as if GeOI wafer top layer Ge aspect is placed on downwards, because top layer Si Ge layer is in the bottom of GeOI wafer neutral surface, its lattice will be compressed when bending is annealed; Lattice constant diminishes, and finally can obtain single shaft compressive strain GeOI wafer.
With respect to existing uniaxial strain GeOI technology, the present invention has the following advantages:
1) answer variation high: with existing similar compared with techniques, under the same flexibility, dependent variable of the present invention is high, thereby can obtain higher mobility.
2) hot property is good: with the answering based on the empty substrate of SiGe of traditional C VD (chemical vapor deposition) epitaxy making
Become the SOI wafer and compare, the strain GeOI wafer that the present invention makes does not have thick SiGe resilient coating, can reduce the hot expense of its device and circuit greatly, and its AlN enterree makes its device and circuit have good heat dispersion again.
3) rate of finished products is high: prior art adopts two Si wafers to carry out the crooked annealing of bonding, and under case of bending, peels off through high temperature and obtain uniaxial strain SOI, thereby the Si sheet is very easy to broken.And the present invention only carries out bending annealing with the GeOI wafer of a slice finished product and obtains uniaxial strain GeOI, is difficult for brokenly, thereby rate of finished products is high.
4) annealing region is big: 200 ℃ to 300 ℃ annealing regions of existing relatively uniaxial strain SOI technology, annealing temperature of the present invention from minimum 300 ℃ to the highest 900 ℃, can select arbitrarily.
5) manufacture craft is simple: with existing similar compared with techniques, do not have extra technologies such as thermal oxidation, ion inject, high temperature is peeled off, mechanical bend and high annealing twice processing step are only arranged.
6) equipment is few and can make by oneself: only need crooked platform and two equipment of annealing furnace can realize the present invention, and crooked platform can be made by oneself.
Description of drawings
Fig. 1 is existing single shaft tensile strain GeOI principle and processing step;
Fig. 2 is existing single shaft compressive strain GeOI principle and processing step;
Fig. 3 is single shaft tensile strain GeOI wafer manufacturing principle of the present invention and processing step;
Fig. 4 is single shaft compressive strain GeOI wafer manufacturing principle of the present invention and processing step;
The 1-Si substrate, 2-AlN enterree, 3-top layer Ge layer.
Embodiment
Below in conjunction with specific embodiment, the present invention is elaborated.
The preparation of embodiment 1:3 inch uniaxial strain GeOI wafer
1, the GeOI wafer is selected: 3 inches (100) or (110) wafer ((100) or (110) refer to certain crystal face of GeOI wafer plane of crystal), the thick 0.4mm of Si substrate, the thick 500nm of AlN enterree, top layer Ge bed thickness 500nm.
The GeOI diameter wafer is selected: the diameter of GeOI wafer is big more; Its crooked minimum bending radius is just more little; The dependent variable of the uniaxial strain GeOI wafer that obtains is also just big more, and the electron mobility of final uniaxial strain GeOI wafer and the enhancing of hole mobility are also just high more.For made of the present invention based on for the uniaxial strain GeOI wafer of AlN enterree, according to the different process of its GeOI device and circuit, can select different-diameter GeOI wafer from 3 inches to 8 inches.
GeOI wafer crystal face and crystal orientation are selected: for the tensile strain GeOI wafer of made of the present invention; Should select (100) crystal face; Bending direction should be selected < 110>crystal orientation, and (< 110>refer to certain crystal orientation of wafer surface; Usually also be the channel direction of device), can obtain maximum electron mobility and promote.For the compressive strain GeOI wafer of made of the present invention, should select (110) crystal face, bending direction should be selected < 100>crystal orientation, can obtain maximum hole mobility and promote.
GeOI wafer Si substrate thickness is selected: the thickness of Si substrate is thin more, and the minimum bending radius of its GeOI wafer is just little, and the dependent variable of the single shaft tensile strain GeOI wafer that obtains is also just big more.For made of the present invention based on for the uniaxial strain GeOI wafer of AlN enterree, according to the different structure and the technology thereof of its GeOI device and circuit, can select the GeOI wafer of different Si substrate thickness.
GeOI wafer top layer Ge layer thickness is selected: according to the different structure of its GeOI device and circuit, can select the GeOI wafer of different top layer Ge layer thickness.If made of the present invention based on SiO
2The compressive strain GeOI wafer of enterree is applied to cmos device and circuit, then requires top layer Ge thickness can not surpass 30nm; If be applied to photo-detector, then require top layer Ge thickness can not be lower than 700nm;
GeOI wafer AlN enterree thickness is selected: according to the different structure of GeOI device and circuit, can select the GeOI wafer of different al N thickness of insulating layer.If the tensile strain GeOI wafer based on the AlN enterree of made of the present invention is applied to cmos device and circuit, then require the AlN thickness of insulating layer to be not less than 250nm; If be applied to photo-detector, then require the AlN thickness of insulating layer to be no more than 200nm;
Crooked platform material is selected: crooked platform material mainly is to select according to annealing temperature, guarantee that crooked platform is indeformable under the highest annealing temperature.For the present invention adopted based on for the GeOI wafer of AlN enterree, its highest annealing temperature is 900 ℃, and then crooked platform material can adopt resistant to elevated temperatures ZG35Cr26Ni12 heat-resisting steel material.
2, crooked platform radius of curvature is selected: according to the GeOI wafer of selecting, selecting crooked platform radius of curvature is 1m.The radius of curvature of crooked platform is to select according to the diameter and the thickness of GeOI wafer.Under the identical GeOI wafer size, the minimum bending radius of thin GeOI wafer is littler than thick GeOI wafer.Under the same thickness, the minimum bending radius of large scale GeOI wafer is littler than small size GeOI wafer.For made of the present invention based on for the tensile strain GeOI wafer of AlN enterree; The bending radius scope of its 4 inches GeOI wafers is 0.50m-1.2m; The bending radius scope of its 6 inches GeOI wafers is 0.45m-1.2m,, its 8 inches GeOI wafer bending radius scopes are 0.4m-1.2m.
3, GeOI wafer bending process step:
1) with GeOI wafer top layer Ge aspect upwards (or, upwards be tensile strain downwards,, be compressive strain downwards like Fig. 3, like Fig. 4, down with) be placed on the arc-shaped bend platform, its bending direction is parallel with < 110>or < 100>direction;
2) two cylindrical horizontal depression bars on the crooked platform lie in a horizontal plane in GeOI wafer two ends respectively, apart from 1 centimetre at its edge;
3) the push rod nut of one of them depression bar on the crooked platform of turn makes GeOI wafer one end fixing earlier;
4) the slow push rod nut of another depression bar of turn again makes the GeOI wafer crooked gradually along arc-shaped bend platform table top, until the GeOI wafer fully and arc-shaped bend platform table top fit fully.
4, annealing process step:
1) annealing temperature: 300 ℃;
2) heating rate: 5 ℃/minute;
3) annealing time: 10 hours;
4) rate of temperature fall: 5 ℃/minute;
5, unload frame: treat that furnace temperature reduces to room temperature, take out crooked platform.The push rod nut of two depression bars in the crooked platform two ends of simultaneously slow turn slowly promotes horizontal struts simultaneously, breaks away from the GeOI wafer fully until depression bar.
Through above-mentioned processing step, can obtain 3 inches uniaxial strain GeOI wafers based on the AlN enterree.
The preparation of embodiment 2:4 inch uniaxial strain GeOI wafer
1, the GeOI wafer is selected: 4 inches (100) or (110) crystal face, the thick 0.55mm of Si substrate, the thick 300nm of AlN enterree, top layer Ge bed thickness 50nm.
2, the bending curvature radius is selected: according to the GeOI wafer of selecting, selecting crooked platform radius of curvature is 0.75m.
3, GeOI wafer bending process step:
1) with GeOI wafer top layer Ge aspect upwards (or downwards) be placed on the stainless steel arc-shaped bend platform of cleaning, its < 110>or < 100>direction are parallel with bending direction, like Fig. 3 or shown in Figure 4;
2) two cylindrical horizontal depression bars on the crooked platform lie in a horizontal plane in GeOI wafer two ends respectively, apart from 1 centimetre at its edge;
3) the push rod nut of one of them depression bar on the crooked platform of turn makes GeOI wafer one end fixing earlier;
4) the slow push rod nut of another depression bar of turn again makes the GeOI wafer crooked gradually along arc-shaped bend platform table top, until the GeOI wafer fully and arc-shaped bend platform table top fit fully.
4, annealing process step:
1) annealing temperature: 600 ℃;
2) heating rate: 4 ℃/minute;
3) annealing time: 5 hours;
4) rate of temperature fall: 4 ℃/minute;
5, unload frame: treat that furnace temperature reduces to room temperature, take out crooked platform.The push rod nut of two depression bars in the crooked platform two ends of simultaneously slow turn slowly promotes horizontal struts simultaneously, breaks away from the GeOI wafer fully until depression bar.
Through above-mentioned processing step, can obtain 4 inches uniaxial strain GeOI wafers based on the AlN enterree.
The preparation of embodiment 3:6 inch uniaxial strain GeOI wafer
1, the GeOI wafer is selected: 6 inches (100) or (110) crystal face, the thick 0.68mm of Si substrate, the thick 1000nm of AlN enterree, top layer Ge bed thickness 1000nm.
2, the bending curvature radius is selected: according to the GeOI wafer of selecting, selecting crooked platform radius of curvature is 0.5m.
3, GeOI wafer bending process step:
1) with GeOI wafer top layer Ge aspect upwards (or downwards) be placed on the arc-shaped bend platform, its bending direction is parallel with < 110>or < 100>direction, like Fig. 3 or shown in Figure 4;
2) two cylindrical horizontal depression bars on the crooked platform lie in a horizontal plane in GeOI wafer two ends respectively, apart from 1 centimetre at its edge;
3) the push rod nut of one of them depression bar on the crooked platform of turn makes GeOI wafer one end fixing earlier;
4) the slow push rod nut of another depression bar of turn again makes the GeOI wafer crooked gradually along arc-shaped bend platform table top, until the GeOI wafer fully and arc-shaped bend platform table top fit fully.
4, annealing process step:
1) annealing temperature: 900 ℃;
2) heating rate: 3 ℃/minute;
3) annealing time: 3 hours;
4) rate of temperature fall: 3 ℃/minute;
5, unload frame: treat that furnace temperature reduces to room temperature, take out crooked platform.The push rod nut of two depression bars in the crooked platform two ends of simultaneously slow turn slowly promotes horizontal struts simultaneously, breaks away from the GeOI wafer fully until depression bar.
Through above-mentioned processing step, can obtain 6 inches uniaxial strain GeOI wafers based on the AlN enterree.
In order to make narration of the present invention more clear, below will make specifying to many details.For example concrete structure, composition, material, size, technical process and technology.
The used arc-shaped bend platform of the present invention adopts the ZG35Cr26Ni12 heat-resisting steel material, and this is indeformable under the highest annealing temperature in order to guarantee crooked platform.In addition, the used crooked platform of the present invention can adopt also that other are easy to machining, fineness is higher and resistant to elevated temperatures all materials are made.
Strain GeOI wafer base semiconductor substrate 1 of the present invention can be other semi-conducting materials also, like all possible semi-conducting materials such as Ge, GaAs.
Strain GeOI wafer top layer semi-conducting material 3 of the present invention is not limited to the Ge semi-conducting material, also Si, SiGe, GaAs etc. all be fit to make semi-conducting materials of GeOI wafer top layer semiconductive thin films.
The GeOI wafer that any process is made all is suitable for the present invention and makes uniaxial strain GeOI wafer, these processes comprise smart peeling (Smart-cut), annotate oxygen isolate (SIMOX), bonding and back of the body corrosion (BeGeOI), layer transfer (eLRANT), based on the epitaxial growth of GeOI wafer etc.
The selection principle of crooked annealing temperature of the present invention and annealing time is guarantee that plastic deformation takes place the AlN film in the GeOI crystal circle structure in annealing process, but the Si substrate in the GeOI wafer in annealing elastic deformation can only take place.Therefore, according to the Material Thermodynamics characteristic of AlN film, its minimum annealing temperature must not be lower than 300 ℃.According to the characteristic of GeOI wafer top layer Ge layer, the highest annealing temperature can reach 900 ℃, near the fusing point of Ge.But the highest annealing temperature must be considered the thermodynamic property of crooked platform material, can not be higher than its deformation temperature.
Detailed description of the present invention and describing all based on the optimization test scheme, but person of skill in the art will appreciate that above-mentioned variation with other forms and details can't depart from essence of the present invention and scope.To those skilled in the art; After having understood content of the present invention and principle; Can be under the situation that does not deviate from the principle and scope of the present invention; Carry out various corrections and change on form and the details according to the method for the invention, but these are based on correction of the present invention with change still within claim protection range of the present invention.
Should be understood that, concerning those of ordinary skills, can improve or conversion, and all these improvement and conversion all should belong to the protection range of accompanying claims of the present invention according to above-mentioned explanation.
Claims (4)
1. the machinery based on the AlN enterree causes the manufacture method of uniaxial strain GeOI wafer, it is characterized in that may further comprise the steps: 1) GeOI wafer top layer Ge aspect is placed on the arc-shaped bend platform up or down; 2) two cylindrical stainless steel depression bars lie in a horizontal plane in GeOI wafer two ends respectively, apart from GeOI crystal round fringes 1cm; 3) slow turn connects the nut of depression bar, makes the GeOI wafer crooked gradually along the arc table top, the complete and arc table top applying until the GeOI wafer; 4) the arc-shaped bend platform that is loaded with the GeOI wafer is placed in the annealing furnace anneals, and annealing temperature can be selected arbitrarily in 300 ℃ to 900 ℃ scopes; 5) annealing slowly is cooled to room temperature after finishing, and takes out the arc-shaped bend platform that is loaded with the GeOI wafer; 6) turn connects the nut of depression bar, depression bar is slowly promoted, until the reinstatement of the GeOI of bending wafer.
2. manufacture method according to claim 1 is characterized in that, the radius of curvature of described crooked platform can change from 1.2m to 0.35m continuously, the uniaxial strain GeOI wafer of the differently strained amount of its respective production; Crooked platform material adopts ZG35Cr26Ni heat resisting steel 12 materials.
3. manufacture method according to claim 1 is characterized in that, the annealing process of said step 4) is: annealed 10 hours down at 300 ℃; Perhaps annealed 5 hours down at 600 ℃; Perhaps annealed 3 hours down at 900 ℃.
4. manufacture method according to claim 1 is characterized in that, said GeOI wafer is 3 inches, 4 inches, 5 inches, 6 inches, 8 inches a GeOI wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110361523.5A CN102593039B (en) | 2011-11-16 | 2011-11-16 | Manufacturing method for mechanically actuated uniaxial strain GeOI wafer based on AlN embedded insulating layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110361523.5A CN102593039B (en) | 2011-11-16 | 2011-11-16 | Manufacturing method for mechanically actuated uniaxial strain GeOI wafer based on AlN embedded insulating layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102593039A true CN102593039A (en) | 2012-07-18 |
| CN102593039B CN102593039B (en) | 2014-12-10 |
Family
ID=46481501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110361523.5A Expired - Fee Related CN102593039B (en) | 2011-11-16 | 2011-11-16 | Manufacturing method for mechanically actuated uniaxial strain GeOI wafer based on AlN embedded insulating layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102593039B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103065938A (en) * | 2012-12-31 | 2013-04-24 | 中国科学院上海微系统与信息技术研究所 | Method for preparing direct band-gap germanium thin film |
| CN103094099A (en) * | 2013-01-14 | 2013-05-08 | 陆伟 | Method of wafer annealing after bonding |
| CN105845617A (en) * | 2016-06-20 | 2016-08-10 | 西安电子科技大学 | Manufacturing method for AlN buried insulating layer wafer level uniaxial strain Ge based on non-crystallization and scale effect |
| CN105938811A (en) * | 2016-06-20 | 2016-09-14 | 西安电子科技大学 | Manufacturing method for wafer level uniaxial strain SOI based on noncrystallization and scale effect |
| CN105938809A (en) * | 2016-06-20 | 2016-09-14 | 西安电子科技大学 | Manufacturing method for wafer level uniaxial strain Si on SiN-buried insulating layer based on noncrystallization and scale effect |
| CN105977198A (en) * | 2016-06-20 | 2016-09-28 | 西安电子科技大学 | Amorphization and scale effect-based manufacturing method of wafer-level uniaxial strain Ge on SiN buried insulating layer |
| CN105977199A (en) * | 2016-06-20 | 2016-09-28 | 西安电子科技大学 | Amorphization and scale effect-based manufacturing method of wafer-level uniaxial strain GeOI |
| CN105977197A (en) * | 2016-06-20 | 2016-09-28 | 西安电子科技大学 | Amorphization and scale effect-based manufacturing method of wafer-level uniaxial strain SiGe on SiN buried insulating layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070081169A1 (en) * | 2005-10-12 | 2007-04-12 | Sematch Inc. | Methods for characterizing semiconductor material using optical metrology |
| CN101292342A (en) * | 2005-10-19 | 2008-10-22 | Soi科技公司 | Treating a germanium layer bonded to a substrate |
| CN101325154A (en) * | 2008-07-16 | 2008-12-17 | 中国科学院上海微系统与信息技术研究所 | Germanium-painting structure for insulating layer of mixed graphical monocrystaline silicon as well as method and application thereof |
-
2011
- 2011-11-16 CN CN201110361523.5A patent/CN102593039B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070081169A1 (en) * | 2005-10-12 | 2007-04-12 | Sematch Inc. | Methods for characterizing semiconductor material using optical metrology |
| CN101292342A (en) * | 2005-10-19 | 2008-10-22 | Soi科技公司 | Treating a germanium layer bonded to a substrate |
| CN101325154A (en) * | 2008-07-16 | 2008-12-17 | 中国科学院上海微系统与信息技术研究所 | Germanium-painting structure for insulating layer of mixed graphical monocrystaline silicon as well as method and application thereof |
Non-Patent Citations (1)
| Title |
|---|
| 肖哲: "晶圆级机械致单轴应变Si技术研究", 《中国优秀硕士学位论文全文数据库》 * |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103065938A (en) * | 2012-12-31 | 2013-04-24 | 中国科学院上海微系统与信息技术研究所 | Method for preparing direct band-gap germanium thin film |
| CN103065938B (en) * | 2012-12-31 | 2015-06-10 | 中国科学院上海微系统与信息技术研究所 | Method for preparing direct band-gap germanium thin film |
| CN103094099A (en) * | 2013-01-14 | 2013-05-08 | 陆伟 | Method of wafer annealing after bonding |
| CN105977198A (en) * | 2016-06-20 | 2016-09-28 | 西安电子科技大学 | Amorphization and scale effect-based manufacturing method of wafer-level uniaxial strain Ge on SiN buried insulating layer |
| CN105938811A (en) * | 2016-06-20 | 2016-09-14 | 西安电子科技大学 | Manufacturing method for wafer level uniaxial strain SOI based on noncrystallization and scale effect |
| CN105938809A (en) * | 2016-06-20 | 2016-09-14 | 西安电子科技大学 | Manufacturing method for wafer level uniaxial strain Si on SiN-buried insulating layer based on noncrystallization and scale effect |
| CN105845617A (en) * | 2016-06-20 | 2016-08-10 | 西安电子科技大学 | Manufacturing method for AlN buried insulating layer wafer level uniaxial strain Ge based on non-crystallization and scale effect |
| CN105977199A (en) * | 2016-06-20 | 2016-09-28 | 西安电子科技大学 | Amorphization and scale effect-based manufacturing method of wafer-level uniaxial strain GeOI |
| CN105977197A (en) * | 2016-06-20 | 2016-09-28 | 西安电子科技大学 | Amorphization and scale effect-based manufacturing method of wafer-level uniaxial strain SiGe on SiN buried insulating layer |
| CN105845617B (en) * | 2016-06-20 | 2018-08-24 | 西安电子科技大学 | Production method based on wafer scale uniaxial strain Ge on the decrystallized AlN enterrees with scale effect |
| CN105977199B (en) * | 2016-06-20 | 2018-09-11 | 西安电子科技大学 | Based on the decrystallized production method with the wafer scale uniaxial strain GeOI of scale effect |
| CN105977197B (en) * | 2016-06-20 | 2018-09-11 | 西安电子科技大学 | Production method based on wafer scale uniaxial strain SiGe on the decrystallized SiN enterrees with scale effect |
| CN105938811B (en) * | 2016-06-20 | 2019-01-29 | 西安电子科技大学 | Based on the decrystallized production method with the wafer scale uniaxial strain SOI of scale effect |
| CN105977198B (en) * | 2016-06-20 | 2019-01-29 | 西安电子科技大学 | Production method based on wafer scale uniaxial strain Ge on the decrystallized SiN enterree with scale effect |
| CN105938809B (en) * | 2016-06-20 | 2019-01-29 | 西安电子科技大学 | Production method based on wafer scale uniaxial strain Si on the decrystallized SiN enterree with scale effect |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102593039B (en) | 2014-12-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102593039B (en) | Manufacturing method for mechanically actuated uniaxial strain GeOI wafer based on AlN embedded insulating layer | |
| US8440129B2 (en) | Production of free-standing solid state layers by thermal processing of substrates with a polymer | |
| Werner et al. | From polycrystalline to single crystalline silicon on glass | |
| TW474012B (en) | Semiconductor substrate and its production method, semiconductor device containing this substrate and its production method | |
| US6562127B1 (en) | Method of making mosaic array of thin semiconductor material of large substrates | |
| CN101256934B (en) | Method for manufacturing semiconductor substrate | |
| CN105684132B (en) | Mitigate the amorphous Si O of stress2Middle layer | |
| US10748989B2 (en) | Insulating layer structure for semiconductor product, and preparation method of insulating layer structure | |
| WO2007142865A2 (en) | Thin film photovoltaic structure and fabrication | |
| CN102403259B (en) | Manufacturing method of single-shaft strain GeOI wafer based on mechanical bending table | |
| CN102569163B (en) | Manufacturing method of wafer-level uniaxial strain SOI (Silicon On Insulator) wafer based on AIN (Advanced Intelligent Network) buried insulating layer | |
| CN102403260B (en) | Method for manufacturing wafer uniaxial strain SOI based on SiN buried insulation layer | |
| CN102832104A (en) | Method for forming two device wafers from a single base substrate | |
| CN102543719B (en) | Manufacture method of uniaxial strain silicon germanium on insulator (SGOI) wafer on aluminum nitride (AIN) embedded insulating barrier based on mechanical bending table | |
| EP2804202B1 (en) | Method for manufacturing a thermally oxidized heterogeneous composite substrate | |
| CN102437086B (en) | Manufacturing method of mechanical uniaxial strain GeOI (germanium-on-insulator) wafer based on SiN buried insulating layer | |
| CN106531682A (en) | GeOI (Ge-on-insulator) structure and preparation method | |
| CN105977198B (en) | Production method based on wafer scale uniaxial strain Ge on the decrystallized SiN enterree with scale effect | |
| CN102347267A (en) | High-quality SGOI (SiGe-on insulator) produced by utilizing material with superlattice structure and production method of high-quality SGOI | |
| CN102437085B (en) | Manufacturing method of mechanical uniaxial strain SOI (silicon-on-insulator) wafer | |
| CN102437019B (en) | Manufacturing method of uniaxial strain SGOI (SiGe-on-Insulator) wafer on SiN buried insulating layer based on mechanical bending table | |
| CN102437054B (en) | Manufacturing method of wafer-level uniaxial strain silicon germanium on insulater (SGOI) | |
| CN109742012B (en) | Low-temperature microwave annealing method for improving photoelectric characteristics of silicon superlattice thin film | |
| CN107785304B (en) | SOI material with nitride film as insulating buried layer and preparation method thereof | |
| CN105845617B (en) | Production method based on wafer scale uniaxial strain Ge on the decrystallized AlN enterrees with scale effect |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141210 Termination date: 20191116 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |